--- /dev/null
+/** @file\r
+Contains root level name space objects for the platform\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+//\r
+// OS TYPE DEFINITION\r
+//\r
+#define WINDOWS_XP 0x01\r
+#define WINDOWS_XP_SP1 0x02\r
+#define WINDOWS_XP_SP2 0x04\r
+#define WINDOWS_2003 0x08\r
+#define WINDOWS_Vista 0x10\r
+#define WINDOWS_WIN7 0x11\r
+#define WINDOWS_WIN8 0x12\r
+#define WINDOWS_WIN8_1 0x13\r
+#define LINUX 0xF0\r
+\r
+//\r
+// GPIO Interrupt Connection Resource Descriptor (GpioInt) usage.\r
+// GpioInt() descriptors maybe used in this file and included .asi files.\r
+//\r
+// The mapping below was provided by the first OS user that requested\r
+// GpioInt() support.\r
+// Other OS users that need GpioInt() support must use the following mapping.\r
+//\r
+#define QUARK_GPIO8_MAPPING 0x00\r
+#define QUARK_GPIO9_MAPPING 0x01\r
+#define QUARK_GPIO_SUS0_MAPPING 0x02\r
+#define QUARK_GPIO_SUS1_MAPPING 0x03\r
+#define QUARK_GPIO_SUS2_MAPPING 0x04\r
+#define QUARK_GPIO_SUS3_MAPPING 0x05\r
+#define QUARK_GPIO_SUS4_MAPPING 0x06\r
+#define QUARK_GPIO_SUS5_MAPPING 0x07\r
+#define QUARK_GPIO0_MAPPING 0x08\r
+#define QUARK_GPIO1_MAPPING 0x09\r
+#define QUARK_GPIO2_MAPPING 0x0A\r
+#define QUARK_GPIO3_MAPPING 0x0B\r
+#define QUARK_GPIO4_MAPPING 0x0C\r
+#define QUARK_GPIO5_MAPPING 0x0D\r
+#define QUARK_GPIO6_MAPPING 0x0E\r
+#define QUARK_GPIO7_MAPPING 0x0F\r
+\r
+DefinitionBlock (\r
+ "Platform.aml",\r
+ "DSDT",\r
+ 1,\r
+ "INTEL ",\r
+ "QuarkNcSocId",\r
+ 3)\r
+{\r
+ //\r
+ // Global Variables\r
+ //\r
+ Name(\GPIC, 0x0)\r
+\r
+ //\r
+ // Port 80\r
+ //\r
+ OperationRegion (DBG0, SystemIO, 0x80, 1)\r
+ Field (DBG0, ByteAcc, NoLock, Preserve)\r
+ { IO80,8 }\r
+\r
+ //\r
+ // Access CMOS range\r
+ //\r
+ OperationRegion (ACMS, SystemIO, 0x72, 2)\r
+ Field (ACMS, ByteAcc, NoLock, Preserve)\r
+ { INDX, 8, DATA, 8 }\r
+\r
+ //\r
+ // Global NVS Memory Block\r
+ //\r
+ OperationRegion (MNVS, SystemMemory, 0xFFFF0000, 512)\r
+ Field (MNVS, ByteAcc, NoLock, Preserve)\r
+ {\r
+ OSTP, 32,\r
+ CFGD, 32,\r
+ HPEA, 32, // HPET Enabled ?\r
+\r
+ P1BB, 32, // Pm1blkIoBaseAddress;\r
+ PBAB, 32, // PmbaIoBaseAddress;\r
+ GP0B, 32, // Gpe0blkIoBaseAddress;\r
+ GPAB, 32, // GbaIoBaseAddress;\r
+\r
+ SMBB, 32, // SmbaIoBaseAddress;\r
+ NRV1, 32, // GNVS reserved field 1.\r
+ WDTB, 32, // WdtbaIoBaseAddress;\r
+\r
+ HPTB, 32, // HpetBaseAddress;\r
+ HPTS, 32, // HpetSize;\r
+ PEXB, 32, // PciExpressBaseAddress;\r
+ PEXS, 32, // PciExpressSize;\r
+\r
+ RCBB, 32, // RcbaMmioBaseAddress;\r
+ RCBS, 32, // RcbaMmioSize;\r
+ APCB, 32, // IoApicBaseAddress;\r
+ APCS, 32, // IoApicSize;\r
+\r
+ TPMP, 32, // TpmPresent ?\r
+ DBGP, 32, // DBG2 Present?\r
+ PTYP, 32, // Set to one of EFI_PLATFORM_TYPE enums.\r
+ ALTS, 32, // Use alternate I2c SLA addresses.\r
+ }\r
+\r
+ OperationRegion (GPEB, SystemIO, 0x1100, 0x40) //GPE Block\r
+ Field (GPEB, AnyAcc, NoLock, Preserve)\r
+ {\r
+ Offset(0x10),\r
+ SMIE, 32, // SMI Enable\r
+ SMIS, 32, // SMI Status\r
+ }\r
+\r
+ //\r
+ // Processor Objects\r
+ //\r
+ Scope(\_PR) {\r
+ //\r
+ // IO base will be updated at runtime with search key "PRIO"\r
+ //\r
+ Processor (CPU0, 0x01, 0x4F495250, 0x06) {}\r
+ }\r
+\r
+ //\r
+ // System Sleep States\r
+ //\r
+ Name (\_S0,Package (){0,0,0,0})\r
+ Name (\_S3,Package (){5,0,0,0})\r
+ Name (\_S4,Package (){6,0,0,0})\r
+ Name (\_S5,Package (){7,0,0,0})\r
+\r
+ //\r
+ // General Purpose Event\r
+ //\r
+ Scope(\_GPE)\r
+ {\r
+ //\r
+ // EGPE generated GPE\r
+ //\r
+ Method(_L0D, 0x0, NotSerialized)\r
+ {\r
+ //\r
+ // Check EGPE for this wake event\r
+ //\r
+ Notify (\_SB.SLPB, 0x02)\r
+\r
+ }\r
+\r
+ //\r
+ // GPIO generated GPE\r
+ //\r
+ Method(_L0E, 0x0, NotSerialized)\r
+ {\r
+ //\r
+ // Check GPIO for this wake event\r
+ //\r
+ Notify (\_SB.PWRB, 0x02)\r
+\r
+ }\r
+\r
+ //\r
+ // SCLT generated GPE\r
+ //\r
+ Method(_L0F, 0x0, NotSerialized)\r
+ {\r
+ //\r
+ // Check SCLT for this wake event\r
+ //\r
+ Notify (\_SB.PCI0.SDIO, 0x02)\r
+ Notify (\_SB.PCI0.URT0, 0x02)\r
+ Notify (\_SB.PCI0.USBD, 0x02)\r
+ Notify (\_SB.PCI0.EHCI, 0x02)\r
+ Notify (\_SB.PCI0.OHCI, 0x02)\r
+ Notify (\_SB.PCI0.URT1, 0x02)\r
+ Notify (\_SB.PCI0.ENT0, 0x02)\r
+ Notify (\_SB.PCI0.ENT1, 0x02)\r
+ Notify (\_SB.PCI0.SPI0, 0x02)\r
+ Notify (\_SB.PCI0.SPI1, 0x02)\r
+ Notify (\_SB.PCI0.GIP0, 0x02)\r
+\r
+ }\r
+\r
+ //\r
+ // Remote Management Unit generated GPE\r
+ //\r
+ Method(_L10, 0x0, NotSerialized)\r
+ {\r
+ //\r
+ // Check Remote Management Unit for this wake event.\r
+ //\r
+ }\r
+\r
+ //\r
+ // PCIE generated GPE\r
+ //\r
+ Method(_L11, 0x0, NotSerialized)\r
+ {\r
+ //\r
+ // Check PCIE for this wake event\r
+ //\r
+ Notify (\_SB.PCI0.PEX0, 0x02)\r
+ Notify (\_SB.PCI0.PEX1, 0x02)\r
+ }\r
+ }\r
+\r
+ //\r
+ // define Sleeping button as mentioned in ACPI spec 2.0\r
+ //\r
+ Device (\_SB.SLPB)\r
+ {\r
+ Name (_HID, EISAID ("PNP0C0E"))\r
+ Method (_PRW, 0, NotSerialized)\r
+ {\r
+ Return (Package (0x02) {0x0D,0x04})\r
+ }\r
+ }\r
+\r
+ //\r
+ // define Power Button\r
+ //\r
+ Device (\_SB.PWRB)\r
+ {\r
+ Name (_HID, EISAID ("PNP0C0C"))\r
+ Method (_PRW, 0, NotSerialized)\r
+ {\r
+ Return (Package (0x02) {0x0E,0x04})\r
+ }\r
+ }\r
+ //\r
+ // System Wake up\r
+ //\r
+ Method(_WAK, 1, Serialized)\r
+ {\r
+ // Do nothing here\r
+ Return (0)\r
+ }\r
+\r
+ //\r
+ // System sleep down\r
+ //\r
+ Method (_PTS, 1, NotSerialized)\r
+ {\r
+ // Get ready for S3 sleep\r
+ if (Lequal(Arg0,3))\r
+ {\r
+ Store(0xffffffff,SMIS) // clear SMI status\r
+ Store(SMIE, Local0) // SMI Enable\r
+ Or(Local0,0x4,SMIE) // Generate SMI on sleep\r
+ }\r
+ }\r
+\r
+ //\r
+ // Determing PIC mode\r
+ //\r
+ Method(\_PIC, 1, NotSerialized)\r
+ {\r
+ Store(Arg0,\GPIC)\r
+ }\r
+\r
+ //\r
+ // System Bus\r
+ //\r
+ Scope(\_SB)\r
+ {\r
+ Device(PCI0)\r
+ {\r
+ Name(_HID,EISAID ("PNP0A08")) // PCI Express Root Bridge\r
+ Name(_CID,EISAID ("PNP0A03")) // Compatible PCI Root Bridge\r
+\r
+ Name(_ADR,0x00000000) // Device (HI WORD)=0, Func (LO WORD)=0\r
+ Method (_INI)\r
+ {\r
+ Store(LINUX, OSTP) // Set the default os is Linux\r
+ If (CondRefOf (_OSI, local0))\r
+ {\r
+ //\r
+ //_OSI is supported, so it is WinXp or Win2003Server\r
+ //\r
+ If (\_OSI("Windows 2001"))\r
+ {\r
+ Store (WINDOWS_XP, OSTP)\r
+ }\r
+ If (\_OSI("Windows 2001 SP1"))\r
+ {\r
+ Store (WINDOWS_XP_SP1, OSTP)\r
+ }\r
+ If (\_OSI("Windows 2001 SP2"))\r
+ {\r
+ Store (WINDOWS_XP_SP2, OSTP)\r
+ }\r
+ If (\_OSI("Windows 2001.1"))\r
+ {\r
+ Store (WINDOWS_2003, OSTP)\r
+ }\r
+ If (\_OSI("Windows 2006"))\r
+ {\r
+ Store (WINDOWS_Vista, OSTP)\r
+ }\r
+ If (\_OSI("Windows 2009"))\r
+ {\r
+ Store (WINDOWS_WIN7, OSTP)\r
+ }\r
+ If (\_OSI("Windows 2012"))\r
+ {\r
+ Store (WINDOWS_WIN8, OSTP)\r
+ }\r
+ If (\_OSI("Windows 2013"))\r
+ {\r
+ Store (WINDOWS_WIN8_1, OSTP)\r
+ }\r
+ If (\_OSI("Linux"))\r
+ {\r
+ Store (LINUX, OSTP)\r
+ }\r
+ }\r
+ }\r
+\r
+ Include ("PciHostBridge.asi") // PCI0 Host bridge\r
+ Include ("QNC.asi") // QNC miscellaneous\r
+ Include ("PcieExpansionPrt.asi") // PCIe expansion bridges/devices\r
+ Include ("QuarkSouthCluster.asi") // Quark South Cluster devices\r
+ Include ("QNCLpc.asi") // LPC bridge device\r
+ Include ("QNCApic.asi") // QNC I/O Apic device\r
+\r
+ }\r
+\r
+ //\r
+ // Include asi files for I2C and SPI onboard devices.\r
+ // Devices placed here instead of below relevant controllers.\r
+ // Hardware topology information is maintained by the\r
+ // ResourceSource arg to the I2CSerialBus/SPISerialBus macros\r
+ // within the device asi files.\r
+ //\r
+ Include ("Tpm.asi") // TPM device.\r
+ Include ("CY8C9540A.asi") // CY8C9540A 40Bit I/O Expander & EEPROM\r
+ Include ("PCAL9555A.asi") // NXP PCAL9555A I/O expander.\r
+ Include ("PCA9685.asi") // NXP PCA9685 PWM/LED controller.\r
+ Include ("CAT24C08.asi") // ONSEMI CAT24C08 I2C 8KB EEPROM.\r
+ Include ("AD7298.asi") // Analog devices AD7298 ADC.\r
+ Include ("ADC108S102.asi") // TI ADC108S102 ADC.\r
+ Include ("GpioClient.asi") // Software device to expose GPIO\r
+ }\r
+}\r
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