+++ /dev/null
-/** @file\r
-\r
-Processor power management initialization code.\r
-\r
-Copyright (c) 2013-2015 Intel Corporation.\r
-\r
-SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
-\r
-**/\r
-\r
-#ifndef _PPM_H\r
-#define _PPM_H\r
-\r
-//\r
-// Bit definitions of PPMFlags\r
-//\r
-#define PPM_GV3 (1 << 0) // Geyserville 3\r
-#define PPM_TURBO (1 << 1) // Turbo Mode\r
-#define PPM_SUPER_LFM (1 << 2) // N/2 Ratio\r
-#define PPM_C1 (1 << 4) // C1 Capable, Enabled\r
-#define PPM_C2 (1 << 5) // C2 Capable, Enabled\r
-#define PPM_C3 (1 << 6) // C3 Capable, Enabled\r
-#define PPM_C4 (1 << 7) // C4 Capable, Enabled\r
-#define PPM_C5 (1 << 8) // C5/Deep C4 Capable, Enabled\r
-#define PPM_C6 (1 << 9) // C6 Capable, Enabled\r
-#define PPM_C1E (1 << 10) // C1E Enabled\r
-#define PPM_C2E (1 << 11) // C2E Enabled\r
-#define PPM_C3E (1 << 12) // C3E Enabled\r
-#define PPM_C4E (1 << 13) // C4E Enabled\r
-#define PPM_HARD_C4E (1 << 14) // Hard C4E Capable, Enabled\r
-#define PPM_TM1 (1 << 16) // Thermal Monitor 1\r
-#define PPM_TM2 (1 << 17) // Thermal Monitor 2\r
-#define PPM_PHOT (1 << 19) // Bi-directional ProcHot\r
-#define PPM_MWAIT_EXT (1 << 21) // MWAIT extensions supported\r
-#define PPM_CMP (1 << 24) // CMP supported, Enabled\r
-#define PPM_TSTATE (1 << 28) // CPU T states supported\r
-\r
-#define PPM_C_STATES (PPM_C1 + PPM_C2 + PPM_C3 + PPM_C4 + PPM_C5 + PPM_C6)\r
-#define PPM_CE_STATES (PPM_C1E + PPM_C2E + PPM_C3E + PPM_C4E + PPM_HARD_C4E)\r
-\r
-\r
-#define MAX_P_STATES_NUM 12\r
-\r
-#define AML_NAME_OP 0x08\r
-#define AML_SCOPE_OP 0x10\r
-#define AML_PACKAGE_OP 0x12\r
-#define AML_METHOD_OP 0x14\r
-\r
-#define S3_CPU_REGISTER_TABLE_GUID \\r
- { \\r
- 0xc4ef988d, 0xe5e, 0x4403, { 0xbe, 0xeb, 0xf1, 0xbb, 0x6, 0x79, 0x6e, 0xdf } \\r
- }\r
-\r
-#pragma pack(1)\r
-typedef struct {\r
- UINT8 StartByte;\r
- UINT32 NameStr;\r
- UINT8 OpCode;\r
- UINT16 Size; // Hardcode to 16bit width because the table we use is fixed size\r
- UINT8 NumEntries;\r
-} EFI_ACPI_NAME_COMMAND;\r
-\r
-typedef struct {\r
- UINT8 PackageOp;\r
- UINT8 PkgLeadByte;\r
- UINT8 NumEntries;\r
- UINT8 DwordPrefix0;\r
- UINT32 CoreFreq;\r
- UINT8 DwordPrefix1;\r
- UINT32 Power;\r
- UINT8 DwordPrefix2;\r
- UINT32 TransLatency;\r
- UINT8 DwordPrefix3;\r
- UINT32 BMLatency;\r
- UINT8 DwordPrefix4;\r
- UINT32 Control;\r
- UINT8 DwordPrefix5;\r
- UINT32 Status;\r
-} EFI_PSS_PACKAGE;\r
-#pragma pack()\r
-\r
-typedef struct {\r
- UINT32 Index;\r
- UINT64 Value;\r
-} S3_CPU_REGISTER;\r
-\r
-//\r
-// Function prototypes\r
-//\r
-\r
-/**\r
- This function is the entry of processor power management initialization code.\r
- It initializes the processor's power management features based on the user\r
- configurations and hardware capablities.\r
-**/\r
-VOID\r
-PpmInit (\r
- VOID\r
- );\r
-\r
-/**\r
- This function is to determine the Processor Power Management Flags\r
- based on the hardware capability.\r
-**/\r
-VOID\r
-PpmDetectCapability (\r
- VOID\r
- );\r
-\r
-/**\r
- This function is to determine the user configuration mask\r
-**/\r
-VOID\r
-PpmGetUserConfigurationMask (\r
- VOID\r
- );\r
-\r
-/**\r
- This function is to patch and publish power management related acpi tables.\r
-**/\r
-VOID\r
-PpmPatchAndPublishAcpiTables (\r
- VOID\r
- );\r
-\r
-/**\r
- This function is to patch PLvl2Lat and PLvl3Lat to enable C2, C3 support in OS.\r
-**/\r
-VOID\r
-PpmPatchFadtTable (\r
- VOID\r
- );\r
-\r
-/**\r
- This function is to load all the power management acpi tables and patch IST table.\r
-**/\r
-VOID\r
-PpmLoadAndPatchPMTables (\r
- VOID\r
- );\r
-\r
-/**\r
- This function is to save cpu registers for s3 resume.\r
-**/\r
-VOID\r
-PpmS3SaveRegisters (\r
- VOID\r
- );\r
-#endif\r