]> git.proxmox.com Git - mirror_edk2.git/blobdiff - QuarkPlatformPkg/Feature/Capsule/Library/PlatformFlashAccessLib/SpiFlashDevice.c
projects / mirror_edk2.git / blobdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | inline | side by side
QuarkPlatformPkg/PlatformFlashAccessLib: Add instance for update.
[mirror_edk2.git] / QuarkPlatformPkg / Feature / Capsule / Library / PlatformFlashAccessLib / SpiFlashDevice.c
diff --git a/QuarkPlatformPkg/Feature/Capsule/Library/PlatformFlashAccessLib/SpiFlashDevice.c b/QuarkPlatformPkg/Feature/Capsule/Library/PlatformFlashAccessLib/SpiFlashDevice.c
new file mode 100644 (file)
index 0000000..e2827b9
--- /dev/null
+++ b/QuarkPlatformPkg/Feature/Capsule/Library/PlatformFlashAccessLib/SpiFlashDevice.c
@@ -0,0 +1,336 @@
+/** @file\r
+  SPI flash device description.\r
+\r
+  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+  This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+#include "SpiFlashDevice.h"\r
+\r
+#define FLASH_SIZE  (FixedPcdGet32 (PcdFlashAreaSize))\r
+\r
+SPI_INIT_TABLE  mSpiInitTable[] = {\r
+  //\r
+  // Macronix 32Mbit part\r
+  //\r
+  {\r
+    SPI_MX25L3205_ID1,\r
+    SPI_MX25L3205_ID2,\r
+    SPI_MX25L3205_ID3,\r
+    {\r
+      SPI_COMMAND_WRITE_ENABLE,\r
+      SPI_COMMAND_WRITE_S_EN\r
+    },\r
+    {\r
+      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle33MHz, EnumSpiOperationJedecId},\r
+      {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle33MHz, EnumSpiOperationOther},\r
+      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},\r
+      {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},\r
+      {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle20MHz, EnumSpiOperationReadData},\r
+      {EnumSpiOpcodeWrite,       SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},\r
+      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle33MHz, EnumSpiOperationReadStatus},\r
+      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}\r
+    },\r
+    (UINTN)(0x400000 - FLASH_SIZE), // BIOS Start Offset\r
+    FLASH_SIZE   // BIOS image size in flash\r
+  },\r
+  //\r
+  // Winbond 32Mbit part\r
+  //\r
+  {\r
+    SPI_W25X32_ID1,\r
+    SF_DEVICE_ID0_W25QXX,\r
+    SF_DEVICE_ID1_W25Q32,\r
+    {\r
+      SPI_COMMAND_WRITE_ENABLE,\r
+      SPI_COMMAND_WRITE_S_EN\r
+    },\r
+    {\r
+      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r
+      {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle50MHz, EnumSpiOperationOther},\r
+      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r
+      {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r
+      {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle50MHz, EnumSpiOperationReadData},\r
+      {EnumSpiOpcodeWrite,       SPI_COMMAND_ERASE,       EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},\r
+      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r
+      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r
+    },\r
+    (UINTN)(0x400000 - FLASH_SIZE), // BIOS Start Offset\r
+    FLASH_SIZE   // BIOS image size in flash\r
+  },\r
+  //\r
+  // Winbond 32Mbit part\r
+  //\r
+  {\r
+    SPI_W25X32_ID1,\r
+    SPI_W25X32_ID2,\r
+    SPI_W25X32_ID3,\r
+    {\r
+      SPI_COMMAND_WRITE_ENABLE,\r
+      SPI_COMMAND_WRITE_S_EN\r
+    },\r
+    {\r
+      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle33MHz, EnumSpiOperationJedecId},\r
+      {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle33MHz, EnumSpiOperationOther},\r
+      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},\r
+      {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},\r
+      {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle33MHz, EnumSpiOperationReadData},\r
+      {EnumSpiOpcodeWrite,       SPI_COMMAND_ERASE,       EnumSpiCycle33MHz, EnumSpiOperationErase_4K_Byte},\r
+      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle33MHz, EnumSpiOperationReadStatus},\r
+      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}\r
+    },\r
+    (UINTN)(0x400000 - FLASH_SIZE), // BIOS Start Offset\r
+    FLASH_SIZE   // BIOS image size in flash\r
+  },\r
+  //\r
+  // Atmel 32Mbit part\r
+  //\r
+  {\r
+    SPI_AT26DF321_ID1,\r
+    SPI_AT26DF321_ID2,  // issue: byte 2 identifies family/density for Atmel\r
+    SPI_AT26DF321_ID3,\r
+    {\r
+      SPI_COMMAND_WRITE_ENABLE,\r
+      SPI_COMMAND_WRITE_S_EN\r
+    },\r
+    {\r
+      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle33MHz, EnumSpiOperationJedecId},\r
+      {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle33MHz, EnumSpiOperationOther},\r
+      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},\r
+      {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},\r
+      {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle33MHz, EnumSpiOperationReadData},\r
+      {EnumSpiOpcodeWrite,       SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},\r
+      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle33MHz, EnumSpiOperationReadStatus},\r
+      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}\r
+    },\r
+    (UINTN)(0x400000 - FLASH_SIZE), // BIOS Start Offset\r
+    FLASH_SIZE   // BIOS image size in flash\r
+  },\r
+\r
+  //\r
+  // Intel 32Mbit part bottom boot\r
+  //\r
+  {\r
+    SPI_QH25F320_ID1,\r
+    SPI_QH25F320_ID2,\r
+    SPI_QH25F320_ID3,\r
+    {\r
+      SPI_COMMAND_WRITE_ENABLE,\r
+      SPI_COMMAND_WRITE_ENABLE\r
+    },\r
+    {\r
+      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle33MHz, EnumSpiOperationJedecId},\r
+      {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle33MHz, EnumSpiOperationOther},\r
+      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},\r
+      {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},\r
+      {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle33MHz, EnumSpiOperationReadData},\r
+      {EnumSpiOpcodeWrite,       SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},\r
+      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle33MHz, EnumSpiOperationReadStatus},\r
+      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}\r
+    },\r
+    0,           // BIOS Start Offset\r
+    FLASH_SIZE   // BIOS image size in flash\r
+  },\r
+  //\r
+  // SST 64Mbit part\r
+  //\r
+  {\r
+    SPI_SST25VF080B_ID1,      // VendorId\r
+    SF_DEVICE_ID0_25VF064C,   // DeviceId 0\r
+    SF_DEVICE_ID1_25VF064C,   // DeviceId 1\r
+    {\r
+      SPI_COMMAND_WRITE_ENABLE,\r
+      SPI_COMMAND_WRITE_S_EN\r
+    },\r
+    {\r
+      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r
+      {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle50MHz, EnumSpiOperationOther},\r
+      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r
+      {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r
+      {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle50MHz, EnumSpiOperationReadData},\r
+      {EnumSpiOpcodeWrite,       SPI_COMMAND_ERASE,       EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},\r
+      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r
+      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r
+    },\r
+    0x800000 - FLASH_SIZE,          // BIOS Start Offset\r
+    FLASH_SIZE   // BIOS image size in flash\r
+  },\r
+  //\r
+  // NUMONYX 64Mbit part\r
+  //\r
+  {\r
+    SF_VENDOR_ID_NUMONYX,     // VendorId\r
+    SF_DEVICE_ID0_M25PX64,    // DeviceId 0\r
+    SF_DEVICE_ID1_M25PX64,    // DeviceId 1\r
+    {\r
+      SPI_COMMAND_WRITE_ENABLE,\r
+      SPI_COMMAND_WRITE_S_EN\r
+    },\r
+    {\r
+      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r
+      {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle50MHz, EnumSpiOperationOther},\r
+      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r
+      {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r
+      {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle50MHz, EnumSpiOperationReadData},\r
+      {EnumSpiOpcodeWrite,       SPI_COMMAND_ERASE,       EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},\r
+      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r
+      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r
+    },\r
+    0x800000 - FLASH_SIZE,          // BIOS Start Offset\r
+    FLASH_SIZE   // BIOS image size in flash\r
+  },\r
+  //\r
+  // Atmel 64Mbit part\r
+  //\r
+  {\r
+    SF_VENDOR_ID_ATMEL,       // VendorId\r
+    SF_DEVICE_ID0_AT25DF641,  // DeviceId 0\r
+    SF_DEVICE_ID1_AT25DF641,  // DeviceId 1\r
+    {\r
+      SPI_COMMAND_WRITE_ENABLE,\r
+      SPI_COMMAND_WRITE_S_EN\r
+    },\r
+    {\r
+      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r
+      {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle50MHz, EnumSpiOperationOther},\r
+      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r
+      {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r
+      {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle50MHz, EnumSpiOperationReadData},\r
+      {EnumSpiOpcodeWrite,       SPI_COMMAND_ERASE,       EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},\r
+      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r
+      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r
+    },\r
+    0x800000 - FLASH_SIZE,          // BIOS Start Offset\r
+    FLASH_SIZE   // BIOS image size in flash\r
+  },\r
+\r
+  //\r
+  // Spansion 64Mbit part\r
+  //\r
+  {\r
+    SF_VENDOR_ID_SPANSION,       // VendorId\r
+    SF_DEVICE_ID0_S25FL064K,  // DeviceId 0\r
+    SF_DEVICE_ID1_S25FL064K,  // DeviceId 1\r
+    {\r
+      SPI_COMMAND_WRITE_ENABLE,\r
+      SPI_COMMAND_WRITE_S_EN\r
+    },\r
+    {\r
+      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r
+      {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle50MHz, EnumSpiOperationOther},\r
+      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r
+      {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r
+      {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle50MHz, EnumSpiOperationReadData},\r
+      {EnumSpiOpcodeWrite,       SPI_COMMAND_ERASE,       EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},\r
+      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r
+      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r
+    },\r
+    0x800000 - FLASH_SIZE,          // BIOS Start Offset\r
+    FLASH_SIZE   // BIOS image size in flash\r
+  },\r
+\r
+  //\r
+  // Macronix 64Mbit part bottom boot\r
+  //\r
+  {\r
+    SF_VENDOR_ID_MX,          // VendorId\r
+    SF_DEVICE_ID0_25L6405D,   // DeviceId 0\r
+    SF_DEVICE_ID1_25L6405D,   // DeviceId 1\r
+    {\r
+      SPI_COMMAND_WRITE_ENABLE,\r
+      SPI_COMMAND_WRITE_S_EN\r
+    },\r
+    {\r
+      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r
+      {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle50MHz, EnumSpiOperationOther},\r
+      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r
+      {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r
+      {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle50MHz, EnumSpiOperationReadData},\r
+      {EnumSpiOpcodeWrite,       SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte},\r
+      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r
+      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r
+    },\r
+    0x800000 - FLASH_SIZE,          // BIOS Start Offset\r
+    FLASH_SIZE   // BIOS image size in flash\r
+  },\r
+  //\r
+  // Winbond 64Mbit part bottom boot\r
+  //\r
+  {\r
+    SPI_W25X64_ID1,\r
+    SF_DEVICE_ID0_W25QXX,\r
+    SF_DEVICE_ID1_W25Q64,\r
+    {\r
+      SPI_COMMAND_WRITE_ENABLE,\r
+      SPI_COMMAND_WRITE_S_EN\r
+    },\r
+    {\r
+      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r
+      {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle50MHz, EnumSpiOperationOther},\r
+      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r
+      {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r
+      {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle50MHz, EnumSpiOperationReadData},\r
+      {EnumSpiOpcodeWrite,       SPI_COMMAND_ERASE,       EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},\r
+      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r
+      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r
+    },\r
+    0x800000 - FLASH_SIZE,          // BIOS Start Offset\r
+    FLASH_SIZE   // BIOS image size in flash\r
+  },\r
+  //\r
+  // Winbond 64Mbit part bottom boot\r
+  //\r
+  {\r
+    SPI_W25X64_ID1,\r
+    SPI_W25X64_ID2,\r
+    SPI_W25X64_ID3,\r
+    {\r
+      SPI_COMMAND_WRITE_ENABLE,\r
+      SPI_COMMAND_WRITE_S_EN\r
+    },\r
+    {\r
+      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r
+      {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle50MHz, EnumSpiOperationOther},\r
+      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r
+      {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r
+      {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle50MHz, EnumSpiOperationReadData},\r
+      {EnumSpiOpcodeWrite,       SPI_COMMAND_ERASE,       EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},\r
+      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r
+      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r
+    },\r
+    0x800000 - FLASH_SIZE,          // BIOS Start Offset\r
+    FLASH_SIZE   // BIOS image size in flash\r
+  },\r
+  //\r
+  // Intel 64Mbit part bottom boot\r
+  //\r
+  {\r
+    SPI_QH25F640_ID1,\r
+    SPI_QH25F640_ID2,\r
+    SPI_QH25F640_ID3,\r
+    {\r
+      SPI_COMMAND_WRITE_ENABLE,\r
+      SPI_COMMAND_WRITE_S_EN\r
+    },\r
+    {\r
+      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle33MHz, EnumSpiOperationJedecId},\r
+      {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle33MHz, EnumSpiOperationOther},\r
+      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},\r
+      {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},\r
+      {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle33MHz, EnumSpiOperationReadData},\r
+      {EnumSpiOpcodeWrite,       SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},\r
+      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle33MHz, EnumSpiOperationReadStatus},\r
+      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}\r
+    },\r
+    0x800000 - FLASH_SIZE,          // BIOS Start Offset\r
+    FLASH_SIZE   // BIOS image size in flash\r
+  }\r
+};\r
EFI Development Kit II mirror for PVE