QuarkPlatformPkg: Add new package for Galileo boards

[mirror_edk2.git] / QuarkPlatformPkg / Library / PlatformPcieHelperLib / SocUnit.c

diff --git a/QuarkPlatformPkg/Library/PlatformPcieHelperLib/SocUnit.c b/QuarkPlatformPkg/Library/PlatformPcieHelperLib/SocUnit.c
new file mode 100644 (file)
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--- /dev/null
+++ b/QuarkPlatformPkg/Library/PlatformPcieHelperLib/SocUnit.c
@@ -0,0 +1,131 @@
+/** @file\r
+System On Chip Unit (SOCUnit) routines.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "CommonHeader.h"\r
+\r
+/** Early initialisation of the SOC Unit\r
+\r
+  @retval   EFI_SUCCESS               Operation success.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SocUnitEarlyInitialisation (\r
+  VOID\r
+  )\r
+{\r
+  UINT32      NewValue;\r
+\r
+  //\r
+  // Set the mixer load resistance\r
+  //\r
+  NewValue = QNCPortIORead (QUARK_SC_PCIE_AFE_SB_PORT_ID, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L0);\r
+  NewValue &= OCFGPIMIXLOAD_1_0_MASK;\r
+  QNCPortIOWrite (QUARK_SC_PCIE_AFE_SB_PORT_ID, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L0, NewValue);\r
+\r
+  NewValue = QNCPortIORead (QUARK_SC_PCIE_AFE_SB_PORT_ID, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L1);\r
+  NewValue &= OCFGPIMIXLOAD_1_0_MASK;\r
+  QNCPortIOWrite (QUARK_SC_PCIE_AFE_SB_PORT_ID, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L1, NewValue);\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/** Tasks to release PCI controller from reset pre wait for PLL Lock.\r
+\r
+  @retval   EFI_SUCCESS               Operation success.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SocUnitReleasePcieControllerPreWaitPllLock (\r
+  IN CONST EFI_PLATFORM_TYPE              PlatformType\r
+  )\r
+{\r
+  UINT32      NewValue;\r
+\r
+  //\r
+  // Assert PERST# and validate time assertion time.\r
+  //\r
+  PlatformPERSTAssert (PlatformType);\r
+  ASSERT (PCIEXP_PERST_MIN_ASSERT_US <= (PCIEXP_DELAY_US_POST_CMNRESET_RESET + PCIEXP_DELAY_US_WAIT_PLL_LOCK + PCIEXP_DELAY_US_POST_SBI_RESET));\r
+\r
+  //\r
+  // PHY Common lane reset.\r
+  //\r
+  NewValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG);\r
+  NewValue |= SOCCLKEN_CONFIG_PHY_I_CMNRESET_L;\r
+  QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, NewValue);\r
+\r
+  //\r
+  // Wait post common lane reset.\r
+  //\r
+  MicroSecondDelay (PCIEXP_DELAY_US_POST_CMNRESET_RESET);\r
+\r
+  //\r
+  // PHY Sideband interface reset.\r
+  // Controller main reset\r
+  //\r
+  NewValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG);\r
+  NewValue |= (SOCCLKEN_CONFIG_SBI_RST_100_CORE_B | SOCCLKEN_CONFIG_PHY_I_SIDE_RST_L);\r
+  QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, NewValue);\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/** Tasks to release PCI controller from reset after PLL has locked\r
+\r
+  @retval   EFI_SUCCESS               Operation success.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SocUnitReleasePcieControllerPostPllLock (\r
+  IN CONST EFI_PLATFORM_TYPE              PlatformType\r
+  )\r
+{\r
+  UINT32 NewValue;\r
+\r
+  //\r
+  // Controller sideband interface reset.\r
+  //\r
+  NewValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG);\r
+  NewValue |= SOCCLKEN_CONFIG_SBI_BB_RST_B;\r
+  QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, NewValue);\r
+\r
+  //\r
+  // Wait post sideband interface reset.\r
+  //\r
+  MicroSecondDelay (PCIEXP_DELAY_US_POST_SBI_RESET);\r
+\r
+  //\r
+  // Deassert PERST#.\r
+  //\r
+  PlatformPERSTDeAssert (PlatformType);\r
+\r
+  //\r
+  // Wait post de assert PERST#.\r
+  //\r
+  MicroSecondDelay (PCIEXP_DELAY_US_POST_PERST_DEASSERT);\r
+\r
+  //\r
+  // Controller primary interface reset.\r
+  //\r
+  NewValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG);\r
+  NewValue |= SOCCLKEN_CONFIG_BB_RST_B;\r
+  QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, NewValue);\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r