QuarkPlatformPkg: Add new package for Galileo boards

[mirror_edk2.git] / QuarkPlatformPkg / Pci / Dxe / PciHostBridge / PciHostBridgeSupport.c

diff --git a/QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciHostBridgeSupport.c b/QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciHostBridgeSupport.c
new file mode 100644 (file)
index 0000000..24f719f
--- /dev/null
+++ b/QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciHostBridgeSupport.c
@@ -0,0 +1,146 @@
+/** @file\r
+Do platform initialization for PCI bridge.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+#include "PciHostBridge.h"\r
+\r
+EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *mPciRootBridgeIo;\r
+\r
+EFI_STATUS\r
+ChipsetPreprocessController (\r
+  IN  EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL          *This,\r
+  IN  EFI_HANDLE                                                RootBridgeHandle,\r
+  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS               PciAddress,\r
+  IN  EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE              Phase\r
+  )\r
+/*++\r
+\r
+Routine Description:\r
+  This function is called for all the PCI controllers that the PCI\r
+  bus driver finds. Can be used to Preprogram the controller.\r
+\r
+Arguments:\r
+  This             -- The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance\r
+  RootBridgeHandle -- The PCI Root Bridge handle\r
+  PciBusAddress    -- Address of the controller on the PCI bus\r
+  Phase            -- The Phase during resource allocation\r
+\r
+Returns:\r
+  EFI_SUCCESS\r
+\r
+--*/\r
+\r
+// GC_TODO:    PciAddress - add argument and description to function comment\r
+//\r
+// GC_TODO:    PciAddress - add argument and description to function comment\r
+//\r
+// GC_TODO:    PciAddress - add argument and description to function comment\r
+//\r
+// GC_TODO:    PciAddress - add argument and description to function comment\r
+//\r
+{\r
+\r
+  EFI_STATUS  Status;\r
+  UINT8       Latency;\r
+  UINT8       CacheLineSize;\r
+\r
+  if (mPciRootBridgeIo == NULL) {\r
+    //\r
+    // Get root bridge in the system.\r
+    //\r
+    Status = gBS->HandleProtocol (RootBridgeHandle, &gEfiPciRootBridgeIoProtocolGuid, (VOID **) &mPciRootBridgeIo);\r
+    ASSERT_EFI_ERROR (Status);\r
+  }\r
+\r
+  if (Phase == EfiPciBeforeResourceCollection) {\r
+    //\r
+    // Program the latency register, CLS register\r
+    //\r
+    PciAddress.Register = PCI_LATENCY_TIMER_OFFSET;\r
+    mPciRootBridgeIo->Pci.Read (\r
+                            mPciRootBridgeIo,\r
+                            EfiPciWidthUint8,\r
+                            *((UINT64 *) &PciAddress),\r
+                            1,\r
+                            &Latency\r
+                            );\r
+\r
+    //\r
+    // PCI-x cards come up with a default latency of 0x40. Don't touch them.\r
+    //\r
+    if (Latency == 0) {\r
+      Latency = DEFAULT_PCI_LATENCY;\r
+      mPciRootBridgeIo->Pci.Write (\r
+                              mPciRootBridgeIo,\r
+                              EfiPciWidthUint8,\r
+                              *((UINT64 *) &PciAddress),\r
+                              1,\r
+                              &Latency\r
+                              );\r
+    }\r
+    //\r
+    // Program Cache Line Size as 64bytes\r
+    // 16 of DWORDs = 64bytes (0x10)\r
+    //\r
+    PciAddress.Register = PCI_CACHELINE_SIZE_OFFSET;\r
+    CacheLineSize       = 0x10;\r
+    mPciRootBridgeIo->Pci.Write (\r
+                            mPciRootBridgeIo,\r
+                            EfiPciWidthUint8,\r
+                            *((UINT64 *) &PciAddress),\r
+                            1,\r
+                            &CacheLineSize\r
+                            );\r
+\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+UINT64\r
+GetAllocAttributes (\r
+  IN  UINTN        RootBridgeIndex\r
+  )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+  Returns the Allocation attributes for the BNB Root Bridge.\r
+\r
+Arguments:\r
+\r
+  RootBridgeIndex  -  The root bridge number. 0 based.\r
+\r
+Returns:\r
+\r
+  EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | EFI_PCI_HOST_BRIDGE_MEM64_DECODE\r
+\r
+--*/\r
+{\r
+  //\r
+  // Cannot have more than one Root bridge\r
+  //\r
+  //ASSERT (RootBridgeIndex == 0);\r
+\r
+  //\r
+  // PCI Root Bridge does not support separate windows for Non-prefetchable\r
+  // and Prefetchable memory. A PCI bus driver needs to include requests for\r
+  // Prefetchable memory in the Non-prefetchable memory pool.\r
+  // Further TNB does not support 64 bit memory apertures for PCI. BNB\r
+  // can only have system memory above 4 GB,\r
+  //\r
+\r
+    return EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | EFI_PCI_HOST_BRIDGE_MEM64_DECODE;\r
+}\r