--- /dev/null
+/** @file\r
+Framework PEIM to initialize memory on an DDR2 SDRAM Memory Controller.\r
+\r
+Copyright (c) 2013 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _MRC_WRAPPER_H\r
+#define _MRC_WRAPPER_H\r
+\r
+#include <Ppi/QNCMemoryInit.h>\r
+#include "PlatformEarlyInit.h"\r
+\r
+//\r
+// Define the default memory areas required\r
+//\r
+#define EDKII_RESERVED_SIZE_PAGES 0x40\r
+#define ACPI_NVS_SIZE_PAGES 0x40\r
+#define RUNTIME_SERVICES_DATA_SIZE_PAGES 0x20\r
+#define RUNTIME_SERVICES_CODE_SIZE_PAGES 0x60\r
+#define ACPI_RECLAIM_SIZE_PAGES 0x10\r
+#define EDKII_DXE_MEM_SIZE_PAGES 0x20\r
+\r
+#define AP_STARTUP_VECTOR 0x00097000\r
+\r
+//\r
+// Maximum number of "Socket Sets", where a "Socket Set is a set of matching\r
+// DIMM's from the various channels\r
+//\r
+#define MAX_SOCKET_SETS 2\r
+\r
+//\r
+// Maximum number of memory ranges supported by the memory controller\r
+//\r
+#define MAX_RANGES (MAX_ROWS + 5)\r
+\r
+//\r
+// Min. of 48MB PEI phase\r
+//\r
+#define PEI_MIN_MEMORY_SIZE (6 * 0x800000)\r
+#define PEI_RECOVERY_MIN_MEMORY_SIZE (6 * 0x800000)\r
+\r
+#define PEI_MEMORY_RANGE_OPTION_ROM UINT32\r
+#define PEI_MR_OPTION_ROM_NONE 0x00000000\r
+\r
+//\r
+// SMRAM Memory Range\r
+//\r
+#define PEI_MEMORY_RANGE_SMRAM UINT32\r
+#define PEI_MR_SMRAM_ALL 0xFFFFFFFF\r
+#define PEI_MR_SMRAM_NONE 0x00000000\r
+#define PEI_MR_SMRAM_CACHEABLE_MASK 0x80000000\r
+#define PEI_MR_SMRAM_SEGTYPE_MASK 0x00FF0000\r
+#define PEI_MR_SMRAM_ABSEG_MASK 0x00010000\r
+#define PEI_MR_SMRAM_HSEG_MASK 0x00020000\r
+#define PEI_MR_SMRAM_TSEG_MASK 0x00040000\r
+//\r
+// SMRAM Size is a multiple of 128KB.\r
+//\r
+#define PEI_MR_SMRAM_SIZE_MASK 0x0000FFFF\r
+\r
+//\r
+// Pci Memory Hole\r
+//\r
+#define PEI_MEMORY_RANGE_PCI_MEMORY UINT32\r
+\r
+typedef enum {\r
+ Ignore,\r
+ Quick,\r
+ Sparse,\r
+ Extensive\r
+} PEI_MEMORY_TEST_OP;\r
+\r
+//\r
+// MRC Params Variable structure.\r
+//\r
+\r
+typedef struct {\r
+ MrcTimings_t timings; // Actual MRC config values saved in variable store.\r
+ UINT8 VariableStorePad[8]; // Allow for data stored in variable is required to be multiple of 8bytes.\r
+} PLATFORM_VARIABLE_MEMORY_CONFIG_DATA;\r
+\r
+///\r
+/// MRC Params Platform Data Flags bits\r
+///\r
+#define PDAT_MRC_FLAG_ECC_EN BIT0\r
+#define PDAT_MRC_FLAG_SCRAMBLE_EN BIT1\r
+#define PDAT_MRC_FLAG_MEMTEST_EN BIT2\r
+#define PDAT_MRC_FLAG_TOP_TREE_EN BIT3 ///< 0b DDR "fly-by" topology else 1b DDR "tree" topology.\r
+#define PDAT_MRC_FLAG_WR_ODT_EN BIT4 ///< If set ODR signal is asserted to DRAM devices on writes.\r
+\r
+///\r
+/// MRC Params Platform Data.\r
+///\r
+typedef struct {\r
+ UINT32 Flags; ///< Bitmap of PDAT_MRC_FLAG_XXX defs above.\r
+ UINT8 DramWidth; ///< 0=x8, 1=x16, others=RESERVED.\r
+ UINT8 DramSpeed; ///< 0=DDRFREQ_800, 1=DDRFREQ_1066, others=RESERVED. Only 533MHz SKU support 1066 memory.\r
+ UINT8 DramType; ///< 0=DDR3,1=DDR3L, others=RESERVED.\r
+ UINT8 RankMask; ///< bit[0] RANK0_EN, bit[1] RANK1_EN, others=RESERVED.\r
+ UINT8 ChanMask; ///< bit[0] CHAN0_EN, others=RESERVED.\r
+ UINT8 ChanWidth; ///< 1=x16, others=RESERVED.\r
+ UINT8 AddrMode; ///< 0, 1, 2 (mode 2 forced if ecc enabled), others=RESERVED.\r
+ UINT8 SrInt; ///< 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED. REFRESH_RATE.\r
+ UINT8 SrTemp; ///< 0=normal, 1=extended, others=RESERVED.\r
+ UINT8 DramRonVal; ///< 0=34ohm, 1=40ohm, others=RESERVED. RON_VALUE Select MRS1.DIC driver impedance control.\r
+ UINT8 DramRttNomVal; ///< 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED.\r
+ UINT8 DramRttWrVal; ///< 0=off others=RESERVED.\r
+ UINT8 SocRdOdtVal; ///< 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED.\r
+ UINT8 SocWrRonVal; ///< 0=27ohm, 1=32ohm, 2=40ohm, others=RESERVED.\r
+ UINT8 SocWrSlewRate; ///< 0=2.5V/ns, 1=4V/ns, others=RESERVED.\r
+ UINT8 DramDensity; ///< 0=512Mb, 1=1Gb, 2=2Gb, 3=4Gb, others=RESERVED.\r
+ UINT32 tRAS; ///< ACT to PRE command period in picoseconds.\r
+ UINT32 tWTR; ///< Delay from start of internal write transaction to internal read command in picoseconds.\r
+ UINT32 tRRD; ///< ACT to ACT command period (JESD79 specific to page size 1K/2K) in picoseconds.\r
+ UINT32 tFAW; ///< Four activate window (JESD79 specific to page size 1K/2K) in picoseconds.\r
+ UINT8 tCL; ///< DRAM CAS Latency in clocks.\r
+} PDAT_MRC_ITEM;\r
+\r
+//\r
+// Memory range types\r
+//\r
+typedef enum {\r
+ DualChannelDdrMainMemory,\r
+ DualChannelDdrSmramCacheable,\r
+ DualChannelDdrSmramNonCacheable,\r
+ DualChannelDdrGraphicsMemoryCacheable,\r
+ DualChannelDdrGraphicsMemoryNonCacheable,\r
+ DualChannelDdrReservedMemory,\r
+ DualChannelDdrMaxMemoryRangeType\r
+} PEI_DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE;\r
+\r
+//\r
+// Memory map range information\r
+//\r
+typedef struct {\r
+ EFI_PHYSICAL_ADDRESS PhysicalAddress;\r
+ EFI_PHYSICAL_ADDRESS CpuAddress;\r
+ EFI_PHYSICAL_ADDRESS RangeLength;\r
+ PEI_DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE Type;\r
+} PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE;\r
+\r
+//\r
+// Function prototypes.\r
+//\r
+\r
+EFI_STATUS\r
+InstallEfiMemory (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices,\r
+ IN EFI_BOOT_MODE BootMode,\r
+ IN UINT32 TotalMemorySize\r
+ );\r
+\r
+EFI_STATUS\r
+InstallS3Memory (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices,\r
+ IN UINT32 TotalMemorySize\r
+ );\r
+\r
+EFI_STATUS\r
+MemoryInit (\r
+ IN EFI_PEI_SERVICES **PeiServices\r
+ );\r
+\r
+\r
+EFI_STATUS\r
+LoadConfig (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices,\r
+ IN OUT MRCParams_t *MrcData\r
+ );\r
+\r
+EFI_STATUS\r
+SaveConfig (\r
+ IN MRCParams_t *MrcData\r
+ );\r
+\r
+VOID\r
+RetriveRequiredMemorySize (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ OUT UINTN *Size\r
+ );\r
+\r
+EFI_STATUS\r
+GetMemoryMap (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN UINT32 TotalMemorySize,\r
+ IN OUT PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE *MemoryMap,\r
+ IN OUT UINT8 *NumRanges\r
+ );\r
+\r
+EFI_STATUS\r
+ChooseRanges (\r
+ IN OUT PEI_MEMORY_RANGE_OPTION_ROM *OptionRomMask,\r
+ IN OUT PEI_MEMORY_RANGE_SMRAM *SmramMask,\r
+ IN OUT PEI_MEMORY_RANGE_PCI_MEMORY *PciMemoryMask\r
+ );\r
+\r
+EFI_STATUS\r
+GetPlatformMemorySize (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_BOOT_MODE BootMode,\r
+ IN OUT UINT64 *MemorySize\r
+ );\r
+\r
+EFI_STATUS\r
+BaseMemoryTest (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_PHYSICAL_ADDRESS BeginAddress,\r
+ IN UINT64 MemoryLength,\r
+ IN PEI_MEMORY_TEST_OP Operation,\r
+ OUT EFI_PHYSICAL_ADDRESS *ErrorAddress\r
+ );\r
+\r
+EFI_STATUS\r
+SetPlatformImrPolicy (\r
+ IN EFI_PHYSICAL_ADDRESS PeiMemoryBaseAddress,\r
+ IN UINT64 PeiMemoryLength,\r
+ IN UINTN RequiredMemSize\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+InfoPostInstallMemory (\r
+ OUT UINT32 *RmuBaseAddressPtr OPTIONAL,\r
+ OUT EFI_SMRAM_DESCRIPTOR **SmramDescriptorPtr OPTIONAL,\r
+ OUT UINTN *NumSmramRegionsPtr OPTIONAL\r
+ );\r
+\r
+#endif\r
projects / mirror_edk2.git / blobdiff