UefiCpuPkg: Define AMD Memory Encryption specific CPUID and MSR

[mirror_edk2.git] / UefiCpuPkg / CpuIo2Dxe / CpuIo2Dxe.c

diff --git a/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.c b/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.c
index 6ccfc40e10f8fb8b9ea2625ce79ea9af4487799e..d19349d4b0ff54e01d089346c249c6f9653502ae 100644 (file)
--- a/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.c
+++ b/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.c
@@ -1,7 +1,9 @@
 /** @file\r
   Produces the CPU I/O 2 Protocol.\r
 \r
-Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
+\r
 This program and the accompanying materials                          \r
 are licensed and made available under the terms and conditions of the BSD License         \r
 which accompanies this distribution.  The full text of the license may be found at        \r
@@ -13,7 +15,6 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 **/\r
 \r
 #include "CpuIo2Dxe.h"\r
-#include "IoFifo.h"\r
 \r
 //\r
 // Handle for the CPU I/O 2 Protocol\r
@@ -140,7 +141,7 @@ CpuIoCheckParameter (
   //\r
   // Check to see if Address is aligned\r
   //\r
-  if ((Address & (UINT64)(mInStride[Width] - 1)) != 0) {\r
+  if ((Address & ((UINT64)mInStride[Width] - 1)) != 0) {\r
     return EFI_UNSUPPORTED;\r
   }\r
 \r
@@ -412,7 +413,9 @@ CpuIoServiceRead (
   OutStride = mOutStride[Width];\r
   OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
 \r
-#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)\r
+  //\r
+  // Fifo operations supported for (mInStride[Width] == 0)\r
+  //\r
   if (InStride == 0) {\r
     switch (OperationWidth) {\r
     case EfiCpuIoWidthUint8:\r
@@ -433,7 +436,6 @@ CpuIoServiceRead (
       break;\r
     }\r
   }\r
-#endif\r
 \r
   for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {\r
     if (OperationWidth == EfiCpuIoWidthUint8) {\r
@@ -518,7 +520,9 @@ CpuIoServiceWrite (
   OutStride = mOutStride[Width];\r
   OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
 \r
-#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)\r
+  //\r
+  // Fifo operations supported for (mInStride[Width] == 0)\r
+  //\r
   if (InStride == 0) {\r
     switch (OperationWidth) {\r
     case EfiCpuIoWidthUint8:\r
@@ -539,7 +543,6 @@ CpuIoServiceWrite (
       break;\r
     }\r
   }\r
-#endif\r
 \r
   for (Uint8Buffer = (UINT8 *)Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {\r
     if (OperationWidth == EfiCpuIoWidthUint8) {\r