//\r
// PPI Descriptor used to install the CPU I/O PPI\r
//\r
-EFI_PEI_PPI_DESCRIPTOR gPpiList = {\r
+EFI_PEI_PPI_DESCRIPTOR gPpiList = {\r
(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
&gEfiPeiCpuIoPpiInstalledGuid,\r
NULL\r
//\r
// Lookup table for increment values based on transfer widths\r
//\r
-UINT8 mInStride[] = {\r
+UINT8 mInStride[] = {\r
1, // EfiPeiCpuIoWidthUint8\r
2, // EfiPeiCpuIoWidthUint16\r
4, // EfiPeiCpuIoWidthUint32\r
//\r
// Lookup table for increment values based on transfer widths\r
//\r
-UINT8 mOutStride[] = {\r
+UINT8 mOutStride[] = {\r
1, // EfiPeiCpuIoWidthUint8\r
2, // EfiPeiCpuIoWidthUint16\r
4, // EfiPeiCpuIoWidthUint32\r
// For FIFO type, the target address won't increase during the access,\r
// so treat Count as 1\r
//\r
- if (Width >= EfiPeiCpuIoWidthFifoUint8 && Width <= EfiPeiCpuIoWidthFifoUint64) {\r
+ if ((Width >= EfiPeiCpuIoWidthFifoUint8) && (Width <= EfiPeiCpuIoWidthFifoUint64)) {\r
Count = 1;\r
}\r
\r
//\r
// Check to see if Width is in the valid range for I/O Port operations\r
//\r
- Width = (EFI_PEI_CPU_IO_PPI_WIDTH) (Width & 0x03);\r
+ Width = (EFI_PEI_CPU_IO_PPI_WIDTH)(Width & 0x03);\r
if (!MmioOperation && (Width == EfiPeiCpuIoWidthUint64)) {\r
return EFI_INVALID_PARAMETER;\r
}\r
if (MaxCount < (Count - 1)) {\r
return EFI_UNSUPPORTED;\r
}\r
+\r
if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {\r
return EFI_UNSUPPORTED;\r
}\r
//\r
// Select loop based on the width of the transfer\r
//\r
- InStride = mInStride[Width];\r
- OutStride = mOutStride[Width];\r
- OperationWidth = (EFI_PEI_CPU_IO_PPI_WIDTH) (Width & 0x03);\r
- Aligned = (BOOLEAN)(((UINTN)Buffer & (mInStride[OperationWidth] - 1)) == 0x00);\r
+ InStride = mInStride[Width];\r
+ OutStride = mOutStride[Width];\r
+ OperationWidth = (EFI_PEI_CPU_IO_PPI_WIDTH)(Width & 0x03);\r
+ Aligned = (BOOLEAN)(((UINTN)Buffer & (mInStride[OperationWidth] - 1)) == 0x00);\r
for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {\r
if (OperationWidth == EfiPeiCpuIoWidthUint8) {\r
*Uint8Buffer = MmioRead8 ((UINTN)Address);\r
}\r
}\r
}\r
+\r
return EFI_SUCCESS;\r
}\r
\r
//\r
// Select loop based on the width of the transfer\r
//\r
- InStride = mInStride[Width];\r
- OutStride = mOutStride[Width];\r
- OperationWidth = (EFI_PEI_CPU_IO_PPI_WIDTH) (Width & 0x03);\r
- Aligned = (BOOLEAN)(((UINTN)Buffer & (mInStride[OperationWidth] - 1)) == 0x00);\r
+ InStride = mInStride[Width];\r
+ OutStride = mOutStride[Width];\r
+ OperationWidth = (EFI_PEI_CPU_IO_PPI_WIDTH)(Width & 0x03);\r
+ Aligned = (BOOLEAN)(((UINTN)Buffer & (mInStride[OperationWidth] - 1)) == 0x00);\r
for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {\r
if (OperationWidth == EfiPeiCpuIoWidthUint8) {\r
MmioWrite8 ((UINTN)Address, *Uint8Buffer);\r
}\r
}\r
}\r
+\r
return EFI_SUCCESS;\r
}\r
\r
//\r
// Select loop based on the width of the transfer\r
//\r
- InStride = mInStride[Width];\r
- OutStride = mOutStride[Width];\r
- OperationWidth = (EFI_PEI_CPU_IO_PPI_WIDTH) (Width & 0x03);\r
+ InStride = mInStride[Width];\r
+ OutStride = mOutStride[Width];\r
+ OperationWidth = (EFI_PEI_CPU_IO_PPI_WIDTH)(Width & 0x03);\r
\r
//\r
// Fifo operations supported for (mInStride[Width] == 0)\r
//\r
if (InStride == 0) {\r
switch (OperationWidth) {\r
- case EfiPeiCpuIoWidthUint8:\r
- IoReadFifo8 ((UINTN)Address, Count, Buffer);\r
- return EFI_SUCCESS;\r
- case EfiPeiCpuIoWidthUint16:\r
- IoReadFifo16 ((UINTN)Address, Count, Buffer);\r
- return EFI_SUCCESS;\r
- case EfiPeiCpuIoWidthUint32:\r
- IoReadFifo32 ((UINTN)Address, Count, Buffer);\r
- return EFI_SUCCESS;\r
- default:\r
- //\r
- // The CpuIoCheckParameter call above will ensure that this\r
- // path is not taken.\r
- //\r
- ASSERT (FALSE);\r
- break;\r
+ case EfiPeiCpuIoWidthUint8:\r
+ IoReadFifo8 ((UINTN)Address, Count, Buffer);\r
+ return EFI_SUCCESS;\r
+ case EfiPeiCpuIoWidthUint16:\r
+ IoReadFifo16 ((UINTN)Address, Count, Buffer);\r
+ return EFI_SUCCESS;\r
+ case EfiPeiCpuIoWidthUint32:\r
+ IoReadFifo32 ((UINTN)Address, Count, Buffer);\r
+ return EFI_SUCCESS;\r
+ default:\r
+ //\r
+ // The CpuIoCheckParameter call above will ensure that this\r
+ // path is not taken.\r
+ //\r
+ ASSERT (FALSE);\r
+ break;\r
}\r
}\r
\r
//\r
// Select loop based on the width of the transfer\r
//\r
- InStride = mInStride[Width];\r
- OutStride = mOutStride[Width];\r
- OperationWidth = (EFI_PEI_CPU_IO_PPI_WIDTH) (Width & 0x03);\r
+ InStride = mInStride[Width];\r
+ OutStride = mOutStride[Width];\r
+ OperationWidth = (EFI_PEI_CPU_IO_PPI_WIDTH)(Width & 0x03);\r
\r
//\r
// Fifo operations supported for (mInStride[Width] == 0)\r
//\r
if (InStride == 0) {\r
switch (OperationWidth) {\r
- case EfiPeiCpuIoWidthUint8:\r
- IoWriteFifo8 ((UINTN)Address, Count, Buffer);\r
- return EFI_SUCCESS;\r
- case EfiPeiCpuIoWidthUint16:\r
- IoWriteFifo16 ((UINTN)Address, Count, Buffer);\r
- return EFI_SUCCESS;\r
- case EfiPeiCpuIoWidthUint32:\r
- IoWriteFifo32 ((UINTN)Address, Count, Buffer);\r
- return EFI_SUCCESS;\r
- default:\r
- //\r
- // The CpuIoCheckParameter call above will ensure that this\r
- // path is not taken.\r
- //\r
- ASSERT (FALSE);\r
- break;\r
+ case EfiPeiCpuIoWidthUint8:\r
+ IoWriteFifo8 ((UINTN)Address, Count, Buffer);\r
+ return EFI_SUCCESS;\r
+ case EfiPeiCpuIoWidthUint16:\r
+ IoWriteFifo16 ((UINTN)Address, Count, Buffer);\r
+ return EFI_SUCCESS;\r
+ case EfiPeiCpuIoWidthUint32:\r
+ IoWriteFifo32 ((UINTN)Address, Count, Buffer);\r
+ return EFI_SUCCESS;\r
+ default:\r
+ //\r
+ // The CpuIoCheckParameter call above will ensure that this\r
+ // path is not taken.\r
+ //\r
+ ASSERT (FALSE);\r
+ break;\r
}\r
}\r
\r
UINT32\r
EFIAPI\r
CpuIoRead32 (\r
- IN CONST EFI_PEI_SERVICES **PeiServices,\r
- IN CONST EFI_PEI_CPU_IO_PPI *This,\r
- IN UINT64 Address\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN CONST EFI_PEI_CPU_IO_PPI *This,\r
+ IN UINT64 Address\r
)\r
{\r
return IoRead32 ((UINTN)Address);\r