/** @file\r
Definitions for CPU S3 data.\r
\r
-Copyright (c) 2013 - 2017, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
Msr,\r
ControlRegister,\r
MemoryMapped,\r
- CacheControl\r
+ CacheControl,\r
+\r
+ //\r
+ // Semaphore type used to control the execute sequence of the Msr.\r
+ // It will be insert between two Msr which has execute dependence.\r
+ //\r
+ Semaphore,\r
+ InvalidReg\r
} REGISTER_TYPE;\r
\r
+//\r
+// Describe the dependency type for different features.\r
+// The value set to CPU_REGISTER_TABLE_ENTRY.Value when the REGISTER_TYPE is Semaphore.\r
+//\r
+typedef enum {\r
+ NoneDepType,\r
+ ThreadDepType,\r
+ CoreDepType,\r
+ PackageDepType,\r
+ InvalidDepType\r
+} CPU_FEATURE_DEPENDENCE_TYPE;\r
+\r
+//\r
+// CPU information.\r
+//\r
+typedef struct {\r
+ //\r
+ // Record the package count in this CPU.\r
+ //\r
+ UINT32 PackageCount;\r
+ //\r
+ // Record the max core count in this CPU.\r
+ // Different packages may have different core count, this value\r
+ // save the max core count in all the packages.\r
+ //\r
+ UINT32 MaxCoreCount;\r
+ //\r
+ // Record the max thread count in this CPU.\r
+ // Different cores may have different thread count, this value\r
+ // save the max thread count in all the cores.\r
+ //\r
+ UINT32 MaxThreadCount;\r
+ //\r
+ // This field points to an array.\r
+ // This array saves valid core count (type UINT32) of each package.\r
+ // The array has PackageCount elements.\r
+ //\r
+ // If the platform does not support MSR setting at S3 resume, and\r
+ // therefore it doesn't need the dependency semaphores, it should set\r
+ // this field to 0.\r
+ //\r
+ EFI_PHYSICAL_ADDRESS ValidCoreCountPerPackage;\r
+} CPU_STATUS_INFORMATION;\r
+\r
//\r
// Element of register table entry\r
//\r
typedef struct {\r
- REGISTER_TYPE RegisterType;\r
- UINT32 Index;\r
- UINT8 ValidBitStart;\r
- UINT8 ValidBitLength;\r
- UINT64 Value;\r
+ REGISTER_TYPE RegisterType; // offset 0 - 3\r
+ UINT32 Index; // offset 4 - 7\r
+ UINT8 ValidBitStart; // offset 8\r
+ UINT8 ValidBitLength; // offset 9\r
+ UINT16 Reserved; // offset 10 - 11\r
+ UINT32 HighIndex; // offset 12-15, only valid for MemoryMapped\r
+ UINT64 Value; // offset 16-23\r
} CPU_REGISTER_TABLE_ENTRY;\r
\r
//\r
//\r
UINT32 InitialApicId;\r
//\r
- // Physical address of CPU_REGISTER_TABLE_ENTRY structures. This buffer must be\r
- // allocated below 4GB from memory of type EfiACPIMemoryNVS.\r
+ // Physical address of CPU_REGISTER_TABLE_ENTRY structures.\r
//\r
EFI_PHYSICAL_ADDRESS RegisterTableEntry;\r
} CPU_REGISTER_TABLE;\r
\r
//\r
-// Data structure that is required for ACPI S3 resume. This structure must be\r
-// allocated below 4GB from memory of type EfiACPIMemoryNVS. The PCD\r
+// Data structure that is required for ACPI S3 resume. The PCD\r
// PcdCpuS3DataAddress must be set to the physical address where this structure\r
// is allocated\r
//\r
//\r
EFI_PHYSICAL_ADDRESS StartupVector;\r
//\r
- // Physical address of structure of type IA32_DESCRIPTOR. This structure must\r
- // be allocated below 4GB from memory of type EfiACPIMemoryNVS. The\r
+ // Physical address of structure of type IA32_DESCRIPTOR. The\r
// IA32_DESCRIPTOR structure provides the base address and length of a GDT\r
- // The buffer for GDT must also be allocated below 4GB from memory of type\r
- // EfiACPIMemoryNVS. The GDT must be filled in with the GDT contents that are\r
+ // The GDT must be filled in with the GDT contents that are\r
// used during an ACPI S3 resume. This is typically the contents of the GDT\r
// used by the boot processor when the platform is booted.\r
//\r
EFI_PHYSICAL_ADDRESS GdtrProfile;\r
//\r
- // Physical address of structure of type IA32_DESCRIPTOR. This structure must\r
- // be allocated below 4GB from memory of type EfiACPIMemoryNVS. The\r
+ // Physical address of structure of type IA32_DESCRIPTOR. The\r
// IA32_DESCRIPTOR structure provides the base address and length of an IDT.\r
- // The buffer for IDT must also be allocated below 4GB from memory of type\r
- // EfiACPIMemoryNVS. The IDT must be filled in with the IDT contents that are\r
+ // The IDT must be filled in with the IDT contents that are\r
// used during an ACPI S3 resume. This is typically the contents of the IDT\r
// used by the boot processor when the platform is booted.\r
//\r
//\r
// Physical address of a buffer that is used as stacks during ACPI S3 resume.\r
// The total size of this buffer, in bytes, is NumberOfCpus * StackSize. This\r
- // structure must be allocated below 4GB from memory of type EfiACPIMemoryNVS.\r
+ // structure must be allocated from memory of type EfiACPIMemoryNVS.\r
//\r
EFI_PHYSICAL_ADDRESS StackAddress;\r
//\r
// Physical address of structure of type MTRR_SETTINGS that contains a copy\r
// of the MTRR settings that are compatible with the MTRR settings used by\r
// the boot processor when the platform was booted. These MTRR settings are\r
- // used during an ACPI S3 resume. This structure must be allocated below 4GB\r
- // from memory of type EfiACPIMemoryNVS.\r
+ // used during an ACPI S3 resume.\r
//\r
EFI_PHYSICAL_ADDRESS MtrrTable;\r
//\r
// Physical address of an array of CPU_REGISTER_TABLE structures, with\r
- // NumberOfCpus entries. This array must be allocated below 4GB from memory\r
- // of type EfiACPIMemoryNVS. If a register table is not required, then the\r
+ // NumberOfCpus entries. If a register table is not required, then the\r
// TableLength and AllocatedSize fields of CPU_REGISTER_TABLE are set to 0.\r
// If TableLength is > 0, then elements of RegisterTableEntry are used to\r
// initialize the CPU that matches InitialApicId, during an ACPI S3 resume,\r
EFI_PHYSICAL_ADDRESS PreSmmInitRegisterTable;\r
//\r
// Physical address of an array of CPU_REGISTER_TABLE structures, with\r
- // NumberOfCpus entries. This array must be allocated below 4GB from memory\r
- // of type EfiACPIMemoryNVS. If a register table is not required, then the\r
+ // NumberOfCpus entries. If a register table is not required, then the\r
// TableLength and AllocatedSize fields of CPU_REGISTER_TABLE are set to 0.\r
// If TableLength is > 0, then elements of RegisterTableEntry are used to\r
// initialize the CPU that matches InitialApicId, during an ACPI S3 resume,\r
EFI_PHYSICAL_ADDRESS RegisterTable;\r
//\r
// Physical address of a buffer that contains the machine check handler that\r
- // is used during an ACPI S3 Resume. This buffer must be allocated below 4GB\r
- // from memory of type EfiACPIMemoryNVS. In order for this machine check\r
+ // is used during an ACPI S3 Resume. In order for this machine check\r
// handler to be active on an AP during an ACPI S3 resume, the machine check\r
// vector in the IDT provided by IdtrProfile must be initialized to transfer\r
// control to this physical address.\r
// provided.\r
//\r
UINT32 ApMachineCheckHandlerSize;\r
+ //\r
+ // CPU information which is required when set the register table.\r
+ //\r
+ CPU_STATUS_INFORMATION CpuStatus;\r
+ //\r
+ // Location info for each AP.\r
+ // It points to an array which saves all APs location info.\r
+ // The array count is the AP count in this CPU.\r
+ //\r
+ // If the platform does not support MSR setting at S3 resume, and\r
+ // therefore it doesn't need the dependency semaphores, it should set\r
+ // this field to 0.\r
+ //\r
+ EFI_PHYSICAL_ADDRESS ApLocation;\r
} ACPI_CPU_DATA;\r
\r
#endif\r