Add generic HPET Timer DXE Driver and support libraries

[mirror_edk2.git] / UefiCpuPkg / Library / BaseXApicLib / BaseXApicLib.c

diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
index 79a0fcd413332c3a17dd97c98beec768c86c47ba..77c24deed0b3096b941bea0d3c62bac96ae8d757 100644 (file)
--- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
@@ -3,7 +3,7 @@
 \r
   This local APIC library instance supports xAPIC mode only.\r
 \r
-  Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -675,3 +675,80 @@ SendApicEoi (
   WriteLocalApicReg (XAPIC_EOI_OFFSET, 0);\r
 }\r
 \r
+/**\r
+  Get the 32-bit address that a device should use to send a Message Signaled \r
+  Interrupt (MSI) to the Local APIC of the currently executing processor.\r
+\r
+  @return 32-bit address used to send an MSI to the Local APIC.\r
+**/\r
+UINT32\r
+EFIAPI    \r
+GetApicMsiAddress (\r
+  VOID\r
+  )\r
+{\r
+  LOCAL_APIC_MSI_ADDRESS  MsiAddress;\r
+\r
+  //\r
+  // Return address for an MSI interrupt to be delivered only to the APIC ID \r
+  // of the currently executing processor.\r
+  //\r
+  MsiAddress.Uint32             = 0;\r
+  MsiAddress.Bits.BaseAddress   = 0xFEE;\r
+  MsiAddress.Bits.DestinationId = GetApicId ();\r
+  return MsiAddress.Uint32;\r
+}\r
+    \r
+/**\r
+  Get the 64-bit data value that a device should use to send a Message Signaled \r
+  Interrupt (MSI) to the Local APIC of the currently executing processor.\r
+\r
+  If Vector is not in range 0x10..0xFE, then ASSERT().\r
+  If DeliveryMode is not supported, then ASSERT().\r
+  \r
+  @param  Vector          The 8-bit interrupt vector associated with the MSI.  \r
+                          Must be in the range 0x10..0xFE\r
+  @param  DeliveryMode    A 3-bit value that specifies how the recept of the MSI \r
+                          is handled.  The only supported values are:\r
+                            0: LOCAL_APIC_DELIVERY_MODE_FIXED\r
+                            1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY\r
+                            2: LOCAL_APIC_DELIVERY_MODE_SMI\r
+                            4: LOCAL_APIC_DELIVERY_MODE_NMI\r
+                            5: LOCAL_APIC_DELIVERY_MODE_INIT\r
+                            7: LOCAL_APIC_DELIVERY_MODE_EXTINT\r
+                          \r
+  @param  LevelTriggered  TRUE specifies a level triggered interrupt.  \r
+                          FALSE specifies an edge triggered interrupt.\r
+  @param  AssertionLevel  Ignored if LevelTriggered is FALSE.\r
+                          TRUE specifies a level triggered interrupt that active \r
+                          when the interrupt line is asserted.\r
+                          FALSE specifies a level triggered interrupt that active \r
+                          when the interrupt line is deasserted.\r
+\r
+  @return 64-bit data value used to send an MSI to the Local APIC.\r
+**/\r
+UINT64\r
+EFIAPI    \r
+GetApicMsiValue (\r
+  IN UINT8    Vector,\r
+  IN UINTN    DeliveryMode,\r
+  IN BOOLEAN  LevelTriggered,\r
+  IN BOOLEAN  AssertionLevel\r
+  )\r
+{\r
+  LOCAL_APIC_MSI_DATA  MsiData;\r
+\r
+  ASSERT (Vector >= 0x10 && Vector <= 0xFE);\r
+  ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3);\r
+  \r
+  MsiData.Uint64            = 0;\r
+  MsiData.Bits.Vector       = Vector;\r
+  MsiData.Bits.DeliveryMode = (UINT32)DeliveryMode;\r
+  if (LevelTriggered) {\r
+    MsiData.Bits.TriggerMode = 1;\r
+    if (AssertionLevel) {\r
+      MsiData.Bits.Level = 1;\r
+    }\r
+  }\r
+  return MsiData.Uint64;\r
+}\r