/** @file\r
Machine Check features.\r
\r
- Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
IN VOID *ConfigData OPTIONAL\r
)\r
{\r
+ if (!MceSupport (ProcessorNumber, CpuInfo, ConfigData)) {\r
+ return FALSE;\r
+ }\r
return (CpuInfo->CpuIdVersionInfoEdx.Bits.MCA == 1);\r
}\r
\r
MSR_IA32_MCG_CAP_REGISTER McgCap;\r
UINT32 BankIndex;\r
\r
- McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);\r
- for (BankIndex = 0; BankIndex < (UINT32) McgCap.Bits.Count; BankIndex++) {\r
- CPU_REGISTER_TABLE_WRITE64 (\r
- ProcessorNumber,\r
- Msr,\r
- MSR_IA32_MC0_CTL + BankIndex * 4,\r
- MAX_UINT64\r
- );\r
+ //\r
+ // The scope of MSR_IA32_MC*_CTL/MSR_IA32_MC*_STATUS is core for below processor type, only program\r
+ // MSR_IA32_MC*_CTL/MSR_IA32_MC*_STATUS for thread 0 in each core.\r
+ //\r
+ if (IS_ATOM_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+ IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+ IS_SANDY_BRIDGE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+ IS_SKYLAKE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+ IS_XEON_PHI_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+ IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+ IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {\r
+ if (CpuInfo->ProcessorInfo.Location.Thread != 0) {\r
+ return RETURN_SUCCESS;\r
+ }\r
}\r
\r
- if (PcdGetBool (PcdIsPowerOnReset)) {\r
- for (BankIndex = 0; BankIndex < (UINTN) McgCap.Bits.Count; BankIndex++) {\r
+ //\r
+ // The scope of MSR_IA32_MC*_CTL/MSR_IA32_MC*_STATUS is package for below processor type, only program\r
+ // MSR_IA32_MC*_CTL/MSR_IA32_MC*_STATUS for thread 0 core 0 in each package.\r
+ //\r
+ if (IS_NEHALEM_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {\r
+ if ((CpuInfo->ProcessorInfo.Location.Thread != 0) || (CpuInfo->ProcessorInfo.Location.Core != 0)) {\r
+ return RETURN_SUCCESS;\r
+ }\r
+ }\r
+\r
+ if (State) {\r
+ McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);\r
+ for (BankIndex = 0; BankIndex < (UINT32) McgCap.Bits.Count; BankIndex++) {\r
CPU_REGISTER_TABLE_WRITE64 (\r
ProcessorNumber,\r
Msr,\r
- MSR_IA32_MC0_STATUS + BankIndex * 4,\r
- 0\r
+ MSR_IA32_MC0_CTL + BankIndex * 4,\r
+ MAX_UINT64\r
);\r
}\r
+\r
+ if (PcdGetBool (PcdIsPowerOnReset)) {\r
+ for (BankIndex = 0; BankIndex < (UINTN) McgCap.Bits.Count; BankIndex++) {\r
+ CPU_REGISTER_TABLE_WRITE64 (\r
+ ProcessorNumber,\r
+ Msr,\r
+ MSR_IA32_MC0_STATUS + BankIndex * 4,\r
+ 0\r
+ );\r
+ }\r
+ }\r
}\r
\r
return RETURN_SUCCESS;\r
}\r
\r
/**\r
- Detects if Local machine check exception feature supported on current \r
+ Detects if Local machine check exception feature supported on current\r
processor.\r
\r
@param[in] ProcessorNumber The index of the CPU executing this function.\r
{\r
MSR_IA32_FEATURE_CONTROL_REGISTER *MsrRegister;\r
\r
+ //\r
+ // The scope of FastStrings bit in the MSR_IA32_MISC_ENABLE is core for below processor type, only program \r
+ // MSR_IA32_MISC_ENABLE for thread 0 in each core.\r
+ //\r
+ if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+ IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+ IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {\r
+ if (CpuInfo->ProcessorInfo.Location.Thread != 0) {\r
+ return RETURN_SUCCESS;\r
+ }\r
+ }\r
+\r
ASSERT (ConfigData != NULL);\r
MsrRegister = (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData;\r
if (MsrRegister[ProcessorNumber].Bits.Lock == 0) {\r