UefiCpuPkg: Apply uncrustify changes

[mirror_edk2.git] / UefiCpuPkg / Library / CpuCommonFeaturesLib / Ppin.c

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c
index 468e425a0bfeba9fa616ed15af5c01f1101f8390..a7c2c12a51f490caf4ddbed21378c07decd4ad76 100644 (file)
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c
@@ -20,10 +20,10 @@
 VOID *\r
 EFIAPI\r
 PpinGetConfigData (\r
-  IN UINTN               NumberOfProcessors\r
+  IN UINTN  NumberOfProcessors\r
   )\r
 {\r
-  VOID          *ConfigData;\r
+  VOID  *ConfigData;\r
 \r
   ConfigData = AllocateZeroPool (sizeof (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER) * NumberOfProcessors);\r
   ASSERT (ConfigData != NULL);\r
@@ -55,8 +55,8 @@ PpinSupport (
   IN VOID                              *ConfigData  OPTIONAL\r
   )\r
 {\r
-  MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER    PlatformInfo;\r
-  MSR_IVY_BRIDGE_PPIN_CTL_REGISTER           *MsrPpinCtrl;\r
+  MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER  PlatformInfo;\r
+  MSR_IVY_BRIDGE_PPIN_CTL_REGISTER         *MsrPpinCtrl;\r
 \r
   if ((CpuInfo->DisplayFamily == 0x06) &&\r
       ((CpuInfo->DisplayModel == 0x3E) ||      // Xeon E5 V2\r
@@ -65,13 +65,14 @@ PpinSupport (
        (CpuInfo->DisplayModel == 0x55) ||      // Xeon Processor Scalable\r
        (CpuInfo->DisplayModel == 0x57) ||      // Xeon Phi processor 3200, 5200, 7200 series.\r
        (CpuInfo->DisplayModel == 0x85)         // Future Xeon phi processor\r
-     )) {\r
+      ))\r
+  {\r
     //\r
     // Check whether platform support this feature.\r
     //\r
     PlatformInfo.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1);\r
     if (PlatformInfo.Bits.PPIN_CAP != 0) {\r
-      MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *) ConfigData;\r
+      MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *)ConfigData;\r
       ASSERT (MsrPpinCtrl != NULL);\r
       MsrPpinCtrl[ProcessorNumber].Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN_CTL);\r
       return TRUE;\r
@@ -112,9 +113,9 @@ PpinInitialize (
   IN BOOLEAN                           State\r
   )\r
 {\r
-  MSR_IVY_BRIDGE_PPIN_CTL_REGISTER     *MsrPpinCtrl;\r
+  MSR_IVY_BRIDGE_PPIN_CTL_REGISTER  *MsrPpinCtrl;\r
 \r
-  MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *) ConfigData;\r
+  MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *)ConfigData;\r
   ASSERT (MsrPpinCtrl != NULL);\r
 \r
   //\r
@@ -143,14 +144,14 @@ PpinInitialize (
     // According to SDM, once Enable_PPIN is set, attempt to write 1 to LockOut will cause #GP.\r
     //\r
     MsrPpinCtrl[ProcessorNumber].Bits.Enable_PPIN = 1;\r
-    MsrPpinCtrl[ProcessorNumber].Bits.LockOut = 0;\r
+    MsrPpinCtrl[ProcessorNumber].Bits.LockOut     = 0;\r
   } else {\r
     //\r
     // Disable and Lock.\r
     // According to SDM, writing 1 to LockOut is permitted only if Enable_PPIN is clear.\r
     //\r
     MsrPpinCtrl[ProcessorNumber].Bits.Enable_PPIN = 0;\r
-    MsrPpinCtrl[ProcessorNumber].Bits.LockOut = 1;\r
+    MsrPpinCtrl[ProcessorNumber].Bits.LockOut     = 1;\r
   }\r
 \r
   CPU_REGISTER_TABLE_WRITE64 (\r