UefiCpuPkg/CpuCommonFeaturesLib: Register MSR base on scope Info.

[mirror_edk2.git] / UefiCpuPkg / Library / CpuCommonFeaturesLib / Ppin.c

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c
index 146c4cfda3f9c76e515a255ac8e1066e93c08b3f..d6219f4f3f23e6103ba528cb9e2a576d09f27924 100644 (file)
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c
@@ -1,7 +1,7 @@
 /** @file\r
   Protected Processor Inventory Number(PPIN) feature.\r
 \r
-  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -15,7 +15,7 @@
 #include "CpuCommonFeatures.h"\r
 \r
 /**\r
-  Detects if Protected Processor Inventory Number feature supported on current \r
+  Detects if Protected Processor Inventory Number feature supported on current\r
   processor.\r
 \r
   @param[in]  ProcessorNumber  The index of the CPU executing this function.\r
@@ -26,8 +26,8 @@
                                CPU_FEATURE_GET_CONFIG_DATA was not provided in\r
                                RegisterCpuFeature().\r
 \r
-  @retval TRUE     Enhanced Intel SpeedStep feature is supported.\r
-  @retval FALSE    Enhanced Intel SpeedStep feature is not supported.\r
+  @retval TRUE     Protected Processor Inventory Number feature is supported.\r
+  @retval FALSE    Protected Processor Inventory Number feature is not supported.\r
 \r
   @note This service could be called by BSP/APs.\r
 **/\r
@@ -41,13 +41,13 @@ PpinSupport (
 {\r
   MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER    PlatformInfo;\r
 \r
-  if ((CpuInfo->DisplayFamily == 0x06) && \r
+  if ((CpuInfo->DisplayFamily == 0x06) &&\r
       ((CpuInfo->DisplayModel == 0x3E) ||      // Xeon E5 V2\r
        (CpuInfo->DisplayModel == 0x56) ||      // Xeon Processor D Product\r
        (CpuInfo->DisplayModel == 0x4F) ||      // Xeon E5 v4, E7 v4\r
        (CpuInfo->DisplayModel == 0x55) ||      // Xeon Processor Scalable\r
        (CpuInfo->DisplayModel == 0x57) ||      // Xeon Phi processor 3200, 5200, 7200 series.\r
-       (CpuInfo->DisplayModel == 0x85)         // Future Xeon phi processor \r
+       (CpuInfo->DisplayModel == 0x85)         // Future Xeon phi processor\r
      )) {\r
     //\r
     // Check whether platform support this feature.\r
@@ -69,14 +69,14 @@ PpinSupport (
                                by CPU_FEATURE_GET_CONFIG_DATA.  NULL if\r
                                CPU_FEATURE_GET_CONFIG_DATA was not provided in\r
                                RegisterCpuFeature().\r
-  @param[in]  State            If TRUE, then the Protected Processor Inventory \r
+  @param[in]  State            If TRUE, then the Protected Processor Inventory\r
                                Number feature must be enabled.\r
-                               If FALSE, then the Protected Processor Inventory \r
+                               If FALSE, then the Protected Processor Inventory\r
                                Number feature must be disabled.\r
 \r
-  @retval RETURN_SUCCESS       Protected Processor Inventory Number feature is \r
+  @retval RETURN_SUCCESS       Protected Processor Inventory Number feature is\r
                                initialized.\r
-  @retval RETURN_DEVICE_ERROR  Device can't change state because it has been \r
+  @retval RETURN_DEVICE_ERROR  Device can't change state because it has been\r
                                locked.\r
 \r
 **/\r
@@ -101,6 +101,17 @@ PpinInitialize (
     return MsrPpinCtrl.Bits.Enable_PPIN == State ? RETURN_SUCCESS : RETURN_DEVICE_ERROR;\r
   }\r
 \r
+  //\r
+  // Support function already check the processor which support PPIN feature, so this function not need\r
+  // to check the processor again.\r
+  //\r
+  // The scope of the MSR_IVY_BRIDGE_PPIN_CTL is package level, only program MSR_IVY_BRIDGE_PPIN_CTL for\r
+  // thread 0 core 0 in each package.\r
+  //\r
+  if ((CpuInfo->ProcessorInfo.Location.Thread != 0) || (CpuInfo->ProcessorInfo.Location.Core != 0)) {\r
+    return RETURN_SUCCESS;\r
+  }\r
+\r
   CPU_REGISTER_TABLE_WRITE_FIELD (\r
     ProcessorNumber,\r
     Msr,\r