/** @file\r
x64 CPU Exception Handler.\r
\r
- Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2012 - 2022, Intel Corporation. All rights reserved.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
UINTN GdtSize;\r
\r
if ((StackSwitchData == NULL) ||\r
- (StackSwitchData->Ia32.Revision != CPU_EXCEPTION_INIT_DATA_REV) ||\r
- (StackSwitchData->X64.KnownGoodStackTop == 0) ||\r
- (StackSwitchData->X64.KnownGoodStackSize == 0) ||\r
- (StackSwitchData->X64.StackSwitchExceptions == NULL) ||\r
- (StackSwitchData->X64.StackSwitchExceptionNumber == 0) ||\r
- (StackSwitchData->X64.StackSwitchExceptionNumber > CPU_EXCEPTION_NUM) ||\r
- (StackSwitchData->X64.GdtTable == NULL) ||\r
- (StackSwitchData->X64.IdtTable == NULL) ||\r
- (StackSwitchData->X64.ExceptionTssDesc == NULL) ||\r
- (StackSwitchData->X64.ExceptionTss == NULL))\r
+ (StackSwitchData->KnownGoodStackTop == 0) ||\r
+ (StackSwitchData->KnownGoodStackSize == 0) ||\r
+ (StackSwitchData->StackSwitchExceptions == NULL) ||\r
+ (StackSwitchData->StackSwitchExceptionNumber == 0) ||\r
+ (StackSwitchData->StackSwitchExceptionNumber > CPU_EXCEPTION_NUM) ||\r
+ (StackSwitchData->GdtTable == NULL) ||\r
+ (StackSwitchData->IdtTable == NULL) ||\r
+ (StackSwitchData->ExceptionTssDesc == NULL) ||\r
+ (StackSwitchData->ExceptionTss == NULL))\r
{\r
return EFI_INVALID_PARAMETER;\r
}\r
// one or newly allocated, has enough space to hold descriptors for exception\r
// task-state segments.\r
//\r
- if (((UINTN)StackSwitchData->X64.GdtTable & (IA32_GDT_ALIGNMENT - 1)) != 0) {\r
+ if (((UINTN)StackSwitchData->GdtTable & (IA32_GDT_ALIGNMENT - 1)) != 0) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
- if ((UINTN)StackSwitchData->X64.ExceptionTssDesc < (UINTN)(StackSwitchData->X64.GdtTable)) {\r
+ if ((UINTN)StackSwitchData->ExceptionTssDesc < (UINTN)(StackSwitchData->GdtTable)) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
- if (((UINTN)StackSwitchData->X64.ExceptionTssDesc + StackSwitchData->X64.ExceptionTssDescSize) >\r
- ((UINTN)(StackSwitchData->X64.GdtTable) + StackSwitchData->X64.GdtTableSize))\r
+ if (((UINTN)StackSwitchData->ExceptionTssDesc + StackSwitchData->ExceptionTssDescSize) >\r
+ ((UINTN)(StackSwitchData->GdtTable) + StackSwitchData->GdtTableSize))\r
{\r
return EFI_INVALID_PARAMETER;\r
}\r
//\r
// One task gate descriptor and one task-state segment are needed.\r
//\r
- if (StackSwitchData->X64.ExceptionTssDescSize < sizeof (IA32_TSS_DESCRIPTOR)) {\r
+ if (StackSwitchData->ExceptionTssDescSize < sizeof (IA32_TSS_DESCRIPTOR)) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
- if (StackSwitchData->X64.ExceptionTssSize < sizeof (IA32_TASK_STATE_SEGMENT)) {\r
+ if (StackSwitchData->ExceptionTssSize < sizeof (IA32_TASK_STATE_SEGMENT)) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
//\r
// Interrupt stack table supports only 7 vectors.\r
//\r
- TssDesc = StackSwitchData->X64.ExceptionTssDesc;\r
- Tss = StackSwitchData->X64.ExceptionTss;\r
- if (StackSwitchData->X64.StackSwitchExceptionNumber > ARRAY_SIZE (Tss->IST)) {\r
+ TssDesc = StackSwitchData->ExceptionTssDesc;\r
+ Tss = StackSwitchData->ExceptionTss;\r
+ if (StackSwitchData->StackSwitchExceptionNumber > ARRAY_SIZE (Tss->IST)) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
AsmReadGdtr (&Gdtr);\r
\r
GdtSize = (UINTN)TssDesc + sizeof (IA32_TSS_DESCRIPTOR) -\r
- (UINTN)(StackSwitchData->X64.GdtTable);\r
- if ((UINTN)StackSwitchData->X64.GdtTable != Gdtr.Base) {\r
- CopyMem (StackSwitchData->X64.GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1);\r
- Gdtr.Base = (UINTN)StackSwitchData->X64.GdtTable;\r
+ (UINTN)(StackSwitchData->GdtTable);\r
+ if ((UINTN)StackSwitchData->GdtTable != Gdtr.Base) {\r
+ CopyMem (StackSwitchData->GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1);\r
+ Gdtr.Base = (UINTN)StackSwitchData->GdtTable;\r
Gdtr.Limit = (UINT16)GdtSize - 1;\r
}\r
\r
- if ((UINTN)StackSwitchData->X64.IdtTable != Idtr.Base) {\r
- Idtr.Base = (UINTN)StackSwitchData->X64.IdtTable;\r
+ if ((UINTN)StackSwitchData->IdtTable != Idtr.Base) {\r
+ Idtr.Base = (UINTN)StackSwitchData->IdtTable;\r
}\r
\r
- if (StackSwitchData->X64.IdtTableSize > 0) {\r
- Idtr.Limit = (UINT16)(StackSwitchData->X64.IdtTableSize - 1);\r
+ if (StackSwitchData->IdtTableSize > 0) {\r
+ Idtr.Limit = (UINT16)(StackSwitchData->IdtTableSize - 1);\r
}\r
\r
//\r
// Fixup exception task descriptor and task-state segment\r
//\r
ZeroMem (Tss, sizeof (*Tss));\r
- StackTop = StackSwitchData->X64.KnownGoodStackTop - CPU_STACK_ALIGNMENT;\r
+ StackTop = StackSwitchData->KnownGoodStackTop - CPU_STACK_ALIGNMENT;\r
StackTop = (UINTN)ALIGN_POINTER (StackTop, CPU_STACK_ALIGNMENT);\r
- IdtTable = StackSwitchData->X64.IdtTable;\r
- for (Index = 0; Index < StackSwitchData->X64.StackSwitchExceptionNumber; ++Index) {\r
+ IdtTable = StackSwitchData->IdtTable;\r
+ for (Index = 0; Index < StackSwitchData->StackSwitchExceptionNumber; ++Index) {\r
//\r
// Fixup IST\r
//\r
Tss->IST[Index] = StackTop;\r
- StackTop -= StackSwitchData->X64.KnownGoodStackSize;\r
+ StackTop -= StackSwitchData->KnownGoodStackSize;\r
\r
//\r
// Set the IST field to enable corresponding IST\r
//\r
- Vector = StackSwitchData->X64.StackSwitchExceptions[Index];\r
+ Vector = StackSwitchData->StackSwitchExceptions[Index];\r
if ((Vector >= CPU_EXCEPTION_NUM) ||\r
(Vector >= (Idtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR)))\r
{\r
//\r
// Load current task\r
//\r
- AsmWriteTr ((UINT16)((UINTN)StackSwitchData->X64.ExceptionTssDesc - Gdtr.Base));\r
+ AsmWriteTr ((UINT16)((UINTN)StackSwitchData->ExceptionTssDesc - Gdtr.Base));\r
\r
//\r
// Publish IDT\r