UefiCpuPkg: Simplify the struct definition of CPU_EXCEPTION_INIT_DATA

CPU_EXCEPTION_INIT_DATA is now an internal implementation of
CpuExceptionHandlerLib. Union can be removed since Ia32 and X64 have the
same definition. Also, two fields (Revision and InitDefaultHandlers)are
useless, can be removed.

Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
index 443eaf359ba79deabf9a1ce50ed59f3c73a6b588..11a5624f5184d034b697413ac530d356103b61fa 100644 (file)
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
@@ -49,71 +49,59 @@
 \r
 #define CPU_TSS_GDT_SIZE  (SIZE_2KB + CPU_TSS_DESC_SIZE + CPU_TSS_SIZE)\r
 \r
-#define CPU_EXCEPTION_INIT_DATA_REV  1\r
-\r
-typedef union {\r
-  struct {\r
-    //\r
-    // Revision number of this structure.\r
-    //\r
-    UINT32     Revision;\r
-    //\r
-    // The address of top of known good stack reserved for *ALL* exceptions\r
-    // listed in field StackSwitchExceptions.\r
-    //\r
-    UINTN      KnownGoodStackTop;\r
-    //\r
-    // The size of known good stack for *ONE* exception only.\r
-    //\r
-    UINTN      KnownGoodStackSize;\r
-    //\r
-    // Buffer of exception vector list for stack switch.\r
-    //\r
-    UINT8      *StackSwitchExceptions;\r
-    //\r
-    // Number of exception vectors in StackSwitchExceptions.\r
-    //\r
-    UINTN      StackSwitchExceptionNumber;\r
-    //\r
-    // Buffer of IDT table. It must be type of IA32_IDT_GATE_DESCRIPTOR.\r
-    // Normally there's no need to change IDT table size.\r
-    //\r
-    VOID       *IdtTable;\r
-    //\r
-    // Size of buffer for IdtTable.\r
-    //\r
-    UINTN      IdtTableSize;\r
-    //\r
-    // Buffer of GDT table. It must be type of IA32_SEGMENT_DESCRIPTOR.\r
-    //\r
-    VOID       *GdtTable;\r
-    //\r
-    // Size of buffer for GdtTable.\r
-    //\r
-    UINTN      GdtTableSize;\r
-    //\r
-    // Pointer to start address of descriptor of exception task gate in the\r
-    // GDT table. It must be type of IA32_TSS_DESCRIPTOR.\r
-    //\r
-    VOID       *ExceptionTssDesc;\r
-    //\r
-    // Size of buffer for ExceptionTssDesc.\r
-    //\r
-    UINTN      ExceptionTssDescSize;\r
-    //\r
-    // Buffer of task-state segment for exceptions. It must be type of\r
-    // IA32_TASK_STATE_SEGMENT.\r
-    //\r
-    VOID       *ExceptionTss;\r
-    //\r
-    // Size of buffer for ExceptionTss.\r
-    //\r
-    UINTN      ExceptionTssSize;\r
-    //\r
-    // Flag to indicate if default handlers should be initialized or not.\r
-    //\r
-    BOOLEAN    InitDefaultHandlers;\r
-  } Ia32, X64;\r
+typedef struct {\r
+  //\r
+  // The address of top of known good stack reserved for *ALL* exceptions\r
+  // listed in field StackSwitchExceptions.\r
+  //\r
+  UINTN    KnownGoodStackTop;\r
+  //\r
+  // The size of known good stack for *ONE* exception only.\r
+  //\r
+  UINTN    KnownGoodStackSize;\r
+  //\r
+  // Buffer of exception vector list for stack switch.\r
+  //\r
+  UINT8    *StackSwitchExceptions;\r
+  //\r
+  // Number of exception vectors in StackSwitchExceptions.\r
+  //\r
+  UINTN    StackSwitchExceptionNumber;\r
+  //\r
+  // Buffer of IDT table. It must be type of IA32_IDT_GATE_DESCRIPTOR.\r
+  // Normally there's no need to change IDT table size.\r
+  //\r
+  VOID     *IdtTable;\r
+  //\r
+  // Size of buffer for IdtTable.\r
+  //\r
+  UINTN    IdtTableSize;\r
+  //\r
+  // Buffer of GDT table. It must be type of IA32_SEGMENT_DESCRIPTOR.\r
+  //\r
+  VOID     *GdtTable;\r
+  //\r
+  // Size of buffer for GdtTable.\r
+  //\r
+  UINTN    GdtTableSize;\r
+  //\r
+  // Pointer to start address of descriptor of exception task gate in the\r
+  // GDT table. It must be type of IA32_TSS_DESCRIPTOR.\r
+  //\r
+  VOID     *ExceptionTssDesc;\r
+  //\r
+  // Size of buffer for ExceptionTssDesc.\r
+  //\r
+  UINTN    ExceptionTssDescSize;\r
+  //\r
+  // Buffer of task-state segment for exceptions. It must be type of\r
+  // IA32_TASK_STATE_SEGMENT.\r
+  //\r
+  VOID     *ExceptionTss;\r
+  //\r
+  // Size of buffer for ExceptionTss.\r
+  //\r
+  UINTN    ExceptionTssSize;\r
 } CPU_EXCEPTION_INIT_DATA;\r
 \r
 //\r

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
index 04e84099226c982db221dfc8b604ab124d94636d..d90c607bd71f9d2788e7b31663ec3d7fc4c565be 100644 (file)
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
@@ -190,19 +190,18 @@ InitializeSeparateExceptionStacks (
   }\r
 \r
   AsmReadIdtr (&Idtr);\r
-  EssData.X64.Revision                   = CPU_EXCEPTION_INIT_DATA_REV;\r
-  EssData.X64.KnownGoodStackTop          = StackTop;\r
-  EssData.X64.KnownGoodStackSize         = CPU_KNOWN_GOOD_STACK_SIZE;\r
-  EssData.X64.StackSwitchExceptions      = CPU_STACK_SWITCH_EXCEPTION_LIST;\r
-  EssData.X64.StackSwitchExceptionNumber = CPU_STACK_SWITCH_EXCEPTION_NUMBER;\r
-  EssData.X64.IdtTable                   = (VOID *)Idtr.Base;\r
-  EssData.X64.IdtTableSize               = Idtr.Limit + 1;\r
-  EssData.X64.GdtTable                   = NewGdtTable;\r
-  EssData.X64.GdtTableSize               = CPU_TSS_DESC_SIZE + Gdtr.Limit + 1;\r
-  EssData.X64.ExceptionTssDesc           = NewGdtTable + Gdtr.Limit + 1;\r
-  EssData.X64.ExceptionTssDescSize       = CPU_TSS_DESC_SIZE;\r
-  EssData.X64.ExceptionTss               = NewGdtTable + Gdtr.Limit + 1 + CPU_TSS_DESC_SIZE;\r
-  EssData.X64.ExceptionTssSize           = CPU_TSS_SIZE;\r
+  EssData.KnownGoodStackTop          = StackTop;\r
+  EssData.KnownGoodStackSize         = CPU_KNOWN_GOOD_STACK_SIZE;\r
+  EssData.StackSwitchExceptions      = CPU_STACK_SWITCH_EXCEPTION_LIST;\r
+  EssData.StackSwitchExceptionNumber = CPU_STACK_SWITCH_EXCEPTION_NUMBER;\r
+  EssData.IdtTable                   = (VOID *)Idtr.Base;\r
+  EssData.IdtTableSize               = Idtr.Limit + 1;\r
+  EssData.GdtTable                   = NewGdtTable;\r
+  EssData.GdtTableSize               = CPU_TSS_DESC_SIZE + Gdtr.Limit + 1;\r
+  EssData.ExceptionTssDesc           = NewGdtTable + Gdtr.Limit + 1;\r
+  EssData.ExceptionTssDescSize       = CPU_TSS_DESC_SIZE;\r
+  EssData.ExceptionTss               = NewGdtTable + Gdtr.Limit + 1 + CPU_TSS_DESC_SIZE;\r
+  EssData.ExceptionTssSize           = CPU_TSS_SIZE;\r
 \r
   return ArchSetupExceptionStack (&EssData);\r
 }\r

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
index f13e8e70206ec7c9a823236c9a1c1f95934c1beb..194d3a499b264818450970415fa18bb74c6acfc2 100644 (file)
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
@@ -1,7 +1,7 @@
 /** @file\r
   IA32 CPU Exception Handler functons.\r
 \r
-  Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2012 - 2022, Intel Corporation. All rights reserved.<BR>\r
   SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
 **/\r
@@ -132,16 +132,15 @@ ArchSetupExceptionStack (
   EXCEPTION_HANDLER_TEMPLATE_MAP  TemplateMap;\r
 \r
   if ((StackSwitchData == NULL) ||\r
-      (StackSwitchData->Ia32.Revision != CPU_EXCEPTION_INIT_DATA_REV) ||\r
-      (StackSwitchData->Ia32.KnownGoodStackTop == 0) ||\r
-      (StackSwitchData->Ia32.KnownGoodStackSize == 0) ||\r
-      (StackSwitchData->Ia32.StackSwitchExceptions == NULL) ||\r
-      (StackSwitchData->Ia32.StackSwitchExceptionNumber == 0) ||\r
-      (StackSwitchData->Ia32.StackSwitchExceptionNumber > CPU_EXCEPTION_NUM) ||\r
-      (StackSwitchData->Ia32.GdtTable == NULL) ||\r
-      (StackSwitchData->Ia32.IdtTable == NULL) ||\r
-      (StackSwitchData->Ia32.ExceptionTssDesc == NULL) ||\r
-      (StackSwitchData->Ia32.ExceptionTss == NULL))\r
+      (StackSwitchData->KnownGoodStackTop == 0) ||\r
+      (StackSwitchData->KnownGoodStackSize == 0) ||\r
+      (StackSwitchData->StackSwitchExceptions == NULL) ||\r
+      (StackSwitchData->StackSwitchExceptionNumber == 0) ||\r
+      (StackSwitchData->StackSwitchExceptionNumber > CPU_EXCEPTION_NUM) ||\r
+      (StackSwitchData->GdtTable == NULL) ||\r
+      (StackSwitchData->IdtTable == NULL) ||\r
+      (StackSwitchData->ExceptionTssDesc == NULL) ||\r
+      (StackSwitchData->ExceptionTss == NULL))\r
   {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
@@ -151,16 +150,16 @@ ArchSetupExceptionStack (
   // one or newly allocated, has enough space to hold descriptors for exception\r
   // task-state segments.\r
   //\r
-  if (((UINTN)StackSwitchData->Ia32.GdtTable & (IA32_GDT_ALIGNMENT - 1)) != 0) {\r
+  if (((UINTN)StackSwitchData->GdtTable & (IA32_GDT_ALIGNMENT - 1)) != 0) {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
 \r
-  if ((UINTN)StackSwitchData->Ia32.ExceptionTssDesc < (UINTN)(StackSwitchData->Ia32.GdtTable)) {\r
+  if ((UINTN)StackSwitchData->ExceptionTssDesc < (UINTN)(StackSwitchData->GdtTable)) {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
 \r
-  if ((UINTN)StackSwitchData->Ia32.ExceptionTssDesc + StackSwitchData->Ia32.ExceptionTssDescSize >\r
-      ((UINTN)(StackSwitchData->Ia32.GdtTable) + StackSwitchData->Ia32.GdtTableSize))\r
+  if ((UINTN)StackSwitchData->ExceptionTssDesc + StackSwitchData->ExceptionTssDescSize >\r
+      ((UINTN)(StackSwitchData->GdtTable) + StackSwitchData->GdtTableSize))\r
   {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
@@ -169,20 +168,20 @@ ArchSetupExceptionStack (
   // We need one descriptor and one TSS for current task and every exception\r
   // specified.\r
   //\r
-  if (StackSwitchData->Ia32.ExceptionTssDescSize <\r
-      sizeof (IA32_TSS_DESCRIPTOR) * (StackSwitchData->Ia32.StackSwitchExceptionNumber + 1))\r
+  if (StackSwitchData->ExceptionTssDescSize <\r
+      sizeof (IA32_TSS_DESCRIPTOR) * (StackSwitchData->StackSwitchExceptionNumber + 1))\r
   {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
 \r
-  if (StackSwitchData->Ia32.ExceptionTssSize <\r
-      sizeof (IA32_TASK_STATE_SEGMENT) * (StackSwitchData->Ia32.StackSwitchExceptionNumber + 1))\r
+  if (StackSwitchData->ExceptionTssSize <\r
+      sizeof (IA32_TASK_STATE_SEGMENT) * (StackSwitchData->StackSwitchExceptionNumber + 1))\r
   {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
 \r
-  TssDesc = StackSwitchData->Ia32.ExceptionTssDesc;\r
-  Tss     = StackSwitchData->Ia32.ExceptionTss;\r
+  TssDesc = StackSwitchData->ExceptionTssDesc;\r
+  Tss     = StackSwitchData->ExceptionTss;\r
 \r
   //\r
   // Initialize new GDT table and/or IDT table, if any\r
@@ -192,20 +191,20 @@ ArchSetupExceptionStack (
 \r
   GdtSize = (UINTN)TssDesc +\r
             sizeof (IA32_TSS_DESCRIPTOR) *\r
-            (StackSwitchData->Ia32.StackSwitchExceptionNumber + 1) -\r
-            (UINTN)(StackSwitchData->Ia32.GdtTable);\r
-  if ((UINTN)StackSwitchData->Ia32.GdtTable != Gdtr.Base) {\r
-    CopyMem (StackSwitchData->Ia32.GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1);\r
-    Gdtr.Base  = (UINTN)StackSwitchData->Ia32.GdtTable;\r
+            (StackSwitchData->StackSwitchExceptionNumber + 1) -\r
+            (UINTN)(StackSwitchData->GdtTable);\r
+  if ((UINTN)StackSwitchData->GdtTable != Gdtr.Base) {\r
+    CopyMem (StackSwitchData->GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1);\r
+    Gdtr.Base  = (UINTN)StackSwitchData->GdtTable;\r
     Gdtr.Limit = (UINT16)GdtSize - 1;\r
   }\r
 \r
-  if ((UINTN)StackSwitchData->Ia32.IdtTable != Idtr.Base) {\r
-    Idtr.Base = (UINTN)StackSwitchData->Ia32.IdtTable;\r
+  if ((UINTN)StackSwitchData->IdtTable != Idtr.Base) {\r
+    Idtr.Base = (UINTN)StackSwitchData->IdtTable;\r
   }\r
 \r
-  if (StackSwitchData->Ia32.IdtTableSize > 0) {\r
-    Idtr.Limit = (UINT16)(StackSwitchData->Ia32.IdtTableSize - 1);\r
+  if (StackSwitchData->IdtTableSize > 0) {\r
+    Idtr.Limit = (UINT16)(StackSwitchData->IdtTableSize - 1);\r
   }\r
 \r
   //\r
@@ -227,10 +226,10 @@ ArchSetupExceptionStack (
   // Fixup exception task descriptor and task-state segment\r
   //\r
   AsmGetTssTemplateMap (&TemplateMap);\r
-  StackTop = StackSwitchData->Ia32.KnownGoodStackTop - CPU_STACK_ALIGNMENT;\r
+  StackTop = StackSwitchData->KnownGoodStackTop - CPU_STACK_ALIGNMENT;\r
   StackTop = (UINTN)ALIGN_POINTER (StackTop, CPU_STACK_ALIGNMENT);\r
-  IdtTable = StackSwitchData->Ia32.IdtTable;\r
-  for (Index = 0; Index < StackSwitchData->Ia32.StackSwitchExceptionNumber; ++Index) {\r
+  IdtTable = StackSwitchData->IdtTable;\r
+  for (Index = 0; Index < StackSwitchData->StackSwitchExceptionNumber; ++Index) {\r
     TssDesc += 1;\r
     Tss     += 1;\r
 \r
@@ -251,7 +250,7 @@ ArchSetupExceptionStack (
     //\r
     // Fixup TSS\r
     //\r
-    Vector = StackSwitchData->Ia32.StackSwitchExceptions[Index];\r
+    Vector = StackSwitchData->StackSwitchExceptions[Index];\r
     if ((Vector >= CPU_EXCEPTION_NUM) ||\r
         (Vector >= (Idtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR)))\r
     {\r
@@ -271,7 +270,7 @@ ArchSetupExceptionStack (
     Tss->FS     = AsmReadFs ();\r
     Tss->GS     = AsmReadGs ();\r
 \r
-    StackTop -= StackSwitchData->Ia32.KnownGoodStackSize;\r
+    StackTop -= StackSwitchData->KnownGoodStackSize;\r
 \r
     //\r
     // Update IDT to use Task Gate for given exception\r
@@ -291,7 +290,7 @@ ArchSetupExceptionStack (
   //\r
   // Load current task\r
   //\r
-  AsmWriteTr ((UINT16)((UINTN)StackSwitchData->Ia32.ExceptionTssDesc - Gdtr.Base));\r
+  AsmWriteTr ((UINT16)((UINTN)StackSwitchData->ExceptionTssDesc - Gdtr.Base));\r
 \r
   //\r
   // Publish IDT\r

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c
index 52ec0fb8033b89b590c258feda4e36b0a733eff6..5952295126fe1b6804a341a224c1e2a86cd2bed1 100644 (file)
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c
@@ -236,19 +236,18 @@ InitializeSeparateExceptionStacks (
   NewGdtTable = ALIGN_POINTER (StackTop, sizeof (IA32_TSS_DESCRIPTOR));\r
 \r
   AsmReadIdtr (&Idtr);\r
-  EssData.X64.Revision                   = CPU_EXCEPTION_INIT_DATA_REV;\r
-  EssData.X64.KnownGoodStackTop          = StackTop;\r
-  EssData.X64.KnownGoodStackSize         = CPU_KNOWN_GOOD_STACK_SIZE;\r
-  EssData.X64.StackSwitchExceptions      = CPU_STACK_SWITCH_EXCEPTION_LIST;\r
-  EssData.X64.StackSwitchExceptionNumber = CPU_STACK_SWITCH_EXCEPTION_NUMBER;\r
-  EssData.X64.IdtTable                   = (VOID *)Idtr.Base;\r
-  EssData.X64.IdtTableSize               = Idtr.Limit + 1;\r
-  EssData.X64.GdtTable                   = NewGdtTable;\r
-  EssData.X64.GdtTableSize               = CPU_TSS_DESC_SIZE + Gdtr.Limit + 1;\r
-  EssData.X64.ExceptionTssDesc           = NewGdtTable + Gdtr.Limit + 1;\r
-  EssData.X64.ExceptionTssDescSize       = CPU_TSS_DESC_SIZE;\r
-  EssData.X64.ExceptionTss               = NewGdtTable + Gdtr.Limit + 1 + CPU_TSS_DESC_SIZE;\r
-  EssData.X64.ExceptionTssSize           = CPU_TSS_SIZE;\r
+  EssData.KnownGoodStackTop          = StackTop;\r
+  EssData.KnownGoodStackSize         = CPU_KNOWN_GOOD_STACK_SIZE;\r
+  EssData.StackSwitchExceptions      = CPU_STACK_SWITCH_EXCEPTION_LIST;\r
+  EssData.StackSwitchExceptionNumber = CPU_STACK_SWITCH_EXCEPTION_NUMBER;\r
+  EssData.IdtTable                   = (VOID *)Idtr.Base;\r
+  EssData.IdtTableSize               = Idtr.Limit + 1;\r
+  EssData.GdtTable                   = NewGdtTable;\r
+  EssData.GdtTableSize               = CPU_TSS_DESC_SIZE + Gdtr.Limit + 1;\r
+  EssData.ExceptionTssDesc           = NewGdtTable + Gdtr.Limit + 1;\r
+  EssData.ExceptionTssDescSize       = CPU_TSS_DESC_SIZE;\r
+  EssData.ExceptionTss               = NewGdtTable + Gdtr.Limit + 1 + CPU_TSS_DESC_SIZE;\r
+  EssData.ExceptionTssSize           = CPU_TSS_SIZE;\r
 \r
   return ArchSetupExceptionStack (&EssData);\r
 }\r

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
index cd7dccd48141025da8a1644fb0a6165b1e982f79..c14ac66c43c03f38d795715f1a4fb7518de19c91 100644 (file)
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
@@ -1,7 +1,7 @@
 /** @file\r
   x64 CPU Exception Handler.\r
 \r
-  Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2012 - 2022, Intel Corporation. All rights reserved.<BR>\r
   SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
 **/\r
@@ -136,16 +136,15 @@ ArchSetupExceptionStack (
   UINTN                     GdtSize;\r
 \r
   if ((StackSwitchData == NULL) ||\r
-      (StackSwitchData->Ia32.Revision != CPU_EXCEPTION_INIT_DATA_REV) ||\r
-      (StackSwitchData->X64.KnownGoodStackTop == 0) ||\r
-      (StackSwitchData->X64.KnownGoodStackSize == 0) ||\r
-      (StackSwitchData->X64.StackSwitchExceptions == NULL) ||\r
-      (StackSwitchData->X64.StackSwitchExceptionNumber == 0) ||\r
-      (StackSwitchData->X64.StackSwitchExceptionNumber > CPU_EXCEPTION_NUM) ||\r
-      (StackSwitchData->X64.GdtTable == NULL) ||\r
-      (StackSwitchData->X64.IdtTable == NULL) ||\r
-      (StackSwitchData->X64.ExceptionTssDesc == NULL) ||\r
-      (StackSwitchData->X64.ExceptionTss == NULL))\r
+      (StackSwitchData->KnownGoodStackTop == 0) ||\r
+      (StackSwitchData->KnownGoodStackSize == 0) ||\r
+      (StackSwitchData->StackSwitchExceptions == NULL) ||\r
+      (StackSwitchData->StackSwitchExceptionNumber == 0) ||\r
+      (StackSwitchData->StackSwitchExceptionNumber > CPU_EXCEPTION_NUM) ||\r
+      (StackSwitchData->GdtTable == NULL) ||\r
+      (StackSwitchData->IdtTable == NULL) ||\r
+      (StackSwitchData->ExceptionTssDesc == NULL) ||\r
+      (StackSwitchData->ExceptionTss == NULL))\r
   {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
@@ -155,16 +154,16 @@ ArchSetupExceptionStack (
   // one or newly allocated, has enough space to hold descriptors for exception\r
   // task-state segments.\r
   //\r
-  if (((UINTN)StackSwitchData->X64.GdtTable & (IA32_GDT_ALIGNMENT - 1)) != 0) {\r
+  if (((UINTN)StackSwitchData->GdtTable & (IA32_GDT_ALIGNMENT - 1)) != 0) {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
 \r
-  if ((UINTN)StackSwitchData->X64.ExceptionTssDesc < (UINTN)(StackSwitchData->X64.GdtTable)) {\r
+  if ((UINTN)StackSwitchData->ExceptionTssDesc < (UINTN)(StackSwitchData->GdtTable)) {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
 \r
-  if (((UINTN)StackSwitchData->X64.ExceptionTssDesc + StackSwitchData->X64.ExceptionTssDescSize) >\r
-      ((UINTN)(StackSwitchData->X64.GdtTable) + StackSwitchData->X64.GdtTableSize))\r
+  if (((UINTN)StackSwitchData->ExceptionTssDesc + StackSwitchData->ExceptionTssDescSize) >\r
+      ((UINTN)(StackSwitchData->GdtTable) + StackSwitchData->GdtTableSize))\r
   {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
@@ -172,20 +171,20 @@ ArchSetupExceptionStack (
   //\r
   // One task gate descriptor and one task-state segment are needed.\r
   //\r
-  if (StackSwitchData->X64.ExceptionTssDescSize < sizeof (IA32_TSS_DESCRIPTOR)) {\r
+  if (StackSwitchData->ExceptionTssDescSize < sizeof (IA32_TSS_DESCRIPTOR)) {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
 \r
-  if (StackSwitchData->X64.ExceptionTssSize < sizeof (IA32_TASK_STATE_SEGMENT)) {\r
+  if (StackSwitchData->ExceptionTssSize < sizeof (IA32_TASK_STATE_SEGMENT)) {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
 \r
   //\r
   // Interrupt stack table supports only 7 vectors.\r
   //\r
-  TssDesc = StackSwitchData->X64.ExceptionTssDesc;\r
-  Tss     = StackSwitchData->X64.ExceptionTss;\r
-  if (StackSwitchData->X64.StackSwitchExceptionNumber > ARRAY_SIZE (Tss->IST)) {\r
+  TssDesc = StackSwitchData->ExceptionTssDesc;\r
+  Tss     = StackSwitchData->ExceptionTss;\r
+  if (StackSwitchData->StackSwitchExceptionNumber > ARRAY_SIZE (Tss->IST)) {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
 \r
@@ -196,19 +195,19 @@ ArchSetupExceptionStack (
   AsmReadGdtr (&Gdtr);\r
 \r
   GdtSize = (UINTN)TssDesc + sizeof (IA32_TSS_DESCRIPTOR) -\r
-            (UINTN)(StackSwitchData->X64.GdtTable);\r
-  if ((UINTN)StackSwitchData->X64.GdtTable != Gdtr.Base) {\r
-    CopyMem (StackSwitchData->X64.GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1);\r
-    Gdtr.Base  = (UINTN)StackSwitchData->X64.GdtTable;\r
+            (UINTN)(StackSwitchData->GdtTable);\r
+  if ((UINTN)StackSwitchData->GdtTable != Gdtr.Base) {\r
+    CopyMem (StackSwitchData->GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1);\r
+    Gdtr.Base  = (UINTN)StackSwitchData->GdtTable;\r
     Gdtr.Limit = (UINT16)GdtSize - 1;\r
   }\r
 \r
-  if ((UINTN)StackSwitchData->X64.IdtTable != Idtr.Base) {\r
-    Idtr.Base = (UINTN)StackSwitchData->X64.IdtTable;\r
+  if ((UINTN)StackSwitchData->IdtTable != Idtr.Base) {\r
+    Idtr.Base = (UINTN)StackSwitchData->IdtTable;\r
   }\r
 \r
-  if (StackSwitchData->X64.IdtTableSize > 0) {\r
-    Idtr.Limit = (UINT16)(StackSwitchData->X64.IdtTableSize - 1);\r
+  if (StackSwitchData->IdtTableSize > 0) {\r
+    Idtr.Limit = (UINT16)(StackSwitchData->IdtTableSize - 1);\r
   }\r
 \r
   //\r
@@ -232,20 +231,20 @@ ArchSetupExceptionStack (
   // Fixup exception task descriptor and task-state segment\r
   //\r
   ZeroMem (Tss, sizeof (*Tss));\r
-  StackTop = StackSwitchData->X64.KnownGoodStackTop - CPU_STACK_ALIGNMENT;\r
+  StackTop = StackSwitchData->KnownGoodStackTop - CPU_STACK_ALIGNMENT;\r
   StackTop = (UINTN)ALIGN_POINTER (StackTop, CPU_STACK_ALIGNMENT);\r
-  IdtTable = StackSwitchData->X64.IdtTable;\r
-  for (Index = 0; Index < StackSwitchData->X64.StackSwitchExceptionNumber; ++Index) {\r
+  IdtTable = StackSwitchData->IdtTable;\r
+  for (Index = 0; Index < StackSwitchData->StackSwitchExceptionNumber; ++Index) {\r
     //\r
     // Fixup IST\r
     //\r
     Tss->IST[Index] = StackTop;\r
-    StackTop       -= StackSwitchData->X64.KnownGoodStackSize;\r
+    StackTop       -= StackSwitchData->KnownGoodStackSize;\r
 \r
     //\r
     // Set the IST field to enable corresponding IST\r
     //\r
-    Vector = StackSwitchData->X64.StackSwitchExceptions[Index];\r
+    Vector = StackSwitchData->StackSwitchExceptions[Index];\r
     if ((Vector >= CPU_EXCEPTION_NUM) ||\r
         (Vector >= (Idtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR)))\r
     {\r
@@ -263,7 +262,7 @@ ArchSetupExceptionStack (
   //\r
   // Load current task\r
   //\r
-  AsmWriteTr ((UINT16)((UINTN)StackSwitchData->X64.ExceptionTssDesc - Gdtr.Base));\r
+  AsmWriteTr ((UINT16)((UINTN)StackSwitchData->ExceptionTssDesc - Gdtr.Base));\r
 \r
   //\r
   // Publish IDT\r