/** @file\r
CPU MP Initialize Library common functions.\r
\r
- Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.<BR>\r
Copyright (c) 2020, AMD Inc. All rights reserved.<BR>\r
\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
CpuMpData->InitFlag = ApInitConfig;\r
WakeUpAP (CpuMpData, TRUE, 0, NULL, NULL, TRUE);\r
CpuMpData->InitFlag = ApInitDone;\r
- ASSERT (CpuMpData->CpuCount <= PcdGet32 (PcdCpuMaxLogicalProcessorNumber));\r
//\r
- // Wait for all APs finished the initialization\r
+ // When InitFlag == ApInitConfig, WakeUpAP () guarantees all APs are checked in.\r
+ // FinishedCount is the number of check-in APs.\r
//\r
- while (CpuMpData->FinishedCount < (CpuMpData->CpuCount - 1)) {\r
- CpuPause ();\r
- }\r
-\r
+ CpuMpData->CpuCount = CpuMpData->FinishedCount + 1;\r
+ ASSERT (CpuMpData->CpuCount <= PcdGet32 (PcdCpuMaxLogicalProcessorNumber));\r
\r
//\r
// Enable x2APIC mode if\r
CurrentApicMode = GetApicMode ();\r
while (TRUE) {\r
if (CpuMpData->InitFlag == ApInitConfig) {\r
- //\r
- // Add CPU number\r
- //\r
- InterlockedIncrement ((UINT32 *) &CpuMpData->CpuCount);\r
ProcessorNumber = ApIndex;\r
//\r
// This is first time AP wakeup, get BIST information from AP stack\r
RestoreVolatileRegisters (&CpuMpData->CpuData[0].VolatileRegisters, FALSE);\r
InitializeApData (CpuMpData, ProcessorNumber, BistData, ApTopOfStack);\r
ApStartupSignalBuffer = CpuMpData->CpuData[ProcessorNumber].StartupApSignal;\r
-\r
- //\r
- // Delay decrementing the APs executing count when SEV-ES is enabled\r
- // to allow the APs to issue an AP_RESET_HOLD before the BSP possibly\r
- // performs another INIT-SIPI-SIPI sequence.\r
- //\r
- if (!CpuMpData->SevEsIsEnabled) {\r
- InterlockedDecrement ((UINT32 *) &CpuMpData->MpCpuExchangeInfo->NumApsExecuting);\r
- }\r
} else {\r
//\r
// Execute AP function if AP is ready\r
}\r
}\r
\r
+ if (CpuMpData->ApLoopMode == ApInHltLoop) {\r
+ //\r
+ // Save AP volatile registers\r
+ //\r
+ SaveVolatileRegisters (&CpuMpData->CpuData[ProcessorNumber].VolatileRegisters);\r
+ }\r
+\r
//\r
// AP finished executing C code\r
//\r
InterlockedIncrement ((UINT32 *) &CpuMpData->FinishedCount);\r
\r
+ if (CpuMpData->InitFlag == ApInitConfig) {\r
+ //\r
+ // Delay decrementing the APs executing count when SEV-ES is enabled\r
+ // to allow the APs to issue an AP_RESET_HOLD before the BSP possibly\r
+ // performs another INIT-SIPI-SIPI sequence.\r
+ //\r
+ if (!CpuMpData->SevEsIsEnabled) {\r
+ InterlockedDecrement ((UINT32 *) &CpuMpData->MpCpuExchangeInfo->NumApsExecuting);\r
+ }\r
+ }\r
+\r
//\r
// Place AP is specified loop mode\r
//\r
if (CpuMpData->ApLoopMode == ApInHltLoop) {\r
- //\r
- // Save AP volatile registers\r
- //\r
- SaveVolatileRegisters (&CpuMpData->CpuData[ProcessorNumber].VolatileRegisters);\r
//\r
// Place AP in HLT-loop\r
//\r
IA32_CR4 Cr4;\r
\r
ExchangeInfo = CpuMpData->MpCpuExchangeInfo;\r
- ExchangeInfo->Lock = 0;\r
ExchangeInfo->StackStart = CpuMpData->Buffer;\r
ExchangeInfo->StackSize = CpuMpData->CpuApStackSize;\r
ExchangeInfo->BufferStart = CpuMpData->WakeupBuffer;\r
AddressMap->SwitchToRealSize +\r
sizeof (MP_CPU_EXCHANGE_INFO);\r
\r
- //\r
- // The AP reset stack is only used by SEV-ES guests. Do not add to the\r
- // allocation if SEV-ES is not enabled.\r
- //\r
- if (PcdGetBool (PcdSevEsIsEnabled)) {\r
- //\r
- // Stack location is based on APIC ID, so use the total number of\r
- // processors for calculating the total stack area.\r
- //\r
- Size += AP_RESET_STACK_SIZE * PcdGet32 (PcdCpuMaxLogicalProcessorNumber);\r
-\r
- Size = ALIGN_VALUE (Size, CPU_STACK_ALIGNMENT);\r
- }\r
-\r
return Size;\r
}\r
\r
)\r
{\r
UINTN ApResetVectorSize;\r
+ UINTN ApResetStackSize;\r
\r
if (CpuMpData->WakeupBuffer == (UINTN) -1) {\r
ApResetVectorSize = GetApResetVectorSize (&CpuMpData->AddressMap);\r
CpuMpData->AddressMap.ModeTransitionOffset\r
);\r
//\r
- // The reset stack starts at the end of the buffer.\r
+ // The AP reset stack is only used by SEV-ES guests. Do not allocate it\r
+ // if SEV-ES is not enabled.\r
//\r
- CpuMpData->SevEsAPResetStackStart = CpuMpData->WakeupBuffer + ApResetVectorSize;\r
+ if (PcdGetBool (PcdSevEsIsEnabled)) {\r
+ //\r
+ // Stack location is based on ProcessorNumber, so use the total number\r
+ // of processors for calculating the total stack area.\r
+ //\r
+ ApResetStackSize = (AP_RESET_STACK_SIZE *\r
+ PcdGet32 (PcdCpuMaxLogicalProcessorNumber));\r
+\r
+ //\r
+ // Invoke GetWakeupBuffer a second time to allocate the stack area\r
+ // below 1MB. The returned buffer will be page aligned and sized and\r
+ // below the previously allocated buffer.\r
+ //\r
+ CpuMpData->SevEsAPResetStackStart = GetWakeupBuffer (ApResetStackSize);\r
+\r
+ //\r
+ // Check to be sure that the "allocate below" behavior hasn't changed.\r
+ // This will also catch a failed allocation, as "-1" is returned on\r
+ // failure.\r
+ //\r
+ if (CpuMpData->SevEsAPResetStackStart >= CpuMpData->WakeupBuffer) {\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "SEV-ES AP reset stack is not below wakeup buffer\n"\r
+ ));\r
+\r
+ ASSERT (FALSE);\r
+ CpuDeadLoop ();\r
+ }\r
+ }\r
}\r
BackupAndPrepareWakeupBuffer (CpuMpData);\r
}\r
UINT32 Offset, InsnByte;\r
UINT8 LoNib, HiNib;\r
\r
- JmpFar = (SEV_ES_AP_JMP_FAR *) FixedPcdGet32 (PcdSevEsWorkAreaBase);\r
+ JmpFar = (SEV_ES_AP_JMP_FAR *) (UINTN) FixedPcdGet32 (PcdSevEsWorkAreaBase);\r
ASSERT (JmpFar != NULL);\r
\r
//\r
IN CPU_MP_DATA *CpuMpData,\r
IN BOOLEAN Broadcast,\r
IN UINTN ProcessorNumber,\r
- IN EFI_AP_PROCEDURE Procedure, OPTIONAL\r
- IN VOID *ProcedureArgument, OPTIONAL\r
+ IN EFI_AP_PROCEDURE Procedure OPTIONAL,\r
+ IN VOID *ProcedureArgument OPTIONAL,\r
IN BOOLEAN WakeUpDisabledAps\r
)\r
{\r
}\r
}\r
\r
+ //\r
+ // Dump the microcode revision for each core.\r
+ //\r
+ DEBUG_CODE_BEGIN ();\r
+ UINT32 ThreadId;\r
+ UINT32 ExpectedMicrocodeRevision;\r
+ CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob;\r
+ for (Index = 0; Index < CpuMpData->CpuCount; Index++) {\r
+ GetProcessorLocationByApicId (CpuInfoInHob[Index].InitialApicId, NULL, NULL, &ThreadId);\r
+ if (ThreadId == 0) {\r
+ //\r
+ // MicrocodeDetect() loads microcode in first thread of each core, so,\r
+ // CpuMpData->CpuData[Index].MicrocodeEntryAddr is initialized only for first thread of each core.\r
+ //\r
+ ExpectedMicrocodeRevision = 0;\r
+ if (CpuMpData->CpuData[Index].MicrocodeEntryAddr != 0) {\r
+ ExpectedMicrocodeRevision = ((CPU_MICROCODE_HEADER *)(UINTN)CpuMpData->CpuData[Index].MicrocodeEntryAddr)->UpdateRevision;\r
+ }\r
+ DEBUG ((\r
+ DEBUG_INFO, "CPU[%04d]: Microcode revision = %08x, expected = %08x\n",\r
+ Index, CpuMpData->CpuData[Index].MicrocodeRevision, ExpectedMicrocodeRevision\r
+ ));\r
+ }\r
+ }\r
+ DEBUG_CODE_END ();\r
//\r
// Initialize global data for MP support\r
//\r
EFI_STATUS\r
EFIAPI\r
MpInitLibGetNumberOfProcessors (\r
- OUT UINTN *NumberOfProcessors, OPTIONAL\r
+ OUT UINTN *NumberOfProcessors OPTIONAL,\r
OUT UINTN *NumberOfEnabledProcessors OPTIONAL\r
)\r
{\r
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