\r
**/\r
\r
-#include <PiSmm.h>\r
+#include <PiMm.h>\r
#include <Library/SmmCpuFeaturesLib.h>\r
#include <Library/BaseLib.h>\r
#include <Library/MtrrLib.h>\r
//\r
// MSRs required for configuration of SMM Code Access Check\r
//\r
-#define SMM_FEATURES_LIB_IA32_MCA_CAP 0x17D\r
-#define SMM_CODE_ACCESS_CHK_BIT BIT58\r
+#define SMM_FEATURES_LIB_IA32_MCA_CAP 0x17D\r
+#define SMM_CODE_ACCESS_CHK_BIT BIT58\r
\r
//\r
// Set default value to assume SMRR is not supported\r
AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx);\r
FamilyId = (RegEax >> 8) & 0xf;\r
ModelId = (RegEax >> 4) & 0xf;\r
- if (FamilyId == 0x06 || FamilyId == 0x0f) {\r
+ if ((FamilyId == 0x06) || (FamilyId == 0x0f)) {\r
ModelId = ModelId | ((RegEax >> 12) & 0xf0);\r
}\r
\r
// SMRR Physical Base and SMM Physical Mask MSRs are not available.\r
//\r
if (FamilyId == 0x06) {\r
- if (ModelId == 0x1C || ModelId == 0x26 || ModelId == 0x27 || ModelId == 0x35 || ModelId == 0x36) {\r
+ if ((ModelId == 0x1C) || (ModelId == 0x26) || (ModelId == 0x27) || (ModelId == 0x35) || (ModelId == 0x36)) {\r
mSmrrSupported = FALSE;\r
}\r
}\r
// Processor Family MSRs\r
//\r
if (FamilyId == 0x06) {\r
- if (ModelId == 0x17 || ModelId == 0x0f) {\r
+ if ((ModelId == 0x17) || (ModelId == 0x0f)) {\r
mSmrrPhysBaseMsr = SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE;\r
mSmrrPhysMaskMsr = SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK;\r
}\r
//\r
// Configure SMBASE.\r
//\r
- CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);\r
+ CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);\r
CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];\r
\r
//\r
// accessing SMRR base/mask MSRs. If Lock(BIT0) of MSR_FEATURE_CONTROL MSR(0x3A)\r
// is set, then the MSR is locked and can not be modified.\r
//\r
- if (mSmrrSupported && mSmrrPhysBaseMsr == SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE) {\r
+ if (mSmrrSupported && (mSmrrPhysBaseMsr == SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE)) {\r
FeatureControl = AsmReadMsr64 (SMM_FEATURES_LIB_IA32_FEATURE_CONTROL);\r
if ((FeatureControl & BIT3) == 0) {\r
if ((FeatureControl & BIT0) == 0) {\r
//\r
if ((CpuHotPlugData->SmrrSize < SIZE_4KB) ||\r
(CpuHotPlugData->SmrrSize != GetPowerOfTwo32 (CpuHotPlugData->SmrrSize)) ||\r
- ((CpuHotPlugData->SmrrBase & ~(CpuHotPlugData->SmrrSize - 1)) != CpuHotPlugData->SmrrBase)) {\r
+ ((CpuHotPlugData->SmrrBase & ~(CpuHotPlugData->SmrrSize - 1)) != CpuHotPlugData->SmrrBase))\r
+ {\r
//\r
// Print message and halt if CPU is Monarch\r
//\r
AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx);\r
FamilyId = (RegEax >> 8) & 0xf;\r
ModelId = (RegEax >> 4) & 0xf;\r
- if (FamilyId == 0x06 || FamilyId == 0x0f) {\r
+ if ((FamilyId == 0x06) || (FamilyId == 0x0f)) {\r
ModelId = ModelId | ((RegEax >> 12) & 0xf0);\r
}\r
\r
// Intel(R) Core(TM) Processor Family MSRs.\r
//\r
if (FamilyId == 0x06) {\r
- if (ModelId == 0x3C || ModelId == 0x45 || ModelId == 0x46 ||\r
- ModelId == 0x3D || ModelId == 0x47 || ModelId == 0x4E || ModelId == 0x4F ||\r
- ModelId == 0x3F || ModelId == 0x56 || ModelId == 0x57 || ModelId == 0x5C ||\r
- ModelId == 0x8C) {\r
+ if ((ModelId == 0x3C) || (ModelId == 0x45) || (ModelId == 0x46) ||\r
+ (ModelId == 0x3D) || (ModelId == 0x47) || (ModelId == 0x4E) || (ModelId == 0x4F) ||\r
+ (ModelId == 0x3F) || (ModelId == 0x56) || (ModelId == 0x57) || (ModelId == 0x5C) ||\r
+ (ModelId == 0x8C))\r
+ {\r
//\r
// Check to see if the CPU supports the SMM Code Access Check feature\r
// Do not access this MSR unless the CPU supports the SmmRegFeatureControl\r
)\r
{\r
if (mSmrrSupported && mNeedConfigureMtrrs) {\r
- AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64(mSmrrPhysMaskMsr) & ~EFI_MSR_SMRR_PHYS_MASK_VALID);\r
+ AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64 (mSmrrPhysMaskMsr) & ~EFI_MSR_SMRR_PHYS_MASK_VALID);\r
}\r
}\r
\r
)\r
{\r
if (mSmrrSupported && mNeedConfigureMtrrs) {\r
- AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64(mSmrrPhysMaskMsr) | EFI_MSR_SMRR_PHYS_MASK_VALID);\r
+ AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64 (mSmrrPhysMaskMsr) | EFI_MSR_SMRR_PHYS_MASK_VALID);\r
}\r
}\r
\r
IN SMM_REG_NAME RegName\r
)\r
{\r
- if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) {\r
+ if (mSmmFeatureControlSupported && (RegName == SmmRegFeatureControl)) {\r
return TRUE;\r
}\r
+\r
return FALSE;\r
}\r
\r
IN SMM_REG_NAME RegName\r
)\r
{\r
- if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) {\r
+ if (mSmmFeatureControlSupported && (RegName == SmmRegFeatureControl)) {\r
return AsmReadMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL);\r
}\r
+\r
return 0;\r
}\r
\r
IN UINT64 Value\r
)\r
{\r
- if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) {\r
+ if (mSmmFeatureControlSupported && (RegName == SmmRegFeatureControl)) {\r
AsmWriteMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL, Value);\r
}\r
}\r
VOID *\r
EFIAPI\r
SmmCpuFeaturesAllocatePageTableMemory (\r
- IN UINTN Pages\r
+ IN UINTN Pages\r
)\r
{\r
return NULL;\r
}\r
-\r