/** @file\r
Code for Processor S3 restoration\r
\r
-Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
\r
#include "PiSmmCpuDxeSmm.h"\r
\r
+#pragma pack(1)\r
typedef struct {\r
UINTN Lock;\r
VOID *StackStart;\r
IA32_DESCRIPTOR IdtrProfile;\r
UINT32 BufferStart;\r
UINT32 Cr3;\r
+ UINTN InitializeFloatingPointUnitsAddress;\r
} MP_CPU_EXCHANGE_INFO;\r
+#pragma pack()\r
\r
typedef struct {\r
UINT8 *RendezvousFunnelAddress;\r
//\r
SPIN_LOCK *mMemoryMappedLock = NULL;\r
\r
+//\r
+// Signal that SMM BASE relocation is complete.\r
+//\r
+volatile BOOLEAN mInitApsAfterSmmBaseReloc;\r
+\r
/**\r
Get starting address and size of the rendezvous entry for APs.\r
Information for fixing a jump instruction in the code is also returned.\r
volatile UINT32 mNumberToFinish;\r
MP_CPU_EXCHANGE_INFO *mExchangeInfo;\r
BOOLEAN mRestoreSmmConfigurationInS3 = FALSE;\r
-VOID *mGdtForAp = NULL;\r
-VOID *mIdtForAp = NULL;\r
-VOID *mMachineCheckHandlerForAp = NULL;\r
MP_MSR_LOCK *mMsrSpinLocks = NULL;\r
UINTN mMsrSpinLockCount;\r
UINTN mMsrCount = 0;\r
\r
This function programs registers for the calling processor.\r
\r
- @param RegisterTable Pointer to register table of the running processor.\r
+ @param RegisterTables Pointer to register table of the running processor.\r
+ @param RegisterTableCount Register table count.\r
\r
**/\r
VOID\r
SetProcessorRegister (\r
- IN CPU_REGISTER_TABLE *RegisterTable\r
+ IN CPU_REGISTER_TABLE *RegisterTables,\r
+ IN UINTN RegisterTableCount\r
)\r
{\r
CPU_REGISTER_TABLE_ENTRY *RegisterTableEntry;\r
UINTN Index;\r
UINTN Value;\r
SPIN_LOCK *MsrSpinLock;\r
+ UINT32 InitApicId;\r
+ CPU_REGISTER_TABLE *RegisterTable;\r
+\r
+ InitApicId = GetInitialApicId ();\r
+ RegisterTable = NULL;\r
+ for (Index = 0; Index < RegisterTableCount; Index++) {\r
+ if (RegisterTables[Index].InitialApicId == InitApicId) {\r
+ RegisterTable = &RegisterTables[Index];\r
+ break;\r
+ }\r
+ }\r
+ ASSERT (RegisterTable != NULL);\r
\r
//\r
// Traverse Register Table of this logical processor\r
}\r
\r
/**\r
- AP initialization before SMBASE relocation in the S3 boot path.\r
+ AP initialization before then after SMBASE relocation in the S3 boot path.\r
**/\r
VOID\r
-EarlyMPRendezvousProcedure (\r
+InitializeAp (\r
VOID\r
)\r
{\r
- CPU_REGISTER_TABLE *RegisterTableList;\r
- UINT32 InitApicId;\r
- UINTN Index;\r
+ UINTN TopOfStack;\r
+ UINT8 Stack[128];\r
\r
LoadMtrrData (mAcpiCpuData.MtrrTable);\r
\r
- //\r
- // Find processor number for this CPU.\r
- //\r
- RegisterTableList = (CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.PreSmmInitRegisterTable;\r
- InitApicId = GetInitialApicId ();\r
- for (Index = 0; Index < mAcpiCpuData.NumberOfCpus; Index++) {\r
- if (RegisterTableList[Index].InitialApicId == InitApicId) {\r
- SetProcessorRegister (&RegisterTableList[Index]);\r
- break;\r
- }\r
- }\r
+ SetProcessorRegister ((CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.PreSmmInitRegisterTable, mAcpiCpuData.NumberOfCpus);\r
\r
//\r
// Count down the number with lock mechanism.\r
//\r
InterlockedDecrement (&mNumberToFinish);\r
-}\r
\r
-/**\r
- AP initialization after SMBASE relocation in the S3 boot path.\r
-**/\r
-VOID\r
-MPRendezvousProcedure (\r
- VOID\r
- )\r
-{\r
- CPU_REGISTER_TABLE *RegisterTableList;\r
- UINT32 InitApicId;\r
- UINTN Index;\r
- UINTN TopOfStack;\r
- UINT8 Stack[128];\r
+ //\r
+ // Wait for BSP to signal SMM Base relocation done.\r
+ //\r
+ while (!mInitApsAfterSmmBaseReloc) {\r
+ CpuPause ();\r
+ }\r
\r
ProgramVirtualWireMode ();\r
DisableLvtInterrupts ();\r
\r
- RegisterTableList = (CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.RegisterTable;\r
- InitApicId = GetInitialApicId ();\r
- for (Index = 0; Index < mAcpiCpuData.NumberOfCpus; Index++) {\r
- if (RegisterTableList[Index].InitialApicId == InitApicId) {\r
- SetProcessorRegister (&RegisterTableList[Index]);\r
- break;\r
- }\r
- }\r
+ SetProcessorRegister ((CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.RegisterTable, mAcpiCpuData.NumberOfCpus);\r
\r
//\r
// Place AP into the safe code, count down the number with lock mechanism in the safe code.\r
CopyMem ((VOID *) (UINTN) &mExchangeInfo->GdtrProfile, (VOID *) (UINTN) mAcpiCpuData.GdtrProfile, sizeof (IA32_DESCRIPTOR));\r
CopyMem ((VOID *) (UINTN) &mExchangeInfo->IdtrProfile, (VOID *) (UINTN) mAcpiCpuData.IdtrProfile, sizeof (IA32_DESCRIPTOR));\r
\r
- //\r
- // Copy AP's GDT, IDT and Machine Check handler from SMRAM to ACPI NVS memory\r
- //\r
- CopyMem ((VOID *) mExchangeInfo->GdtrProfile.Base, mGdtForAp, mExchangeInfo->GdtrProfile.Limit + 1);\r
- CopyMem ((VOID *) mExchangeInfo->IdtrProfile.Base, mIdtForAp, mExchangeInfo->IdtrProfile.Limit + 1);\r
- CopyMem ((VOID *)(UINTN) mAcpiCpuData.ApMachineCheckHandlerBase, mMachineCheckHandlerForAp, mAcpiCpuData.ApMachineCheckHandlerSize);\r
-\r
mExchangeInfo->StackStart = (VOID *) (UINTN) mAcpiCpuData.StackAddress;\r
mExchangeInfo->StackSize = mAcpiCpuData.StackSize;\r
mExchangeInfo->BufferStart = (UINT32) StartupVector;\r
mExchangeInfo->Cr3 = (UINT32) (AsmReadCr3 ());\r
+ mExchangeInfo->InitializeFloatingPointUnitsAddress = (UINTN)InitializeFloatingPointUnits;\r
}\r
\r
/**\r
\r
**/\r
VOID\r
-EarlyInitializeCpu (\r
+InitializeCpuBeforeRebase (\r
VOID\r
)\r
{\r
- CPU_REGISTER_TABLE *RegisterTableList;\r
- UINT32 InitApicId;\r
- UINTN Index;\r
-\r
LoadMtrrData (mAcpiCpuData.MtrrTable);\r
\r
- //\r
- // Find processor number for this CPU.\r
- //\r
- RegisterTableList = (CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.PreSmmInitRegisterTable;\r
- InitApicId = GetInitialApicId ();\r
- for (Index = 0; Index < mAcpiCpuData.NumberOfCpus; Index++) {\r
- if (RegisterTableList[Index].InitialApicId == InitApicId) {\r
- SetProcessorRegister (&RegisterTableList[Index]);\r
- break;\r
- }\r
- }\r
+ SetProcessorRegister ((CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.PreSmmInitRegisterTable, mAcpiCpuData.NumberOfCpus);\r
\r
ProgramVirtualWireMode ();\r
\r
PrepareApStartupVector (mAcpiCpuData.StartupVector);\r
\r
mNumberToFinish = mAcpiCpuData.NumberOfCpus - 1;\r
- mExchangeInfo->ApFunction = (VOID *) (UINTN) EarlyMPRendezvousProcedure;\r
+ mExchangeInfo->ApFunction = (VOID *) (UINTN) InitializeAp;\r
+\r
+ //\r
+ // Execute code for before SmmBaseReloc. Note: This flag is maintained across S3 boots.\r
+ //\r
+ mInitApsAfterSmmBaseReloc = FALSE;\r
\r
//\r
// Send INIT IPI - SIPI to all APs\r
\r
**/\r
VOID\r
-InitializeCpu (\r
+InitializeCpuAfterRebase (\r
VOID\r
)\r
{\r
- CPU_REGISTER_TABLE *RegisterTableList;\r
- UINT32 InitApicId;\r
- UINTN Index;\r
-\r
- RegisterTableList = (CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.RegisterTable;\r
- InitApicId = GetInitialApicId ();\r
- for (Index = 0; Index < mAcpiCpuData.NumberOfCpus; Index++) {\r
- if (RegisterTableList[Index].InitialApicId == InitApicId) {\r
- SetProcessorRegister (&RegisterTableList[Index]);\r
- break;\r
- }\r
- }\r
+ SetProcessorRegister ((CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.RegisterTable, mAcpiCpuData.NumberOfCpus);\r
\r
mNumberToFinish = mAcpiCpuData.NumberOfCpus - 1;\r
- //\r
- // StackStart was updated when APs were waken up in EarlyInitializeCpu.\r
- // Re-initialize StackAddress to original beginning address.\r
- //\r
- mExchangeInfo->StackStart = (VOID *) (UINTN) mAcpiCpuData.StackAddress;\r
- mExchangeInfo->ApFunction = (VOID *) (UINTN) MPRendezvousProcedure;\r
\r
//\r
- // Send INIT IPI - SIPI to all APs\r
+ // Signal that SMM base relocation is complete and to continue initialization.\r
//\r
- SendInitSipiSipiAllExcludingSelf ((UINT32)mAcpiCpuData.StartupVector);\r
+ mInitApsAfterSmmBaseReloc = TRUE;\r
\r
while (mNumberToFinish > 0) {\r
CpuPause ();\r
//\r
// First time microcode load and restore MTRRs\r
//\r
- EarlyInitializeCpu ();\r
+ InitializeCpuBeforeRebase ();\r
}\r
\r
//\r
//\r
// Restore MSRs for BSP and all APs\r
//\r
- InitializeCpu ();\r
+ InitializeCpuAfterRebase ();\r
}\r
\r
//\r
}\r
\r
GuidHob = GetFirstGuidHob (&gEfiAcpiVariableGuid);\r
- if (GuidHob != NULL) {\r
+ if (GuidHob == NULL) {\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "ERROR:%a(): HOB(gEfiAcpiVariableGuid=%g) needed by S3 resume doesn't exist!\n",\r
+ __FUNCTION__,\r
+ &gEfiAcpiVariableGuid\r
+ ));\r
+ CpuDeadLoop ();\r
+ } else {\r
SmramDescriptor = (EFI_SMRAM_DESCRIPTOR *) GET_GUID_HOB_DATA (GuidHob);\r
\r
DEBUG ((EFI_D_INFO, "SMM S3 SMRAM Structure = %x\n", SmramDescriptor));\r
SmmS3ResumeState->SmmS3StackSize = 0;\r
}\r
\r
- SmmS3ResumeState->SmmS3Cr0 = gSmmCr0;\r
+ SmmS3ResumeState->SmmS3Cr0 = mSmmCr0;\r
SmmS3ResumeState->SmmS3Cr3 = Cr3;\r
- SmmS3ResumeState->SmmS3Cr4 = gSmmCr4;\r
+ SmmS3ResumeState->SmmS3Cr4 = mSmmCr4;\r
\r
if (sizeof (UINTN) == sizeof (UINT64)) {\r
SmmS3ResumeState->Signature = SMM_S3_RESUME_SMM_64;\r
if (sizeof (UINTN) == sizeof (UINT32)) {\r
SmmS3ResumeState->Signature = SMM_S3_RESUME_SMM_32;\r
}\r
- }\r
\r
- //\r
- // Patch SmmS3ResumeState->SmmS3Cr3\r
- //\r
- InitSmmS3Cr3 ();\r
+ //\r
+ // Patch SmmS3ResumeState->SmmS3Cr3\r
+ //\r
+ InitSmmS3Cr3 ();\r
+ }\r
\r
//\r
// Allocate safe memory in ACPI NVS for AP to execute hlt loop in\r
ACPI_CPU_DATA *AcpiCpuData;\r
IA32_DESCRIPTOR *Gdtr;\r
IA32_DESCRIPTOR *Idtr;\r
+ VOID *GdtForAp;\r
+ VOID *IdtForAp;\r
+ VOID *MachineCheckHandlerForAp;\r
\r
if (!mAcpiS3Enable) {\r
return;\r
Gdtr = (IA32_DESCRIPTOR *)(UINTN)mAcpiCpuData.GdtrProfile;\r
Idtr = (IA32_DESCRIPTOR *)(UINTN)mAcpiCpuData.IdtrProfile;\r
\r
- mGdtForAp = AllocatePool ((Gdtr->Limit + 1) + (Idtr->Limit + 1) + mAcpiCpuData.ApMachineCheckHandlerSize);\r
- ASSERT (mGdtForAp != NULL);\r
- mIdtForAp = (VOID *) ((UINTN)mGdtForAp + (Gdtr->Limit + 1));\r
- mMachineCheckHandlerForAp = (VOID *) ((UINTN)mIdtForAp + (Idtr->Limit + 1));\r
+ GdtForAp = AllocatePool ((Gdtr->Limit + 1) + (Idtr->Limit + 1) + mAcpiCpuData.ApMachineCheckHandlerSize);\r
+ ASSERT (GdtForAp != NULL);\r
+ IdtForAp = (VOID *) ((UINTN)GdtForAp + (Gdtr->Limit + 1));\r
+ MachineCheckHandlerForAp = (VOID *) ((UINTN)IdtForAp + (Idtr->Limit + 1));\r
+\r
+ CopyMem (GdtForAp, (VOID *)Gdtr->Base, Gdtr->Limit + 1);\r
+ CopyMem (IdtForAp, (VOID *)Idtr->Base, Idtr->Limit + 1);\r
+ CopyMem (MachineCheckHandlerForAp, (VOID *)(UINTN)mAcpiCpuData.ApMachineCheckHandlerBase, mAcpiCpuData.ApMachineCheckHandlerSize);\r
\r
- CopyMem (mGdtForAp, (VOID *)Gdtr->Base, Gdtr->Limit + 1);\r
- CopyMem (mIdtForAp, (VOID *)Idtr->Base, Idtr->Limit + 1);\r
- CopyMem (mMachineCheckHandlerForAp, (VOID *)(UINTN)mAcpiCpuData.ApMachineCheckHandlerBase, mAcpiCpuData.ApMachineCheckHandlerSize);\r
+ Gdtr->Base = (UINTN)GdtForAp;\r
+ Idtr->Base = (UINTN)IdtForAp;\r
+ mAcpiCpuData.ApMachineCheckHandlerBase = (EFI_PHYSICAL_ADDRESS)(UINTN)MachineCheckHandlerForAp;\r
}\r
\r
/**\r