///\r
#define IA32_PG_P BIT0\r
#define IA32_PG_RW BIT1\r
+#define IA32_PG_U BIT2\r
#define IA32_PG_WT BIT3\r
#define IA32_PG_CD BIT4\r
#define IA32_PG_A BIT5\r
+#define IA32_PG_D BIT6\r
#define IA32_PG_PS BIT7\r
#define IA32_PG_PAT_2M BIT12\r
#define IA32_PG_PAT_4K IA32_PG_PS\r
#define IA32_PG_PMNT BIT62\r
#define IA32_PG_NX BIT63\r
\r
+#define PAGE_ATTRIBUTE_BITS (IA32_PG_RW | IA32_PG_P)\r
+//\r
+// Bits 1, 2, 5, 6 are reserved in the IA32 PAE PDPTE\r
+// X64 PAE PDPTE does not have such restriction\r
+//\r
+#define IA32_PAE_PDPTE_ATTRIBUTE_BITS (IA32_PG_P)\r
+\r
//\r
// Size of Task-State Segment defined in IA32 Manual\r
//\r
Create 4G PageTable in SMRAM.\r
\r
@param ExtraPages Additional page numbers besides for 4G memory\r
+ @param Is32BitPageTable Whether the page table is 32-bit PAE\r
@return PageTable Address\r
\r
**/\r
UINT32\r
Gen4GPageTable (\r
- IN UINTN ExtraPages\r
+ IN UINTN ExtraPages,\r
+ IN BOOLEAN Is32BitPageTable\r
);\r
\r
\r