//\r
UINTN mMsrDsAreaSize = SMM_PROFILE_DTS_SIZE;\r
\r
-//\r
-// The flag indicates if execute-disable is supported by processor.\r
-//\r
-BOOLEAN mXdSupported = FALSE;\r
-\r
//\r
// The flag indicates if execute-disable is enabled on processor.\r
//\r
//\r
// The flag indicates if BTS is supported by processor.\r
//\r
-BOOLEAN mBtsSupported = FALSE;\r
+BOOLEAN mBtsSupported = TRUE;\r
\r
//\r
// The flag indicates if SMM profile starts to record data.\r
\r
ApicId = GetApicId ();\r
\r
- for (Index = 0; Index < PcdGet32 (PcdCpuMaxLogicalProcessorNumber); Index++) {\r
+ for (Index = 0; Index < mMaxNumberOfCpus; Index++) {\r
if (gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId == ApicId) {\r
return Index;\r
}\r
//\r
continue;\r
}\r
+ if ((*Pde & IA32_PG_PS) != 0) {\r
+ //\r
+ // This is 1G entry, skip it\r
+ //\r
+ continue;\r
+ }\r
Pte = (UINT64 *)(UINTN)(*Pde & PHYSICAL_ADDRESS_MASK);\r
if (Pte == 0) {\r
continue;\r
//\r
continue;\r
}\r
+ if ((*Pde & IA32_PG_PS) != 0) {\r
+ //\r
+ // This is 1G entry, set NX bit and skip it\r
+ //\r
+ if (mXdSupported) {\r
+ *Pde = *Pde | IA32_PG_NX;\r
+ }\r
+ continue;\r
+ }\r
Pte = (UINT64 *)(UINTN)(*Pde & PHYSICAL_ADDRESS_MASK);\r
if (Pte == 0) {\r
continue;\r
UINTN MsrDsAreaSizePerCpu;\r
UINTN TotalSize;\r
\r
- mPFEntryCount = (UINTN *)AllocateZeroPool (sizeof (UINTN) * PcdGet32 (PcdCpuMaxLogicalProcessorNumber));\r
+ mPFEntryCount = (UINTN *)AllocateZeroPool (sizeof (UINTN) * mMaxNumberOfCpus);\r
ASSERT (mPFEntryCount != NULL);\r
mLastPFEntryValue = (UINT64 (*)[MAX_PF_ENTRY_COUNT])AllocateZeroPool (\r
- sizeof (mLastPFEntryValue[0]) * PcdGet32 (PcdCpuMaxLogicalProcessorNumber));\r
+ sizeof (mLastPFEntryValue[0]) * mMaxNumberOfCpus);\r
ASSERT (mLastPFEntryValue != NULL);\r
mLastPFEntryPointer = (UINT64 *(*)[MAX_PF_ENTRY_COUNT])AllocateZeroPool (\r
- sizeof (mLastPFEntryPointer[0]) * PcdGet32 (PcdCpuMaxLogicalProcessorNumber));\r
+ sizeof (mLastPFEntryPointer[0]) * mMaxNumberOfCpus);\r
ASSERT (mLastPFEntryPointer != NULL);\r
\r
//\r
mSmmProfileBase->NumCpus = gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;\r
\r
if (mBtsSupported) {\r
- mMsrDsArea = (MSR_DS_AREA_STRUCT **)AllocateZeroPool (sizeof (MSR_DS_AREA_STRUCT *) * PcdGet32 (PcdCpuMaxLogicalProcessorNumber));\r
+ mMsrDsArea = (MSR_DS_AREA_STRUCT **)AllocateZeroPool (sizeof (MSR_DS_AREA_STRUCT *) * mMaxNumberOfCpus);\r
ASSERT (mMsrDsArea != NULL);\r
- mMsrBTSRecord = (BRANCH_TRACE_RECORD **)AllocateZeroPool (sizeof (BRANCH_TRACE_RECORD *) * PcdGet32 (PcdCpuMaxLogicalProcessorNumber));\r
+ mMsrBTSRecord = (BRANCH_TRACE_RECORD **)AllocateZeroPool (sizeof (BRANCH_TRACE_RECORD *) * mMaxNumberOfCpus);\r
ASSERT (mMsrBTSRecord != NULL);\r
- mMsrPEBSRecord = (PEBS_RECORD **)AllocateZeroPool (sizeof (PEBS_RECORD *) * PcdGet32 (PcdCpuMaxLogicalProcessorNumber));\r
+ mMsrPEBSRecord = (PEBS_RECORD **)AllocateZeroPool (sizeof (PEBS_RECORD *) * mMaxNumberOfCpus);\r
ASSERT (mMsrPEBSRecord != NULL);\r
\r
mMsrDsAreaBase = (MSR_DS_AREA_STRUCT *)((UINTN)Base + mSmmProfileSize);\r
- MsrDsAreaSizePerCpu = mMsrDsAreaSize / PcdGet32 (PcdCpuMaxLogicalProcessorNumber);\r
+ MsrDsAreaSizePerCpu = mMsrDsAreaSize / mMaxNumberOfCpus;\r
mBTSRecordNumber = (MsrDsAreaSizePerCpu - sizeof(PEBS_RECORD) * PEBS_RECORD_NUMBER - sizeof(MSR_DS_AREA_STRUCT)) / sizeof(BRANCH_TRACE_RECORD);\r
- for (Index = 0; Index < PcdGet32 (PcdCpuMaxLogicalProcessorNumber); Index++) {\r
+ for (Index = 0; Index < mMaxNumberOfCpus; Index++) {\r
mMsrDsArea[Index] = (MSR_DS_AREA_STRUCT *)((UINTN)mMsrDsAreaBase + MsrDsAreaSizePerCpu * Index);\r
mMsrBTSRecord[Index] = (BRANCH_TRACE_RECORD *)((UINTN)mMsrDsArea[Index] + sizeof(MSR_DS_AREA_STRUCT));\r
mMsrPEBSRecord[Index] = (PEBS_RECORD *)((UINTN)mMsrDsArea[Index] + MsrDsAreaSizePerCpu - sizeof(PEBS_RECORD) * PEBS_RECORD_NUMBER);\r
/**\r
Check if XD feature is supported by a processor.\r
\r
- @param[in,out] Buffer The pointer to private data buffer.\r
-\r
**/\r
VOID\r
-EFIAPI\r
CheckFeatureSupported (\r
- IN OUT VOID *Buffer\r
+ VOID\r
)\r
{\r
- UINT32 RegEax;\r
- UINT32 RegEdx;\r
+ UINT32 RegEax;\r
+ UINT32 RegEdx;\r
+ MSR_IA32_MISC_ENABLE_REGISTER MiscEnableMsr;\r
\r
if (mXdSupported) {\r
AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);\r
// BTINT bits in the MSR_DEBUGCTLA MSR.\r
// 2. The IA32_DS_AREA MSR can be programmed to point to the DS save area.\r
//\r
- if (AsmMsrBitFieldRead64 (MSR_IA32_MISC_ENABLE, 11, 11) == 1) {\r
+ MiscEnableMsr.Uint64 = AsmReadMsr64 (MSR_IA32_MISC_ENABLE);\r
+ if (MiscEnableMsr.Bits.BTS == 1) {\r
//\r
- // BTS facilities is not supported if MSR_IA32_MISC_ENABLE BIT11 is set.\r
+ // BTS facilities is not supported if MSR_IA32_MISC_ENABLE.BTS bit is set.\r
//\r
mBtsSupported = FALSE;\r
}\r
}\r
}\r
\r
-/**\r
- Check if XD and BTS features are supported by all processors.\r
-\r
-**/\r
-VOID\r
-CheckProcessorFeature (\r
- VOID\r
- )\r
-{\r
- EFI_STATUS Status;\r
- EFI_MP_SERVICES_PROTOCOL *MpServices;\r
-\r
- Status = gBS->LocateProtocol (&gEfiMpServiceProtocolGuid, NULL, (VOID **)&MpServices);\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- //\r
- // First detect if XD and BTS are supported\r
- //\r
- mXdSupported = TRUE;\r
- mBtsSupported = TRUE;\r
-\r
- //\r
- // Check if XD and BTS are supported on all processors.\r
- //\r
- CheckFeatureSupported (NULL);\r
-\r
- //\r
- //Check on other processors if BSP supports this\r
- //\r
- if (mXdSupported || mBtsSupported) {\r
- MpServices->StartupAllAPs (\r
- MpServices,\r
- CheckFeatureSupported,\r
- TRUE,\r
- NULL,\r
- 0,\r
- NULL,\r
- NULL\r
- );\r
- }\r
-}\r
-\r
-/**\r
- Enable XD feature.\r
-\r
-**/\r
-VOID\r
-ActivateXd (\r
- VOID\r
- )\r
-{\r
- UINT64 MsrRegisters;\r
-\r
- MsrRegisters = AsmReadMsr64 (MSR_EFER);\r
- if ((MsrRegisters & MSR_EFER_XD) != 0) {\r
- return ;\r
- }\r
- MsrRegisters |= MSR_EFER_XD;\r
- AsmWriteMsr64 (MSR_EFER, MsrRegisters);\r
-}\r
-\r
/**\r
Enable single step.\r
\r
if ((DebugCtl & MSR_DEBUG_CTL_LBR) != 0) {\r
return ;\r
}\r
- AsmWriteMsr64 (MSR_LER_FROM_LIP, 0);\r
- AsmWriteMsr64 (MSR_LER_TO_LIP, 0);\r
DebugCtl |= MSR_DEBUG_CTL_LBR;\r
AsmWriteMsr64 (MSR_DEBUG_CTL, DebugCtl);\r
}\r
VOID\r
)\r
{\r
- SmmRegisterExceptionHandler (&mSmmCpuService, EXCEPT_IA32_DEBUG, DebugExceptionHandler);\r
+ EFI_STATUS Status;\r
+\r
+ Status = SmmRegisterExceptionHandler (&mSmmCpuService, EXCEPT_IA32_DEBUG, DebugExceptionHandler);\r
+ ASSERT_EFI_ERROR (Status);\r
}\r
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