ArmPlatformPkg/PL011SerialPortLib: use untyped PCD for register base

[mirror_edk2.git] / UefiCpuPkg / SecCore / SecMain.c

diff --git a/UefiCpuPkg/SecCore/SecMain.c b/UefiCpuPkg/SecCore/SecMain.c
index 18b7782bb87d905ff8fb98943e9c90d2e4973aed..b24e190617764ed244344b21dc071303110225e3 100644 (file)
--- a/UefiCpuPkg/SecCore/SecMain.c
+++ b/UefiCpuPkg/SecCore/SecMain.c
@@ -1,7 +1,7 @@
 /** @file\r
   C functions in SEC\r
 \r
-  Copyright (c) 2008 - 2017, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.<BR>\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -21,6 +21,14 @@ EFI_PEI_TEMPORARY_RAM_DONE_PPI gSecTemporaryRamDonePpi = {
 EFI_SEC_PLATFORM_INFORMATION_PPI  mSecPlatformInformationPpi = { SecPlatformInformation };\r
 \r
 EFI_PEI_PPI_DESCRIPTOR            mPeiSecPlatformInformationPpi[] = {\r
+  {\r
+    //\r
+    // SecPerformance PPI notify descriptor.\r
+    //\r
+    EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK,\r
+    &gPeiSecPerformancePpiGuid,\r
+    (VOID *) (UINTN) SecPerformancePpiCallBack\r
+  },\r
   {\r
     EFI_PEI_PPI_DESCRIPTOR_PPI,\r
     &gEfiTemporaryRamDonePpiGuid,\r
@@ -55,6 +63,44 @@ SecStartupPhase2(
   IN VOID                     *Context\r
   );\r
 \r
+/**\r
+  Entry point of the notification callback function itself within the PEIM.\r
+  It is to get SEC performance data and build HOB to convey the SEC performance\r
+  data to DXE phase.\r
+\r
+  @param  PeiServices      Indirect reference to the PEI Services Table.\r
+  @param  NotifyDescriptor Address of the notification descriptor data structure.\r
+  @param  Ppi              Address of the PPI that was installed.\r
+\r
+  @return Status of the notification.\r
+          The status code returned from this function is ignored.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SecPerformancePpiCallBack (\r
+  IN EFI_PEI_SERVICES           **PeiServices,\r
+  IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,\r
+  IN VOID                       *Ppi\r
+  )\r
+{\r
+  EFI_STATUS                    Status;\r
+  PEI_SEC_PERFORMANCE_PPI       *SecPerf;\r
+  FIRMWARE_SEC_PERFORMANCE      Performance;\r
+\r
+  SecPerf = (PEI_SEC_PERFORMANCE_PPI *) Ppi;\r
+  Status = SecPerf->GetPerformance ((CONST EFI_PEI_SERVICES **) PeiServices, SecPerf, &Performance);\r
+  if (!EFI_ERROR (Status)) {\r
+    BuildGuidDataHob (\r
+      &gEfiFirmwarePerformanceGuid,\r
+      &Performance,\r
+      sizeof (FIRMWARE_SEC_PERFORMANCE)\r
+    );\r
+    DEBUG ((DEBUG_INFO, "FPDT: SEC Performance Hob ResetEnd = %ld\n", Performance.ResetEnd));\r
+  }\r
+\r
+  return Status;\r
+}\r
+\r
 /**\r
 \r
   Entry point to the C language phase of SEC. After the SEC assembly\r
@@ -67,6 +113,7 @@ SecStartupPhase2(
   @param BootFirmwareVolume  Base address of the Boot Firmware Volume.\r
 **/\r
 VOID\r
+NORETURN\r
 EFIAPI\r
 SecStartup (\r
   IN UINT32                   SizeOfRam,\r
@@ -143,7 +190,7 @@ SecStartup (
   //\r
   SecCoreData.DataSize               = (UINT16) sizeof (EFI_SEC_PEI_HAND_OFF);\r
   SecCoreData.BootFirmwareVolumeBase = BootFirmwareVolume;\r
-  SecCoreData.BootFirmwareVolumeSize = (UINTN)(0x100000000ULL - (UINTN) BootFirmwareVolume);\r
+  SecCoreData.BootFirmwareVolumeSize = (UINTN)((EFI_FIRMWARE_VOLUME_HEADER *) BootFirmwareVolume)->FvLength;\r
   SecCoreData.TemporaryRamBase       = (VOID*)(UINTN) TempRamBase;\r
   SecCoreData.TemporaryRamSize       = SizeOfRam;\r
   SecCoreData.PeiTemporaryRamBase    = SecCoreData.TemporaryRamBase;\r
@@ -155,6 +202,11 @@ SecStartup (
   // Initialize Debug Agent to support source level debug in SEC/PEI phases before memory ready.\r
   //\r
   InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, &SecCoreData, SecStartupPhase2);\r
+\r
+  //\r
+  // Should not come here.\r
+  //\r
+  UNREACHABLE ();\r
 }\r
 \r
 /**\r
@@ -235,7 +287,7 @@ SecStartupPhase2(
     // will be built based on them in PEI phase.\r
     //\r
     SecCoreData->PeiTemporaryRamBase = (VOID *)(((UINTN)SecCoreData->PeiTemporaryRamBase + 7) & ~0x07);\r
-    SecCoreData->PeiTemporaryRamSize &= ~0x07;\r
+    SecCoreData->PeiTemporaryRamSize &= ~(UINTN)0x07;\r
   } else {\r
     //\r
     // No addition PPI, PpiList directly point to the common PPI list.\r