Upload BSD-licensed Vlv2TbltDevicePkg and Vlv2DeviceRefCodePkg to

[mirror_edk2.git] / Vlv2DeviceRefCodePkg / AcpiTablesPCAT / PCI_DRC.ASL

diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PCI_DRC.ASL b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PCI_DRC.ASL
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+/**************************************************************************;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;*    Intel Corporation - ACPI Reference Code for the Baytrail            *;\r
+;*    Family of Customer Reference Boards.                                *;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;*    Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved    *;\r
+;\r
+; This program and the accompanying materials are licensed and made available under\r
+; the terms and conditions of the BSD License that accompanies this distribution.\r
+; The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;**************************************************************************/\r
+\r
+\r
+\r
+Scope (\_SB.PCI0)\r
+{\r
+\r
+  Device(PDRC)   // PCI Device Resource Consumption\r
+  {\r
+    Name(_HID,EISAID("PNP0C02"))\r
+\r
+    Name(_UID,1)\r
+\r
+    Name(BUF0,ResourceTemplate()\r
+    {\r
+      //\r
+      // PCI Express BAR _BAS and _LEN will be updated in _CRS below according to B0:D0:F0:Reg.60h\r
+      // Forced hard code at the moment.\r
+      //\r
+      //Memory32Fixed(ReadWrite,0,0,PCIX)       // PCIEX BAR\r
+      Memory32Fixed(ReadWrite,0x0E0000000,0x010000000,PCIX)\r
+\r
+      //\r
+      // SPI BAR. Check if the hard code meets the real configuration.\r
+      // If not, dynamically update it like the _CRS method below.\r
+      //\r
+      Memory32Fixed(ReadWrite,0x0FED01000,0x01000,SPIB) // SPI BAR\r
+\r
+      //\r
+      // PMC BAR. Check if the hard code meets the real configuration.\r
+      // If not, dynamically update it like the _CRS method below.\r
+      //\r
+      Memory32Fixed(ReadWrite,0x0FED03000,0x01000,PMCB) // PMC BAR\r
+\r
+      //\r
+      // SMB BAR. Check if the hard code meets the real configuration.\r
+      // If not, dynamically update it like the _CRS method below.\r
+      //\r
+      Memory32Fixed(ReadWrite,0x0FED04000,0x01000,SMBB) // SMB BAR\r
+\r
+      //\r
+      // IO BAR. Check if the hard code meets the real configuration.\r
+      // If not, dynamically update it like the _CRS method below.\r
+      //\r
+      Memory32Fixed(ReadWrite,0x0FED0C000,0x04000,IOBR) // IO BAR\r
+\r
+      //\r
+      // ILB BAR. Check if the hard code meets the real configuration.\r
+      // If not, dynamically update it like the _CRS method below.\r
+      //\r
+      Memory32Fixed(ReadWrite,0x0FED08000,0x01000,ILBB) // ILB BAR\r
+\r
+      //\r
+      // RCRB BAR _BAS will be updated in _CRS below according to B0:D31:F0:Reg.F0h\r
+      //\r
+      Memory32Fixed(ReadWrite,0x0FED1C000,0x01000,RCRB) // RCRB BAR\r
+\r
+      //\r
+      // Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF)\r
+      //\r
+      Memory32Fixed (ReadOnly, 0x0FEE00000, 0x0100000, LIOH)\r
+\r
+      //\r
+      // MPHY BAR. Check if the hard code meets the real configuration.\r
+      // If not, dynamically update it like the _CRS method below.\r
+      //\r
+      Memory32Fixed(ReadWrite,0x0FEF00000,0x0100000,MPHB)       // MPHY BAR\r
+    })\r
+\r
+    Method(_CRS,0,Serialized)\r
+    {\r
+\r
+      Return(BUF0)\r
+    }\r
+\r
+  }\r
+}\r