+++ /dev/null
-/**************************************************************************;\r
-;* *;\r
-;* *;\r
-;* Intel Corporation - ACPI Reference Code for the Baytrail *;\r
-;* Family of Customer Reference Boards. *;\r
-;* *;\r
-;* *;\r
-;* Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved *;\r
-;\r
-; SPDX-License-Identifier: BSD-2-Clause-Patent\r
-;\r
-;* *;\r
-;* *;\r
-;**************************************************************************/\r
-DefinitionBlock (\r
- "Rtd3.aml",\r
- "SSDT",\r
- 1,\r
- "AcpiRef",\r
- "Msg_Rtd3",\r
- 0x1000\r
-)\r
-{\r
- External(RTD3) //flag if RTD3 is enabled\r
-\r
- If(LEqual(RTD3,1))\r
- {\r
- Scope (\_SB)\r
- {\r
- Name(OSCI, 0) // \_SB._OSC DWORD2 input\r
- Name(OSCO, 0) // \_SB._OSC DWORD2 output\r
-\r
- //Arg0 -- A buffer containing UUID\r
- //Arg1 -- An Interger containing a Revision ID of the buffer format\r
- //Arg2 -- An interger containing a count of entries in Arg3\r
- //Arg3 -- A buffer containing a list of DWORD capacities\r
- Method(_OSC, 4, NotSerialized)\r
- {\r
- // Check for proper UUID\r
- If(LEqual(Arg0, ToUUID("0811B06E-4A27-44F9-8D60-3CBBC22E7B48")))\r
- {\r
- CreateDWordField(Arg3,0,CDW1) //bit1,2 is always clear\r
- CreateDWordField(Arg3,4,CDW2) //Table 6-147 from ACPI spec\r
-\r
- Store(CDW2, OSCI) // Save DWord2\r
- Or(OSCI, 0x4, OSCO) // Only allow _PR3 support\r
-\r
- If(LNotEqual(Arg1,One))\r
- {\r
- Or(CDW1,0x08,CDW1) // Unknown revision\r
- }\r
-\r
- If(LNotEqual(OSCI, OSCO))\r
- {\r
- Or(CDW1,0x10,CDW1) // Capabilities bits were masked\r
- }\r
-\r
- Store(OSCO, CDW2) // Replace DWord2\r
- Return(Arg3)\r
- } Else\r
- {\r
- Or(CDW1,4,CDW1) // Unrecognized UUID\r
- Return(Arg3)\r
- }\r
- }// End _OSC\r
- }\r
- }//end of RTD3 condition\r
-\r
-\r
- //USB RTD3 code\r
- If(LEqual(RTD3,1))\r
- {\r
- Scope(\_SB.PCI0.EHC1.HUBN.PR01.PR13)\r
- {\r
- Name(_PR0, Package() {\PR34})\r
- Name(_PR3, Package() {\PR34})\r
-\r
- Method(_S0W, 0)\r
- {\r
- If(And(\_SB.OSCO, 0x04)) // PMEs can be genrated from D3cold\r
- {\r
- Return(4) // OS comprehends D3cold, as described via \_SB._OSC\r
- } Else\r
- {\r
- Return(3)\r
- }\r
- } // End _S0W\r
- }\r
-\r
- Scope(\_SB.PCI0.EHC1.HUBN.PR01.PR14)\r
- {\r
- Name(_PR0, Package() {\PR34})\r
- Name(_PR3, Package() {\PR34})\r
-\r
- Method(_S0W, 0)\r
- {\r
- If(And(\_SB.OSCO, 0x04))\r
- {\r
- Return(4)\r
- } Else\r
- {\r
- Return(3)\r
- }\r
- } // End _S0W\r
- }\r
-\r
-\r
- Scope(\_SB.PCI0.EHC1.HUBN.PR01.PR15)\r
- {\r
- Name(_PR0, Package() {\PR56})\r
- Name(_PR3, Package() {\PR56})\r
-\r
- Method(_S0W, 0)\r
- {\r
- If(And(\_SB.OSCO, 0x04))\r
- {\r
- Return(4)\r
- } Else\r
- {\r
- Return(3)\r
- }\r
- } // End _S0W\r
- }\r
-\r
- Scope(\_SB.PCI0.EHC1.HUBN.PR01.PR16)\r
- {\r
- Name(_PR0, Package() {\PR56})\r
- Name(_PR3, Package() {\PR56})\r
-\r
- Method(_S0W, 0)\r
- {\r
- If(And(\_SB.OSCO, 0x04))\r
- {\r
- Return(4)\r
- } Else\r
- {\r
- Return(3)\r
- }\r
- } // End _S0W\r
- }\r
-\r
- Scope(\_SB.PCI0.XHC1) // XHCI host only controller\r
- {\r
-\r
- Method(_PS0,0,Serialized) // set device into D0 state\r
- {\r
- }\r
-\r
- Method(_PS3,0,Serialized) // place device into D3H state\r
- {\r
- //write to PMCSR\r
- }\r
-\r
- Method(_DSW, 3,Serialized) // enable or disable the device’s ability to wake a sleeping system.\r
- {\r
- }\r
- }\r
-\r
- Scope(\_SB.PCI0.XHC1.RHUB.HS01)\r
- {\r
-\r
- }\r
-\r
- Scope(\_SB.PCI0.XHC1.RHUB.SSP1)\r
- {\r
-\r
- }\r
-\r
- Scope(\_SB.PCI0.XHC2) // OTG\r
- {\r
-\r
- Method(_PS0,0,Serialized) // set device into D0 state\r
- {\r
- }\r
-\r
- Method(_PS3,0,Serialized) // place device into D3H state\r
- {\r
- //write to PMCSR\r
- }\r
-\r
- Method(_DSW, 3,Serialized) // enable or disable the device’s ability to wake a sleeping system.\r
- {\r
- }\r
- }\r
-\r
- Scope(\_SB.PCI0.XHC2.RHUB.HS01)\r
- {\r
-\r
- }\r
-\r
- Scope(\_SB.PCI0.XHC2.RHUB.SSP1)\r
- {\r
-\r
- }\r
- } //If(LEqual(RTD3,1)) USB\r
-\r
-}//end of SSDT\r