edk2: Remove packages moved to edk2-platforms

[mirror_edk2.git] / Vlv2DeviceRefCodePkg / ValleyView2Soc / SouthCluster / Include / PchRegs / PchRegsPcie.h

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsPcie.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsPcie.h
deleted file mode 100644 (file)
index 8b1ae40..0000000
--- a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsPcie.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/**\r
-\r
-Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved\r
-\r
-  SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
-\r
-\r
-  @file\r
-  PchRegsPcie.h\r
-\r
-  @brief\r
-  Register names for VLV PCI-E root port devices\r
-\r
-  Conventions:\r
-\r
-  - Prefixes:\r
-    Definitions beginning with "R_" are registers\r
-    Definitions beginning with "B_" are bits within registers\r
-    Definitions beginning with "V_" are meaningful values of bits within the registers\r
-    Definitions beginning with "S_" are register sizes\r
-    Definitions beginning with "N_" are the bit position\r
-  - In general, PCH registers are denoted by "_PCH_" in register names\r
-  - Registers / bits that are different between PCH generations are denoted by\r
-    "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"\r
-  - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"\r
-    at the end of the register/bit names\r
-  - Registers / bits of new devices introduced in a PCH generation will be just named\r
-    as "_PCH_" without <generation_name> inserted.\r
-\r
---*/\r
-#ifndef _PCH_REGS_PCIE_H_\r
-#define _PCH_REGS_PCIE_H_\r
-\r
-#define PCH_PCIE_MAX_ROOT_PORTS                            4\r
-\r
-///\r
-/// VLV PCI Express Root Ports (D28:F0~F3)\r
-///\r
-#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS              28\r
-#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1           0\r
-#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2           1\r
-#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3           2\r
-#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4           3\r
-\r
-#define R_PCH_PCIE_ID                                      0x00  // Identifiers\r
-#define B_PCH_PCIE_ID_DID                                  0xFFFF0000 // Device ID\r
-#define V_PCH_PCIE_DEVICE_ID_0                             0x0F48  // PCIE Root Port #1\r
-#define V_PCH_PCIE_DEVICE_ID_1                             0x0F4A  // PCIE Root Port #2\r
-#define V_PCH_PCIE_DEVICE_ID_2                             0x0F4C  // PCIE Root Port #3\r
-#define V_PCH_PCIE_DEVICE_ID_3                             0x0F4E  // PCIE Root Port #4\r
-#define B_PCH_PCIE_ID_VID                                  0x0000FFFF // Vendor ID\r
-#define V_PCH_PCIE_VENDOR_ID                               V_PCH_INTEL_VENDOR_ID\r
-\r
-\r
-#define R_PCH_PCIE_BNUM_SLT                                0x18  // Bus Numbers; Secondary Latency Timer\r
-#define B_PCH_PCIE_BNUM_SLT_SLT                            0xFF000000 // Secondary Latency Timer\r
-#define B_PCH_PCIE_BNUM_SLT_SBBN                           0x00FF0000 // Subordinate Bus Number\r
-#define B_PCH_PCIE_BNUM_SLT_SCBN                           0x0000FF00 // Secondary Bus Number\r
-#define B_PCH_PCIE_BNUM_SLT_PBN                            0x000000FF // Primary Bus Number\r
-#define R_PCH_PCIE_CAPP                                    0x34  // Capabilities List Pointer\r
-#define B_PCH_PCIE_CAPP                                    0xFF  // Capabilities Pointer\r
-\r
-#define R_PCH_PCIE_SLCTL_SLSTS                             0x58  // Slot Control; Slot Status\r
-#define S_PCH_PCIE_SLCTL_SLSTS                             4\r
-#define B_PCH_PCIE_SLCTL_SLSTS_DLLSC                       BIT24 // Data Link Layer State Changed\r
-#define B_PCH_PCIE_SLCTL_SLSTS_PDS                         BIT22 // Presence Detect State\r
-#define B_PCH_PCIE_SLCTL_SLSTS_MS                          BIT21 // MRL Sensor State\r
-#define B_PCH_PCIE_SLCTL_SLSTS_PDC                         BIT19 // Presence Detect Changed\r
-#define B_PCH_PCIE_SLCTL_SLSTS_MSC                         BIT18 // MRL Sensor Changed\r
-#define B_PCH_PCIE_SLCTL_SLSTS_PFD                         BIT17 // Power Fault Detected\r
-#define B_PCH_PCIE_SLCTL_SLSTS_DLLSCE                      BIT12 // Data Link Layer State Changed Enable\r
-#define B_PCH_PCIE_SLCTL_SLSTS_PCC                         BIT10 // Power Controller Control\r
-#define B_PCH_PCIE_SLCTL_SLSTS_HPE                         BIT5  // Hot Plug Interrupt Enable\r
-#define B_PCH_PCIE_SLCTL_SLSTS_CCE                         BIT4  // Command Completed Interrupt Enable\r
-#define B_PCH_PCIE_SLCTL_SLSTS_PDE                         BIT3  // Presence Detect Changed Enable\r
-\r
-#define R_PCH_PCIE_SVID                                    0x94  // Subsystem Vendor IDs\r
-#define S_PCH_PCIE_SVID                                    4\r
-#define B_PCH_PCIE_SVID_SID                                0xFFFF0000 // Subsystem Identifier\r
-#define B_PCH_PCIE_SVID_SVID                               0x0000FFFF // Subsystem Vendor Identifier\r
-\r
-#endif\r