+++ /dev/null
-/** @file\r
- Multiplatform initialization.\r
-\r
- Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>\r
- \r\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
- \r\r
-\r
-**/\r
-\r
-#include <MultiPlatformLib.h>\r
-\r
-/**\r
- Platform Type detection. Because the PEI globle variable\r
- is in the flash, it could not change directly.So use\r
- 2 PPIs to distinguish the platform type.\r
-\r
- @param FfsHeader Pointer to Firmware File System file header.\r
- @param PeiServices General purpose services available to every PEIM.\r
-\r
- @retval EFI_SUCCESS Memory initialization completed successfully.\r
- @retval Others All other error conditions encountered result in an ASSERT.\r
-\r
-**/\r
-EFI_STATUS\r
-MultiPlatformInfoInit (\r
- IN CONST EFI_PEI_SERVICES **PeiServices,\r
- IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob\r
- )\r
-{\r
- UINT32 PcieLength;\r
-\r
-\r
- PlatformInfoHob->IohSku = MmPci16(0, MC_BUS, MC_DEV, MC_FUN, PCI_DEVICE_ID_OFFSET);\r
-\r
- PlatformInfoHob->IohRevision = MmPci8(0, MC_BUS, MC_DEV, MC_FUN, PCI_REVISION_ID_OFFSET);\r
-\r
- //\r
- // Update ICH Type\r
- //\r
- //\r
- // Device ID\r
- //\r
- PlatformInfoHob->IchSku = PchLpcPciCfg16(PCI_DEVICE_ID_OFFSET);\r
-\r
- PlatformInfoHob->IchRevision = PchLpcPciCfg8(PCI_REVISION_ID_OFFSET);\r
-\r
- //\r
- //64MB\r
- //\r
- PcieLength = 0x04000000;\r
-\r
- //\r
- // Don't support BASE above 4GB currently.\r
- //\r
- PlatformInfoHob->PciData.PciExpressSize = PcieLength;\r
- PlatformInfoHob->PciData.PciExpressBase = PcdGet64 (PcdPciExpressBaseAddress);\r
-\r
- PlatformInfoHob->PciData.PciResourceMem32Base = (UINT32) (PlatformInfoHob->PciData.PciExpressBase - RES_MEM32_MIN_LEN);\r
- PlatformInfoHob->PciData.PciResourceMem32Limit = (UINT32) (PlatformInfoHob->PciData.PciExpressBase -1);\r
-\r
- PlatformInfoHob->PciData.PciResourceMem64Base = RES_MEM64_36_BASE;\r
- PlatformInfoHob->PciData.PciResourceMem64Limit = RES_MEM64_36_LIMIT;\r
- PlatformInfoHob->CpuData.CpuAddressWidth = 36;\r
-\r
- PlatformInfoHob->MemData.MemMir0 = PlatformInfoHob->PciData.PciResourceMem64Base;\r
- PlatformInfoHob->MemData.MemMir1 = PlatformInfoHob->PciData.PciResourceMem64Limit + 1;\r
-\r
- PlatformInfoHob->PciData.PciResourceMinSecBus = 1; //can be changed by SystemConfiguration->PciMinSecondaryBus;\r
-\r
- //\r
- // Set MemMaxTolm to the lowest address between PCIe Base and PCI32 Base.\r
- //\r
- if (PlatformInfoHob->PciData.PciExpressBase > PlatformInfoHob->PciData.PciResourceMem32Base ) {\r
- PlatformInfoHob->MemData.MemMaxTolm = (UINT32) PlatformInfoHob->PciData.PciResourceMem32Base;\r
- } else {\r
- PlatformInfoHob->MemData.MemMaxTolm = (UINT32) PlatformInfoHob->PciData.PciExpressBase;\r
- }\r
- PlatformInfoHob->MemData.MemTolm = PlatformInfoHob->MemData.MemMaxTolm;\r
-\r
- //\r
- // Platform PCI MMIO Size in unit of 1MB.\r
- //\r
- PlatformInfoHob->MemData.MmioSize = 0x1000 - (UINT16)(PlatformInfoHob->MemData.MemMaxTolm >> 20);\r
-\r
- //\r
- // Enable ICH IOAPIC\r
- //\r
- PlatformInfoHob->SysData.SysIoApicEnable = ICH_IOAPIC;\r
-\r
- DEBUG ((EFI_D_ERROR, "PlatformFlavor is %x (%x=tablet,%x=mobile,%x=desktop)\n",\r
- PlatformInfoHob->PlatformFlavor,\r
- FlavorTablet,\r
- FlavorMobile,\r
- FlavorDesktop));\r
-\r
- //\r
- // Get Platform Info and fill the Hob.\r
- //\r
- PlatformInfoHob->RevisonId = PLATFORM_INFO_HOB_REVISION;\r
-\r
- //\r
- // Get GPIO table\r
- //\r
- MultiPlatformGpioTableInit (PeiServices, PlatformInfoHob);\r
-\r
- //\r
- // Program GPIO\r
- //\r
- MultiPlatformGpioProgram (PeiServices, PlatformInfoHob);\r
-\r
- //\r
- // Update OemId\r
- //\r
- InitializeBoardOemId (PeiServices, PlatformInfoHob);\r
- InitializeBoardSsidSvid (PeiServices, PlatformInfoHob);\r
-\r
- return EFI_SUCCESS;\r
-}\r