--- /dev/null
+/*++\r
+\r
+ Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r
+ \r\r
+ This program and the accompanying materials are licensed and made available under\r\r
+ the terms and conditions of the BSD License that accompanies this distribution. \r\r
+ The full text of the license may be found at \r\r
+ http://opensource.org/licenses/bsd-license.php. \r\r
+ \r\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r\r
+ \r\r
+\r
+**/\r
+\r
+\r
+#ifndef _EFI_PCI_BUS_H_\r
+#define _EFI_PCI_BUS_H_\r
+\r
+#include <PiDxe.h>\r
+\r
+#include <Protocol/LoadedImage.h>\r
+#include <Protocol/PciHostBridgeResourceAllocation.h>\r
+#include <Protocol/PciIo.h>\r
+#include <Protocol/LoadFile2.h>\r
+#include <Protocol/PciRootBridgeIo.h>\r
+#include <Protocol/PciHotPlugRequest.h>\r
+#include <Protocol/DevicePath.h>\r
+#include <Protocol/PciPlatform.h>\r
+#include <Protocol/PciHotPlugInit.h>\r
+#include <Protocol/Decompress.h>\r
+#include <Protocol/BusSpecificDriverOverride.h>\r
+#include <Protocol/IncompatiblePciDeviceSupport.h>\r
+#include <Protocol/PciOverride.h>\r
+#include <Protocol/PciEnumerationComplete.h>\r
+\r
+#include <Library/DebugLib.h>\r
+#include <Library/UefiDriverEntryPoint.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/ReportStatusCodeLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/DevicePathLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/PeCoffLib.h>\r
+\r
+#include <IndustryStandard/Pci.h>\r
+#include <IndustryStandard/PeImage.h>\r
+#include <IndustryStandard/Acpi.h>\r
+\r
+typedef struct _PCI_IO_DEVICE PCI_IO_DEVICE;\r
+typedef struct _PCI_BAR PCI_BAR;\r
+\r
+#define EFI_PCI_RID(Bus, Device, Function) (((UINT32)Bus << 8) + ((UINT32)Device << 3) + (UINT32)Function)\r
+#define EFI_PCI_BUS_OF_RID(RID) ((UINT32)RID >> 8)\r
+\r
+#define EFI_PCI_IOV_POLICY_ARI 0x0001\r
+#define EFI_PCI_IOV_POLICY_SRIOV 0x0002\r
+#define EFI_PCI_IOV_POLICY_MRIOV 0x0004\r
+\r
+typedef enum {\r
+ PciBarTypeUnknown = 0,\r
+ PciBarTypeIo16,\r
+ PciBarTypeIo32,\r
+ PciBarTypeMem32,\r
+ PciBarTypePMem32,\r
+ PciBarTypeMem64,\r
+ PciBarTypePMem64,\r
+ PciBarTypeIo,\r
+ PciBarTypeMem,\r
+ PciBarTypeMaxType\r
+} PCI_BAR_TYPE;\r
+\r
+\r
+#define VGABASE1 0x3B0\r
+#define VGALIMIT1 0x3BB\r
+\r
+#define VGABASE2 0x3C0\r
+#define VGALIMIT2 0x3DF\r
+\r
+#define ISABASE 0x100\r
+#define ISALIMIT 0x3FF\r
+\r
+//\r
+// PCI BAR parameters\r
+//\r
+struct _PCI_BAR {\r
+ UINT64 BaseAddress;\r
+ UINT64 Length;\r
+ UINT64 Alignment;\r
+ PCI_BAR_TYPE BarType;\r
+ BOOLEAN Prefetchable;\r
+ UINT8 MemType;\r
+ UINT16 Offset;\r
+};\r
+\r
+//\r
+// defined in PCI Card Specification, 8.0\r
+//\r
+#define PCI_CARD_MEMORY_BASE_0 0x1C\r
+#define PCI_CARD_MEMORY_LIMIT_0 0x20\r
+#define PCI_CARD_MEMORY_BASE_1 0x24\r
+#define PCI_CARD_MEMORY_LIMIT_1 0x28\r
+#define PCI_CARD_IO_BASE_0_LOWER 0x2C\r
+#define PCI_CARD_IO_BASE_0_UPPER 0x2E\r
+#define PCI_CARD_IO_LIMIT_0_LOWER 0x30\r
+#define PCI_CARD_IO_LIMIT_0_UPPER 0x32\r
+#define PCI_CARD_IO_BASE_1_LOWER 0x34\r
+#define PCI_CARD_IO_BASE_1_UPPER 0x36\r
+#define PCI_CARD_IO_LIMIT_1_LOWER 0x38\r
+#define PCI_CARD_IO_LIMIT_1_UPPER 0x3A\r
+#define PCI_CARD_BRIDGE_CONTROL 0x3E\r
+\r
+#define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8\r
+#define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9\r
+\r
+#define PPB_BAR_0 0\r
+#define PPB_BAR_1 1\r
+#define PPB_IO_RANGE 2\r
+#define PPB_MEM32_RANGE 3\r
+#define PPB_PMEM32_RANGE 4\r
+#define PPB_PMEM64_RANGE 5\r
+#define PPB_MEM64_RANGE 0xFF\r
+\r
+#define P2C_BAR_0 0\r
+#define P2C_MEM_1 1\r
+#define P2C_MEM_2 2\r
+#define P2C_IO_1 3\r
+#define P2C_IO_2 4\r
+\r
+#define EFI_BRIDGE_IO32_DECODE_SUPPORTED 0x0001\r
+#define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED 0x0002\r
+#define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED 0x0004\r
+#define EFI_BRIDGE_IO16_DECODE_SUPPORTED 0x0008\r
+#define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010\r
+#define EFI_BRIDGE_MEM64_DECODE_SUPPORTED 0x0020\r
+#define EFI_BRIDGE_MEM32_DECODE_SUPPORTED 0x0040\r
+\r
+#define PCI_MAX_HOST_BRIDGE_NUM 0x0010\r
+\r
+//\r
+// Define option for attribute\r
+//\r
+#define EFI_SET_SUPPORTS 0\r
+#define EFI_SET_ATTRIBUTES 1\r
+\r
+#define PCI_IO_DEVICE_SIGNATURE SIGNATURE_32 ('p', 'c', 'i', 'o')\r
+\r
+struct _PCI_IO_DEVICE {\r
+ UINT32 Signature;\r
+ EFI_HANDLE Handle;\r
+ EFI_PCI_IO_PROTOCOL PciIo;\r
+ LIST_ENTRY Link;\r
+\r
+ EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;\r
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
+ EFI_LOAD_FILE2_PROTOCOL LoadFile2;\r
+\r
+ //\r
+ // PCI configuration space header type\r
+ //\r
+ PCI_TYPE00 Pci;\r
+\r
+ //\r
+ // Bus number, Device number, Function number\r
+ //\r
+ UINT8 BusNumber;\r
+ UINT8 DeviceNumber;\r
+ UINT8 FunctionNumber;\r
+\r
+ //\r
+ // BAR for this PCI Device\r
+ //\r
+ PCI_BAR PciBar[PCI_MAX_BAR];\r
+\r
+ //\r
+ // The bridge device this pci device is subject to\r
+ //\r
+ PCI_IO_DEVICE *Parent;\r
+\r
+ //\r
+ // A linked list for children Pci Device if it is bridge device\r
+ //\r
+ LIST_ENTRY ChildList;\r
+\r
+ //\r
+ // TURE if the PCI bus driver creates the handle for this PCI device\r
+ //\r
+ BOOLEAN Registered;\r
+\r
+ //\r
+ // TRUE if the PCI bus driver successfully allocates the resource required by\r
+ // this PCI device\r
+ //\r
+ BOOLEAN Allocated;\r
+\r
+ //\r
+ // The attribute this PCI device currently set\r
+ //\r
+ UINT64 Attributes;\r
+\r
+ //\r
+ // The attributes this PCI device actually supports\r
+ //\r
+ UINT64 Supports;\r
+\r
+ //\r
+ // The resource decode the bridge supports\r
+ //\r
+ UINT32 Decodes;\r
+\r
+ //\r
+ // TRUE if the ROM image is from the PCI Option ROM BAR\r
+ //\r
+ BOOLEAN EmbeddedRom;\r
+\r
+ //\r
+ // The OptionRom Size\r
+ //\r
+ UINT64 RomSize;\r
+\r
+ //\r
+ // The OptionRom Size\r
+ //\r
+ UINT64 RomBase;\r
+\r
+ //\r
+ // TRUE if all OpROM (in device or in platform specific position) have been processed\r
+ //\r
+ BOOLEAN AllOpRomProcessed;\r
+\r
+ //\r
+ // TRUE if there is any EFI driver in the OptionRom\r
+ //\r
+ BOOLEAN BusOverride;\r
+\r
+ //\r
+ // A list tracking reserved resource on a bridge device\r
+ //\r
+ LIST_ENTRY ReservedResourceList;\r
+\r
+ //\r
+ // A list tracking image handle of platform specific overriding driver\r
+ //\r
+ LIST_ENTRY OptionRomDriverList;\r
+\r
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ResourcePaddingDescriptors;\r
+ EFI_HPC_PADDING_ATTRIBUTES PaddingAttributes;\r
+\r
+ BOOLEAN IsPciExp;\r
+\r
+ //\r
+ // For SR-IOV\r
+ //\r
+ UINT8 PciExpressCapabilityOffset;\r
+ UINT32 AriCapabilityOffset;\r
+ UINT32 SrIovCapabilityOffset;\r
+ UINT32 MrIovCapabilityOffset;\r
+ PCI_BAR VfPciBar[PCI_MAX_BAR];\r
+ UINT32 SystemPageSize;\r
+ UINT16 InitialVFs;\r
+ UINT16 ReservedBusNum;\r
+\r
+ //\r
+ // Per PCI to PCI Bridge spec, I/O window is 4K aligned,\r
+ // but some chipsets support non-stardard I/O window aligments less than 4K.\r
+ // This field is used to support this case.\r
+ //\r
+ UINT16 BridgeIoAlignment;\r
+};\r
+\r
+#define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \\r
+ CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)\r
+\r
+#define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \\r
+ CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)\r
+\r
+#define PCI_IO_DEVICE_FROM_LINK(a) \\r
+ CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)\r
+\r
+#define PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS(a) \\r
+ CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE)\r
+\r
+\r
+\r
+//\r
+// Global Variables\r
+//\r
+extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gEfiIncompatiblePciDeviceSupport;\r
+extern EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding;\r
+extern EFI_COMPONENT_NAME_PROTOCOL gPciBusComponentName;\r
+extern EFI_COMPONENT_NAME2_PROTOCOL gPciBusComponentName2;\r
+extern BOOLEAN gFullEnumeration;\r
+extern UINTN gPciHostBridgeNumber;\r
+extern EFI_HANDLE gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];\r
+extern UINT64 gAllOne;\r
+extern UINT64 gAllZero;\r
+extern EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol;\r
+extern EFI_PCI_OVERRIDE_PROTOCOL *gPciOverrideProtocol;\r
+extern BOOLEAN mReserveIsaAliases;\r
+extern BOOLEAN mReserveVgaAliases;\r
+\r
+/**\r
+ Macro that checks whether device is a GFX device.\r
+\r
+ @param _p Specified device.\r
+\r
+ @retval TRUE Device is a a GFX device.\r
+ @retval FALSE Device is not a a GFX device.\r
+\r
+**/\r
+#define IS_PCI_GFX(_p) IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)\r
+\r
+/**\r
+ Test to see if this driver supports ControllerHandle. Any ControllerHandle\r
+ than contains a gEfiPciRootBridgeIoProtocolGuid protocol can be supported.\r
+\r
+ @param This Protocol instance pointer.\r
+ @param Controller Handle of device to test.\r
+ @param RemainingDevicePath Optional parameter use to pick a specific child.\r
+ device to start.\r
+\r
+ @retval EFI_SUCCESS This driver supports this device.\r
+ @retval EFI_ALREADY_STARTED This driver is already running on this device.\r
+ @retval other This driver does not support this device.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PciBusDriverBindingSupported (\r
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
+ IN EFI_HANDLE Controller,\r
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
+ );\r
+\r
+/**\r
+ Start this driver on ControllerHandle and enumerate Pci bus and start\r
+ all device under PCI bus.\r
+\r
+ @param This Protocol instance pointer.\r
+ @param Controller Handle of device to bind driver to.\r
+ @param RemainingDevicePath Optional parameter use to pick a specific child.\r
+ device to start.\r
+\r
+ @retval EFI_SUCCESS This driver is added to ControllerHandle.\r
+ @retval EFI_ALREADY_STARTED This driver is already running on ControllerHandle.\r
+ @retval other This driver does not support this device.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PciBusDriverBindingStart (\r
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
+ IN EFI_HANDLE Controller,\r
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
+ );\r
+\r
+/**\r
+ Stop this driver on ControllerHandle. Support stoping any child handles\r
+ created by this driver.\r
+\r
+ @param This Protocol instance pointer.\r
+ @param Controller Handle of device to stop driver on.\r
+ @param NumberOfChildren Number of Handles in ChildHandleBuffer. If number of\r
+ children is zero stop the entire bus driver.\r
+ @param ChildHandleBuffer List of Child Handles to Stop.\r
+\r
+ @retval EFI_SUCCESS This driver is removed ControllerHandle.\r
+ @retval other This driver was not removed from this device.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PciBusDriverBindingStop (\r
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
+ IN EFI_HANDLE Controller,\r
+ IN UINTN NumberOfChildren,\r
+ IN EFI_HANDLE *ChildHandleBuffer\r
+ );\r
+\r
+#endif\r
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