Replace hard-coded machine code with equivalent assembly source code.
Changes tested by checking for machine code equivalence by disassembling
the original and changed code.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Chris Ruffin <chris.ruffin@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
;------------------------------------------------------------------------------ ;\r
;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r
; This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution. The full text of the license may be found at\r
; This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution. The full text of the license may be found at\r
global ASM_PFX(gStmXdSupported)\r
extern ASM_PFX(gStmSmiHandlerIdtr)\r
\r
global ASM_PFX(gStmXdSupported)\r
extern ASM_PFX(gStmSmiHandlerIdtr)\r
\r
+ASM_PFX(gStmSmiCr3) EQU StmSmiCr3Patch - 4\r
+ASM_PFX(gStmSmiStack) EQU StmSmiStackPatch - 4\r
+ASM_PFX(gStmSmbase) EQU StmSmbasePatch - 4\r
+ASM_PFX(gStmXdSupported) EQU StmXdSupportedPatch - 1\r
+\r
SECTION .text\r
\r
BITS 16\r
SECTION .text\r
\r
BITS 16\r
o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]\r
mov ax, PROTECT_MODE_CS\r
mov [cs:bx-0x2],ax\r
o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]\r
mov ax, PROTECT_MODE_CS\r
mov [cs:bx-0x2],ax\r
- DB 0x66, 0xbf ; mov edi, SMBASE\r
-ASM_PFX(gStmSmbase): DD 0\r
+o32 mov edi, strict dword 0\r
+StmSmbasePatch:\r
lea eax, [edi + (@32bit - _StmSmiEntryPoint) + 0x8000]\r
mov [cs:bx-0x6],eax\r
mov ebx, cr0\r
lea eax, [edi + (@32bit - _StmSmiEntryPoint) + 0x8000]\r
mov [cs:bx-0x6],eax\r
mov ebx, cr0\r
o16 mov fs, ax\r
o16 mov gs, ax\r
o16 mov ss, ax\r
o16 mov fs, ax\r
o16 mov gs, ax\r
o16 mov ss, ax\r
- DB 0xbc ; mov esp, imm32\r
-ASM_PFX(gStmSmiStack): DD 0\r
+ mov esp, strict dword 0\r
+StmSmiStackPatch:\r
mov eax, ASM_PFX(gStmSmiHandlerIdtr)\r
lidt [eax]\r
jmp ProtFlatMode\r
\r
ProtFlatMode:\r
mov eax, ASM_PFX(gStmSmiHandlerIdtr)\r
lidt [eax]\r
jmp ProtFlatMode\r
\r
ProtFlatMode:\r
- DB 0xb8 ; mov eax, imm32\r
-ASM_PFX(gStmSmiCr3): DD 0\r
+ mov eax, strict dword 0\r
+StmSmiCr3Patch:\r
mov cr3, eax\r
;\r
; Need to test for CR4 specific bit support\r
mov cr3, eax\r
;\r
; Need to test for CR4 specific bit support\r
.6:\r
\r
; enable NXE if supported\r
.6:\r
\r
; enable NXE if supported\r
- DB 0b0h ; mov al, imm8\r
-ASM_PFX(gStmXdSupported): DB 1\r
+ mov al, strict byte 1\r
+StmXdSupportedPatch:\r
cmp al, 0\r
jz @SkipXd\r
;\r
cmp al, 0\r
jz @SkipXd\r
;\r
\r
ASM_PFX(gcStmSmiHandlerSize) : DW $ - _StmSmiEntryPoint\r
ASM_PFX(gcStmSmiHandlerOffset) : DW _StmSmiHandler - _StmSmiEntryPoint\r
\r
ASM_PFX(gcStmSmiHandlerSize) : DW $ - _StmSmiEntryPoint\r
ASM_PFX(gcStmSmiHandlerOffset) : DW _StmSmiHandler - _StmSmiEntryPoint\r
;------------------------------------------------------------------------------ ;\r
;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>\r
; This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution. The full text of the license may be found at\r
; This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution. The full text of the license may be found at\r
\r
mov ebx, eax\r
mov eax, 4\r
\r
mov ebx, eax\r
mov eax, 4\r
- DB 0x0f, 0x01, 0x0c1 ; VMCALL\r
jmp $\r
\r
global ASM_PFX(OnStmSetup)\r
jmp $\r
\r
global ASM_PFX(OnStmSetup)\r
;------------------------------------------------------------------------------ ;\r
;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r
; This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution. The full text of the license may be found at\r
; This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution. The full text of the license may be found at\r
global ASM_PFX(gcStmSmiHandlerSize)\r
global ASM_PFX(gcStmSmiHandlerOffset)\r
\r
global ASM_PFX(gcStmSmiHandlerSize)\r
global ASM_PFX(gcStmSmiHandlerOffset)\r
\r
+ASM_PFX(gStmSmbase) EQU StmSmbasePatch - 4\r
+ASM_PFX(gStmSmiStack) EQU StmSmiStackPatch - 4\r
+ASM_PFX(gStmSmiCr3) EQU StmSmiCr3Patch - 4\r
+ASM_PFX(gStmXdSupported) EQU StmXdSupportedPatch - 1\r
+\r
DEFAULT REL\r
SECTION .text\r
\r
DEFAULT REL\r
SECTION .text\r
\r
o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]\r
mov ax, PROTECT_MODE_CS\r
mov [cs:bx-0x2],ax\r
o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]\r
mov ax, PROTECT_MODE_CS\r
mov [cs:bx-0x2],ax\r
- DB 0x66, 0xbf ; mov edi, SMBASE\r
-ASM_PFX(gStmSmbase): DD 0\r
+o32 mov edi, strict dword 0\r
+StmSmbasePatch:\r
lea eax, [edi + (@ProtectedMode - _StmSmiEntryPoint) + 0x8000]\r
mov [cs:bx-0x6],eax\r
mov ebx, cr0\r
lea eax, [edi + (@ProtectedMode - _StmSmiEntryPoint) + 0x8000]\r
mov [cs:bx-0x6],eax\r
mov ebx, cr0\r
o16 mov fs, ax\r
o16 mov gs, ax\r
o16 mov ss, ax\r
o16 mov fs, ax\r
o16 mov gs, ax\r
o16 mov ss, ax\r
- DB 0xbc ; mov esp, imm32\r
-ASM_PFX(gStmSmiStack): DD 0\r
+ mov esp, strict dword 0\r
+StmSmiStackPatch:\r
jmp ProtFlatMode\r
\r
BITS 64\r
ProtFlatMode:\r
jmp ProtFlatMode\r
\r
BITS 64\r
ProtFlatMode:\r
- DB 0xb8 ; mov eax, offset gStmSmiCr3\r
-ASM_PFX(gStmSmiCr3): DD 0\r
+ mov eax, strict dword 0\r
+StmSmiCr3Patch:\r
mov cr3, rax\r
mov eax, 0x668 ; as cr4.PGE is not set here, refresh cr3\r
mov cr4, rax ; in PreModifyMtrrs() to flush TLB.\r
mov cr3, rax\r
mov eax, 0x668 ; as cr4.PGE is not set here, refresh cr3\r
mov cr4, rax ; in PreModifyMtrrs() to flush TLB.\r
ltr ax\r
\r
; enable NXE if supported\r
ltr ax\r
\r
; enable NXE if supported\r
- DB 0xb0 ; mov al, imm8\r
-ASM_PFX(gStmXdSupported): DB 1\r
+ mov al, strict byte 1\r
+StmXdSupportedPatch:\r
cmp al, 0\r
jz @SkipXd\r
;\r
cmp al, 0\r
jz @SkipXd\r
;\r
; Save FP registers\r
;\r
sub rsp, 0x200\r
; Save FP registers\r
;\r
sub rsp, 0x200\r
- DB 0x48 ; FXSAVE64\r
- fxsave [rsp]\r
;\r
; Restore FP registers\r
;\r
;\r
; Restore FP registers\r
;\r
- DB 0x48 ; FXRSTOR64\r
- fxrstor [rsp]\r
;------------------------------------------------------------------------------ ;\r
;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r
; This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution. The full text of the license may be found at\r
; This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution. The full text of the license may be found at\r
add rsp, 0x28\r
mov ebx, eax\r
mov eax, 4\r
add rsp, 0x28\r
mov ebx, eax\r
mov eax, 4\r
- DB 0x0f, 0x01, 0x0c1 ; VMCALL\r
jmp $\r
\r
global ASM_PFX(OnStmSetup)\r
jmp $\r
\r
global ASM_PFX(OnStmSetup)\r