https://bugzilla.tianocore.org/show_bug.cgi?id=674
Add CPUID check to see if the CPU supports the Machine
Check Architecture before accessing the Machine Check
Architecture related MSRs.
Cc: Eric Dong <eric.dong@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
UINTN mSemaphoreSize;\r
SPIN_LOCK *mPFLock = NULL;\r
SMM_CPU_SYNC_MODE mCpuSmmSyncMode;\r
UINTN mSemaphoreSize;\r
SPIN_LOCK *mPFLock = NULL;\r
SMM_CPU_SYNC_MODE mCpuSmmSyncMode;\r
+BOOLEAN mMachineCheckSupported = FALSE;\r
\r
/**\r
Performs an atomic compare exchange operation to get semaphore.\r
\r
/**\r
Performs an atomic compare exchange operation to get semaphore.\r
\r
ASSERT (*mSmmMpSyncData->Counter <= mNumberOfCpus);\r
\r
\r
ASSERT (*mSmmMpSyncData->Counter <= mNumberOfCpus);\r
\r
- LmceEn = IsLmceOsEnabled ();\r
- LmceSignal = IsLmceSignaled();\r
+ LmceEn = FALSE;\r
+ LmceSignal = FALSE;\r
+ if (mMachineCheckSupported) {\r
+ LmceEn = IsLmceOsEnabled ();\r
+ LmceSignal = IsLmceSignaled();\r
+ }\r
\r
//\r
// Platform implementor should choose a timeout value appropriately:\r
\r
//\r
// Platform implementor should choose a timeout value appropriately:\r
UINTN Index;\r
UINT8 *GdtTssTables;\r
UINTN GdtTableStepSize;\r
UINTN Index;\r
UINT8 *GdtTssTables;\r
UINTN GdtTableStepSize;\r
+ CPUID_VERSION_INFO_EDX RegEdx;\r
+\r
+ //\r
+ // Determine if this CPU supports machine check\r
+ //\r
+ AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx.Uint32);\r
+ mMachineCheckSupported = (BOOLEAN)(RegEdx.Bits.MCA == 1);\r
\r
//\r
// Allocate memory for all locks and semaphores\r
\r
//\r
// Allocate memory for all locks and semaphores\r