/** @file\r
Page table management support.\r
\r
- Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>\r
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
#include "CpuDxe.h"\r
#include "CpuPageTable.h"\r
\r
-///\r
-/// Paging registers\r
-///\r
-#define CR0_WP BIT16\r
-#define CR0_PG BIT31\r
-#define CR4_PSE BIT4\r
-#define CR4_PAE BIT5\r
-\r
///\r
/// Page Table Entry\r
///\r
UINT32 RegEax;\r
CPUID_EXTENDED_CPU_SIG_EDX RegEdx;\r
MSR_IA32_EFER_REGISTER MsrEfer;\r
+ IA32_CR4 Cr4;\r
+ IA32_CR0 Cr0;\r
\r
//\r
// Don't retrieve current paging context from processor if in SMM mode.\r
} else {\r
mPagingContext.MachineType = IMAGE_FILE_MACHINE_I386;\r
}\r
- if ((AsmReadCr0 () & CR0_PG) != 0) {\r
+\r
+ Cr0.UintN = AsmReadCr0 ();\r
+ Cr4.UintN = AsmReadCr4 ();\r
+\r
+ if (Cr0.Bits.PG != 0) {\r
mPagingContext.ContextData.X64.PageTableBase = (AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64);\r
} else {\r
mPagingContext.ContextData.X64.PageTableBase = 0;\r
}\r
-\r
- if ((AsmReadCr4 () & CR4_PSE) != 0) {\r
+ if (Cr0.Bits.WP != 0) {\r
+ mPagingContext.ContextData.Ia32.Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_WP_ENABLE;\r
+ }\r
+ if (Cr4.Bits.PSE != 0) {\r
mPagingContext.ContextData.Ia32.Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PSE;\r
}\r
- if ((AsmReadCr4 () & CR4_PAE) != 0) {\r
+ if (Cr4.Bits.PAE != 0) {\r
mPagingContext.ContextData.Ia32.Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE;\r
}\r
- if ((AsmReadCr0 () & CR0_WP) != 0) {\r
- mPagingContext.ContextData.Ia32.Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_WP_ENABLE;\r
- }\r
\r
AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);\r
if (RegEax >= CPUID_EXTENDED_CPU_SIG) {\r
VOID\r
)\r
{\r
+ IA32_CR0 Cr0;\r
//\r
// To avoid unforseen consequences, don't touch paging settings in SMM mode\r
// in this driver.\r
//\r
if (!IsInSmm ()) {\r
- return ((AsmReadCr0 () & CR0_WP) != 0);\r
+ Cr0.UintN = AsmReadCr0 ();\r
+ return (BOOLEAN) (Cr0.Bits.WP != 0);\r
}\r
return FALSE;\r
}\r
VOID\r
)\r
{\r
+ IA32_CR0 Cr0;\r
//\r
// To avoid unforseen consequences, don't touch paging settings in SMM mode\r
// in this driver.\r
//\r
if (!IsInSmm ()) {\r
- AsmWriteCr0 (AsmReadCr0 () & ~CR0_WP);\r
+ Cr0.UintN = AsmReadCr0 ();\r
+ Cr0.Bits.WP = 0;\r
+ AsmWriteCr0 (Cr0.UintN);\r
}\r
}\r
\r
VOID\r
)\r
{\r
+ IA32_CR0 Cr0;\r
//\r
// To avoid unforseen consequences, don't touch paging settings in SMM mode\r
// in this driver.\r
//\r
if (!IsInSmm ()) {\r
- AsmWriteCr0 (AsmReadCr0 () | CR0_WP);\r
+ Cr0.UintN = AsmReadCr0 ();\r
+ Cr0.Bits.WP = 1;\r
+ AsmWriteCr0 (Cr0.UintN);\r
}\r
}\r
\r