//\r
#pragma pack(1)\r
\r
+/**\r
+ Macro used to verify the size of a data type at compile time and trigger a\r
+ STATIC_ASSERT() with an error message if the size of the data type does not\r
+ match the expected size.\r
+\r
+ @param TypeName Type name of data type to verify.\r
+ @param ExpectedSize The expected size, in bytes, of the data type specified\r
+ by TypeName.\r
+**/\r
+#define CXL_11_SIZE_ASSERT(TypeName, ExpectedSize) \\r
+ STATIC_ASSERT ( \\r
+ sizeof (TypeName) == ExpectedSize, \\r
+ "Size of " #TypeName \\r
+ " does not meet CXL 1.1 Specification requirements." \\r
+ )\r
+\r
+/**\r
+ Macro used to verify the offset of a field in a data type at compile time and\r
+ trigger a STATIC_ASSERT() with an error message if the offset of the field in\r
+ the data type does not match the expected offset.\r
+\r
+ @param TypeName Type name of data type to verify.\r
+ @param FieldName Field name in the data type specified by TypeName to\r
+ verify.\r
+ @param ExpectedOffset The expected offset, in bytes, of the field specified\r
+ by TypeName and FieldName.\r
+**/\r
+#define CXL_11_OFFSET_ASSERT(TypeName, FieldName, ExpectedOffset) \\r
+ STATIC_ASSERT ( \\r
+ OFFSET_OF (TypeName, FieldName) == ExpectedOffset, \\r
+ "Offset of " #TypeName "." #FieldName \\r
+ " does not meet CXL 1.1 Specification requirements." \\r
+ )\r
+\r
///\r
/// The PCIe DVSEC for Flex Bus Device\r
///@{\r
CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_HIGH DeviceRange2BaseHigh; // offset 48\r
CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_LOW DeviceRange2BaseLow; // offset 52\r
} CXL_1_1_DVSEC_FLEX_BUS_DEVICE;\r
+\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, Header , 0x00);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DesignatedVendorSpecificHeader1, 0x04);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DesignatedVendorSpecificHeader2, 0x08);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceCapability , 0x0A);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceControl , 0x0C);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceStatus , 0x0E);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceControl2 , 0x10);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceStatus2 , 0x12);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceLock , 0x14);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1SizeHigh , 0x18);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1SizeLow , 0x1C);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1BaseHigh , 0x20);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1BaseLow , 0x24);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2SizeHigh , 0x28);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2SizeLow , 0x2C);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2BaseHigh , 0x30);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2BaseLow , 0x34);\r
+CXL_11_SIZE_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE , 0x38);\r
///@}\r
\r
///\r
CXL_1_1_DVSEC_FLEX_BUS_PORT_CONTROL PortControl; // offset 12\r
CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS PortStatus; // offset 14\r
} CXL_1_1_DVSEC_FLEX_BUS_PORT;\r
+\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, Header , 0x00);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, DesignatedVendorSpecificHeader1, 0x04);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, DesignatedVendorSpecificHeader2, 0x08);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, PortCapability , 0x0A);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, PortControl , 0x0C);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, PortStatus , 0x0E);\r
+CXL_11_SIZE_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT , 0x10);\r
///@}\r
\r
///\r
UINT32 HeaderLog[16];\r
} CXL_1_1_RAS_CAPABILITY_STRUCTURE;\r
\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, UncorrectableErrorStatus , 0x00);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, UncorrectableErrorMask , 0x04);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, UncorrectableErrorSeverity , 0x08);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, CorrectableErrorStatus , 0x0C);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, CorrectableErrorMask , 0x10);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, ErrorCapabilitiesAndControl, 0x14);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, HeaderLog , 0x18);\r
+CXL_11_SIZE_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE , 0x58);\r
+\r
typedef union {\r
struct {\r
UINT32 DeviceTrustLevel : 2; // bit 0..1\r
CXL_1_1_SECURITY_POLICY SecurityPolicy;\r
} CXL_1_1_SECURITY_CAPABILITY_STRUCTURE;\r
\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_SECURITY_CAPABILITY_STRUCTURE, SecurityPolicy, 0x0);\r
+CXL_11_SIZE_ASSERT (CXL_1_1_SECURITY_CAPABILITY_STRUCTURE, 0x4);\r
+\r
typedef union {\r
struct {\r
UINT64 CxlLinkVersionSupported : 4; // bit 0..3\r
UINT16 LlRetryBufferConsumed : 8; // bit 5..12\r
UINT16 Reserved : 3; // bit 13..15\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT64 Uint64;\r
} CXL_LINK_LAYER_CONTROL_AND_STATUS;\r
\r
typedef union {\r
UINT32 AckForceThreshold : 8; // bit 0..7\r
UINT32 AckFLushRetimer : 10; // bit 8..17\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT64 Uint64;\r
} CXL_LINK_LAYER_ACK_TIMER_CONTROL;\r
\r
typedef union {\r
UINT32 MdhDisable : 1; // bit 0..0\r
UINT32 Reserved : 31; // bit 1..31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT64 Uint64;\r
} CXL_LINK_LAYER_DEFEATURE;\r
\r
typedef struct {\r
CXL_LINK_LAYER_DEFEATURE LinkLayerDefeature;\r
} CXL_1_1_LINK_CAPABILITY_STRUCTURE;\r
\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerCapability , 0x00);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerControlStatus , 0x08);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerRxCreditControl , 0x10);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerRxCreditReturnStatus, 0x18);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerTxCreditStatus , 0x20);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerAckTimerControl , 0x28);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerDefeature , 0x30);\r
+CXL_11_SIZE_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE , 0x38);\r
+\r
#define CXL_IO_ARBITRATION_CONTROL_OFFSET 0x180\r
typedef union {\r
struct {\r
UINT32 Uint32;\r
} CXL_IO_ARBITRATION_CONTROL;\r
\r
+CXL_11_SIZE_ASSERT (CXL_IO_ARBITRATION_CONTROL, 0x4);\r
+\r
#define CXL_CACHE_MEMORY_ARBITRATION_CONTROL_OFFSET 0x1C0\r
typedef union {\r
struct {\r
} Bits;\r
UINT32 Uint32;\r
} CXL_CACHE_MEMORY_ARBITRATION_CONTROL;\r
+\r
+CXL_11_SIZE_ASSERT (CXL_CACHE_MEMORY_ARBITRATION_CONTROL, 0x4);\r
+\r
///@}\r
\r
/// The CXL.RCRB base register definition\r
} Bits;\r
UINT64 Uint64;\r
} CXL_RCRB_BASE;\r
+\r
+CXL_11_SIZE_ASSERT (CXL_RCRB_BASE, 0x8);\r
+\r
///@}\r
\r
#pragma pack()\r