In various archs, Processor memory address may not be same with Pci memory address...

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9259 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.c b/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.c
index 4bac309cc1fae1d039f1ac4d321342cd21da2f2e..c57b0c80cada19efeab51c8e36037739ce7a944d 100644 (file)
--- a/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.c
+++ b/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.c
@@ -707,7 +707,9 @@ Uhci2ControlTransfer (
           Uhc,\r
           DeviceAddress,\r
           PktId,\r
+          (UINT8*)Request,\r
           RequestPhy,\r
+          (UINT8*)Data,\r
           DataPhy,\r
           TransferDataLength,\r
           (UINT8) MaximumPacketLength,\r
@@ -724,7 +726,7 @@ Uhci2ControlTransfer (
   // the TD to corrosponding queue head, then check\r
   // the execution result\r
   //\r
-  UhciLinkTdToQh (Uhc->CtrlQh, TDs);\r
+  UhciLinkTdToQh (Uhc, Uhc->CtrlQh, TDs);\r
   Status = UhciExecuteTransfer (Uhc, Uhc->CtrlQh, TDs, TimeOut, IsSlowDevice, &QhResult);\r
   UhciUnlinkTdFromQh (Uhc->CtrlQh, TDs);\r
 \r
@@ -858,6 +860,7 @@ Uhci2BulkTransfer (
              DeviceAddress,\r
              EndPointAddress,\r
              PktId,\r
+             (UINT8 *)*Data,\r
              DataPhy,\r
              *DataLength,\r
              DataToggle,\r
@@ -878,7 +881,7 @@ Uhci2BulkTransfer (
   //\r
   BulkQh = Uhc->BulkQh;\r
 \r
-  UhciLinkTdToQh (BulkQh, TDs);\r
+  UhciLinkTdToQh (Uhc, BulkQh, TDs);\r
   Status = UhciExecuteTransfer (Uhc, BulkQh, TDs, TimeOut, FALSE, &QhResult);\r
   UhciUnlinkTdFromQh (BulkQh, TDs);\r
 \r
@@ -1036,6 +1039,7 @@ Uhci2AsyncInterruptTransfer (
              DeviceAddress,\r
              EndPointAddress,\r
              PktId,\r
+             DataPtr,\r
              DataPhy,\r
              DataLength,\r
              DataToggle,\r
@@ -1048,7 +1052,7 @@ Uhci2AsyncInterruptTransfer (
     goto DESTORY_QH;\r
   }\r
 \r
-  UhciLinkTdToQh (Qh, IntTds);\r
+  UhciLinkTdToQh (Uhc, Qh, IntTds);\r
 \r
   //\r
   // Save QH-TD structures to async Interrupt transfer list,\r
@@ -1073,7 +1077,7 @@ Uhci2AsyncInterruptTransfer (
     goto DESTORY_QH;\r
   }\r
 \r
-  UhciLinkQhToFrameList (Uhc->FrameBase, Qh);\r
+  UhciLinkQhToFrameList (Uhc, Qh);\r
 \r
   gBS->RestoreTPL (OldTpl);\r
   return EFI_SUCCESS;\r
@@ -1209,6 +1213,7 @@ Uhci2SyncInterruptTransfer (
           DeviceAddress,\r
           EndPointAddress,\r
           PktId,\r
+          (UINT8 *)Data,\r
           DataPhy,\r
           *DataLength,\r
           DataToggle,\r
@@ -1224,7 +1229,7 @@ Uhci2SyncInterruptTransfer (
   }\r
 \r
 \r
-  UhciLinkTdToQh (Uhc->SyncIntQh, TDs);\r
+  UhciLinkTdToQh (Uhc, Uhc->SyncIntQh, TDs);\r
 \r
   Status = UhciExecuteTransfer (Uhc, Uhc->SyncIntQh, TDs, TimeOut, IsSlowDevice, &QhResult);\r
 \r

diff --git a/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.h b/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.h
index 3ebafb00ed4d4e3d2ddeb56c8ff90717eade7b36..eb61554e0e86c3612c6893458d809d1423703c20 100644 (file)
--- a/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.h
+++ b/MdeModulePkg/Bus/Pci/UhciDxe/Uhci.h
@@ -117,6 +117,7 @@ struct _USB_HC_DEV {
   // Schedule data structures\r
   //\r
   UINT32                    *FrameBase;\r
+  UINT32                    *FrameBasePciMemAddr;\r
   UHCI_QH_SW                *SyncIntQh;\r
   UHCI_QH_SW                *CtrlQh;\r
   UHCI_QH_SW                *BulkQh;\r

diff --git a/MdeModulePkg/Bus/Pci/UhciDxe/UhciQueue.c b/MdeModulePkg/Bus/Pci/UhciDxe/UhciQueue.c
index 3bf802eecfe00f9bc07e87e086e460a203babaeb..a816956bbedf6fe7cd7ec91d3806777bc9ce6dd7 100644 (file)
--- a/MdeModulePkg/Bus/Pci/UhciDxe/UhciQueue.c
+++ b/MdeModulePkg/Bus/Pci/UhciDxe/UhciQueue.c
@@ -152,19 +152,36 @@ EXIT:
 /**\r
   Link the TD To QH.\r
 \r
+  @param  Uhc         The UHCI device.\r
   @param  Qh          The queue head for the TD to link to.\r
   @param  Td          The TD to link.\r
 \r
 **/\r
 VOID\r
 UhciLinkTdToQh (\r
+  IN USB_HC_DEV           *Uhc,\r
   IN UHCI_QH_SW           *Qh,\r
   IN UHCI_TD_SW           *Td\r
   )\r
 {\r
-  ASSERT ((Qh != NULL) && (Td != NULL));\r
+  EFI_STATUS            Status;\r
+  UINTN                 Len;\r
+  EFI_PHYSICAL_ADDRESS  PhyAddr;\r
+  VOID*                 Map;\r
+\r
+  Len    = sizeof (UHCI_TD_HW);\r
+  Status = Uhc->PciIo->Map (\r
+                         Uhc->PciIo,\r
+                         EfiPciIoOperationBusMasterRead,\r
+                         Td,\r
+                         &Len,\r
+                         &PhyAddr,\r
+                         &Map\r
+                         );\r
+\r
+  ASSERT (!EFI_ERROR (Status) && (Qh != NULL) && (Td != NULL));\r
 \r
-  Qh->QhHw.VerticalLink = QH_VLINK (Td, FALSE);\r
+  Qh->QhHw.VerticalLink = QH_VLINK (PhyAddr, FALSE);\r
   Qh->TDs               = (VOID *) Td;\r
 }\r
 \r
@@ -192,19 +209,36 @@ UhciUnlinkTdFromQh (
 /**\r
   Append a new TD To the previous TD.\r
 \r
+  @param  Uhc         The UHCI device.\r
   @param  PrevTd      Previous UHCI_TD_SW to be linked to.\r
   @param  ThisTd      TD to link.\r
 \r
 **/\r
 VOID\r
 UhciAppendTd (\r
+  IN USB_HC_DEV     *Uhc,\r
   IN UHCI_TD_SW     *PrevTd,\r
   IN UHCI_TD_SW     *ThisTd\r
   )\r
 {\r
-  ASSERT ((PrevTd != NULL) && (ThisTd != NULL));\r
+  EFI_STATUS            Status;\r
+  UINTN                 Len;\r
+  EFI_PHYSICAL_ADDRESS  PhyAddr;\r
+  VOID*                 Map;\r
 \r
-  PrevTd->TdHw.NextLink = TD_LINK (ThisTd, TRUE, FALSE);\r
+  Len    = sizeof (UHCI_TD_HW);\r
+  Status = Uhc->PciIo->Map (\r
+                         Uhc->PciIo,\r
+                         EfiPciIoOperationBusMasterRead,\r
+                         ThisTd,\r
+                         &Len,\r
+                         &PhyAddr,\r
+                         &Map\r
+                         );\r
+\r
+  ASSERT (!EFI_ERROR (Status) && (PrevTd != NULL) && (ThisTd != NULL));\r
+\r
+  PrevTd->TdHw.NextLink = TD_LINK (PhyAddr, TRUE, FALSE);\r
   PrevTd->NextTd        = (VOID *) ThisTd;\r
 }\r
 \r
@@ -290,7 +324,6 @@ UhciCreateTd (
     return NULL;\r
   }\r
 \r
-  Td->TdHw.NextLink = TD_LINK (NULL, FALSE, TRUE);\r
   Td->NextTd        = NULL;\r
   Td->Data          = NULL;\r
   Td->DataLen       = 0;\r
@@ -304,7 +337,8 @@ UhciCreateTd (
 \r
   @param  Uhc         The UHCI device.\r
   @param  DevAddr     Device address.\r
-  @param  Request     Device request.\r
+  @param  Request     A pointer to cpu memory address of Device request.\r
+  @param  RequestPhy  A pointer to pci memory address of Device request.\r
   @param  IsLow       Full speed or low speed.\r
 \r
   @return The created setup Td Pointer.\r
@@ -315,6 +349,7 @@ UhciCreateSetupTd (
   IN  USB_HC_DEV          *Uhc,\r
   IN  UINT8               DevAddr,\r
   IN  UINT8               *Request,\r
+  IN  UINT8               *RequestPhy,\r
   IN  BOOLEAN             IsLow\r
   )\r
 {\r
@@ -338,7 +373,7 @@ UhciCreateSetupTd (
   Td->TdHw.DeviceAddr   = DevAddr & 0x7F;\r
   Td->TdHw.MaxPacketLen = (UINT32) (sizeof (EFI_USB_DEVICE_REQUEST) - 1);\r
   Td->TdHw.PidCode      = SETUP_PACKET_ID;\r
-  Td->TdHw.DataBuffer   = (UINT32) (UINTN) Request;\r
+  Td->TdHw.DataBuffer   = (UINT32) (UINTN) RequestPhy;\r
 \r
   Td->Data              = Request;\r
   Td->DataLen           = sizeof (EFI_USB_DEVICE_REQUEST);\r
@@ -353,7 +388,8 @@ UhciCreateSetupTd (
   @param  Uhc         The UHCI device.\r
   @param  DevAddr     Device address.\r
   @param  Endpoint    Endpoint number.\r
-  @param  DataPtr     Data buffer.\r
+  @param  DataPtr     A pointer to cpu memory address of Data buffer.\r
+  @param  DataPhyPtr  A pointer to pci memory address of Data buffer.\r
   @param  Len         Data length.\r
   @param  PktId       Packet ID.\r
   @param  Toggle      Data toggle value.\r
@@ -368,6 +404,7 @@ UhciCreateDataTd (
   IN  UINT8               DevAddr,\r
   IN  UINT8               Endpoint,\r
   IN  UINT8               *DataPtr,\r
+  IN  UINT8               *DataPhyPtr,\r
   IN  UINTN               Len,\r
   IN  UINT8               PktId,\r
   IN  UINT8               Toggle,\r
@@ -399,7 +436,7 @@ UhciCreateDataTd (
   Td->TdHw.DeviceAddr   = DevAddr & 0x7F;\r
   Td->TdHw.MaxPacketLen = (UINT32) (Len - 1);\r
   Td->TdHw.PidCode      = (UINT8) PktId;\r
-  Td->TdHw.DataBuffer   = (UINT32) (UINTN) DataPtr;\r
+  Td->TdHw.DataBuffer   = (UINT32) (UINTN) DataPhyPtr;\r
 \r
   Td->Data              = DataPtr;\r
   Td->DataLen           = (UINT16) Len;\r
@@ -462,8 +499,10 @@ UhciCreateStatusTd (
   @param  Uhc         The UHCI device.\r
   @param  DeviceAddr  The device address.\r
   @param  DataPktId   Packet Identification of Data Tds.\r
-  @param  Request     A pointer to request structure buffer to transfer.\r
-  @param  Data        A pointer to user data buffer to transfer.\r
+  @param  Request     A pointer to cpu memory address of request structure buffer to transfer.\r
+  @param  RequestPhy  A pointer to pci memory address of request structure buffer to transfer.\r
+  @param  Data        A pointer to cpu memory address of user data buffer to transfer.\r
+  @param  DataPhy     A pointer to pci memory address of user data buffer to transfer.\r
   @param  DataLen     Length of user data to transfer.\r
   @param  MaxPacket   Maximum packet size for control transfer.\r
   @param  IsLow       Full speed or low speed.\r
@@ -477,7 +516,9 @@ UhciCreateCtrlTds (
   IN UINT8                DeviceAddr,\r
   IN UINT8                DataPktId,\r
   IN UINT8                *Request,\r
+  IN UINT8                *RequestPhy,\r
   IN UINT8                *Data,\r
+  IN UINT8                *DataPhy,\r
   IN UINTN                DataLen,\r
   IN UINT8                MaxPacket,\r
   IN BOOLEAN              IsLow\r
@@ -502,7 +543,7 @@ UhciCreateCtrlTds (
   //\r
   // Create setup packets for the transfer\r
   //\r
-  SetupTd = UhciCreateSetupTd (Uhc, DeviceAddr, Request, IsLow);\r
+  SetupTd = UhciCreateSetupTd (Uhc, DeviceAddr, Request, RequestPhy, IsLow);\r
 \r
   if (SetupTd == NULL) {\r
     return NULL;\r
@@ -523,7 +564,8 @@ UhciCreateCtrlTds (
                Uhc,\r
                DeviceAddr,\r
                0,\r
-               Data,\r
+               Data,  //cpu memory address\r
+               DataPhy, //Pci memory address\r
                ThisTdLen,\r
                DataPktId,\r
                DataToggle,\r
@@ -538,12 +580,13 @@ UhciCreateCtrlTds (
       FirstDataTd         = DataTd;\r
       FirstDataTd->NextTd = NULL;\r
     } else {\r
-      UhciAppendTd (PrevDataTd, DataTd);\r
+      UhciAppendTd (Uhc, PrevDataTd, DataTd);\r
     }\r
 \r
     DataToggle ^= 1;\r
     PrevDataTd = DataTd;\r
     Data += ThisTdLen;\r
+    DataPhy += ThisTdLen;\r
     DataLen -= ThisTdLen;\r
   }\r
 \r
@@ -566,10 +609,10 @@ UhciCreateCtrlTds (
   // Link setup Td -> data Tds -> status Td together\r
   //\r
   if (FirstDataTd != NULL) {\r
-    UhciAppendTd (SetupTd, FirstDataTd);\r
-    UhciAppendTd (PrevDataTd, StatusTd);\r
+    UhciAppendTd (Uhc, SetupTd, FirstDataTd);\r
+    UhciAppendTd (Uhc, PrevDataTd, StatusTd);\r
   } else {\r
-    UhciAppendTd (SetupTd, StatusTd);\r
+    UhciAppendTd (Uhc, SetupTd, StatusTd);\r
   }\r
 \r
   return SetupTd;\r
@@ -594,7 +637,8 @@ FREE_TD:
   @param  DevAddr     Address of Device.\r
   @param  EndPoint    Endpoint Number.\r
   @param  PktId       Packet Identification of Data Tds.\r
-  @param  Data        A pointer to user data buffer to transfer.\r
+  @param  Data        A pointer to cpu memory address of user data buffer to transfer.\r
+  @param  DataPhy     A pointer to pci memory address of user data buffer to transfer.\r
   @param  DataLen     Length of user data to transfer.\r
   @param  DataToggle  Data Toggle Pointer.\r
   @param  MaxPacket   Maximum packet size for Bulk/Interrupt transfer.\r
@@ -610,6 +654,7 @@ UhciCreateBulkOrIntTds (
   IN UINT8                EndPoint,\r
   IN UINT8                PktId,\r
   IN UINT8                *Data,\r
+  IN UINT8                *DataPhy,\r
   IN UINTN                DataLen,\r
   IN OUT UINT8            *DataToggle,\r
   IN UINT8                MaxPacket,\r
@@ -643,6 +688,7 @@ UhciCreateBulkOrIntTds (
                DevAddr,\r
                EndPoint,\r
                Data,\r
+               DataPhy,\r
                ThisTdLen,\r
                PktId,\r
                *DataToggle,\r
@@ -661,12 +707,13 @@ UhciCreateBulkOrIntTds (
       FirstDataTd         = DataTd;\r
       FirstDataTd->NextTd = NULL;\r
     } else {\r
-      UhciAppendTd (PrevDataTd, DataTd);\r
+      UhciAppendTd (Uhc, PrevDataTd, DataTd);\r
     }\r
 \r
     *DataToggle ^= 1;\r
     PrevDataTd   = DataTd;\r
     Data        += ThisTdLen;\r
+    DataPhy     += ThisTdLen;\r
     DataLen     -= ThisTdLen;\r
   }\r
 \r

diff --git a/MdeModulePkg/Bus/Pci/UhciDxe/UhciQueue.h b/MdeModulePkg/Bus/Pci/UhciDxe/UhciQueue.h
index 70e7f377ded6b699d57147c1bf5ecc9136f49314..d89e2713ad4c661cca4bbaabd1f728eba29cbf77 100644 (file)
--- a/MdeModulePkg/Bus/Pci/UhciDxe/UhciQueue.h
+++ b/MdeModulePkg/Bus/Pci/UhciDxe/UhciQueue.h
@@ -97,14 +97,14 @@ struct _UHCI_TD_SW {
 /**\r
   Link the TD To QH.\r
 \r
+  @param  Uhc         The UHCI device.\r
   @param  Qh          The queue head for the TD to link to.\r
   @param  Td          The TD to link.\r
 \r
-  @return None.\r
-\r
 **/\r
 VOID\r
 UhciLinkTdToQh (\r
+  IN USB_HC_DEV           *Uhc,\r
   IN UHCI_QH_SW           *Qh,\r
   IN UHCI_TD_SW           *Td\r
   );\r
@@ -212,8 +212,10 @@ UhciCreateQh (
   @param  Uhc         The UHCI device.\r
   @param  DeviceAddr  The device address.\r
   @param  DataPktId   Packet Identification of Data Tds.\r
-  @param  Request     A pointer to request structure buffer to transfer.\r
-  @param  Data        A pointer to user data buffer to transfer.\r
+  @param  Request     A pointer to cpu memory address of request structure buffer to transfer.\r
+  @param  RequestPhy  A pointer to pci memory address of request structure buffer to transfer.\r
+  @param  Data        A pointer to cpu memory address of user data buffer to transfer.\r
+  @param  DataPhy     A pointer to pci memory address of user data buffer to transfer.\r
   @param  DataLen     Length of user data to transfer.\r
   @param  MaxPacket   Maximum packet size for control transfer.\r
   @param  IsLow       Full speed or low speed.\r
@@ -227,7 +229,9 @@ UhciCreateCtrlTds (
   IN UINT8                DeviceAddr,\r
   IN UINT8                DataPktId,\r
   IN UINT8                *Request,\r
+  IN UINT8                *RequestPhy,\r
   IN UINT8                *Data,\r
+  IN UINT8                *DataPhy,\r
   IN UINTN                DataLen,\r
   IN UINT8                MaxPacket,\r
   IN BOOLEAN              IsLow\r
@@ -241,7 +245,8 @@ UhciCreateCtrlTds (
   @param  DevAddr     Address of Device.\r
   @param  EndPoint    Endpoint Number.\r
   @param  PktId       Packet Identification of Data Tds.\r
-  @param  Data        A pointer to user data buffer to transfer.\r
+  @param  Data        A pointer to cpu memory address of user data buffer to transfer.\r
+  @param  DataPhy     A pointer to pci memory address of user data buffer to transfer.\r
   @param  DataLen     Length of user data to transfer.\r
   @param  DataToggle  Data Toggle Pointer.\r
   @param  MaxPacket   Maximum packet size for Bulk/Interrupt transfer.\r
@@ -257,6 +262,7 @@ UhciCreateBulkOrIntTds (
   IN UINT8                EndPoint,\r
   IN UINT8                PktId,\r
   IN UINT8                *Data,\r
+  IN UINT8                *DataPhy,\r
   IN UINTN                DataLen,\r
   IN OUT UINT8            *DataToggle,\r
   IN UINT8                MaxPacket,\r

diff --git a/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.c b/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.c
index 671a54205a5e28c6bd51400362179542909e1ff9..f56fa2b4b16fea9163c7656a2686507c4bd44735 100644 (file)
--- a/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.c
+++ b/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.c
@@ -38,6 +38,8 @@ UhciInitFrameList (
   UINTN                 Pages;\r
   UINTN                 Bytes;\r
   UINTN                 Index;\r
+  UINTN                 Len;\r
+  EFI_PHYSICAL_ADDRESS  PhyAddr;\r
 \r
   //\r
   // The Frame List is a common buffer that will be\r
@@ -75,8 +77,9 @@ UhciInitFrameList (
     goto ON_ERROR;\r
   }\r
 \r
-  Uhc->FrameBase    = (UINT32 *) (UINTN) MappedAddr;\r
-  Uhc->FrameMapping = Mapping;\r
+  Uhc->FrameBase           = (UINT32 *) (UINTN) Buffer; // Cpu memory address\r
+  Uhc->FrameBasePciMemAddr = (UINT32 *) (UINTN) MappedAddr; // Pci memory address\r
+  Uhc->FrameMapping        = Mapping;\r
 \r
   //\r
   // Allocate the QH used by sync interrupt/control/bulk transfer.\r
@@ -101,10 +104,31 @@ UhciInitFrameList (
   // Each frame entry is linked to this sequence of QH. These QH\r
   // will remain on the schedul, never got removed\r
   //\r
-  Uhc->SyncIntQh->QhHw.HorizonLink  = QH_HLINK (Uhc->CtrlQh, FALSE);\r
+  Len    = sizeof (UHCI_QH_HW);\r
+  Status = Uhc->PciIo->Map (\r
+                         Uhc->PciIo,\r
+                         EfiPciIoOperationBusMasterRead,\r
+                         Uhc->CtrlQh,\r
+                         &Len,\r
+                         &PhyAddr,\r
+                         &Mapping\r
+                         );\r
+  ASSERT (!EFI_ERROR (Status));\r
+\r
+  Uhc->SyncIntQh->QhHw.HorizonLink  = QH_HLINK (PhyAddr, FALSE);\r
   Uhc->SyncIntQh->NextQh            = Uhc->CtrlQh;\r
 \r
-  Uhc->CtrlQh->QhHw.HorizonLink     = QH_HLINK (Uhc->BulkQh, FALSE);\r
+  Status = Uhc->PciIo->Map (\r
+                         Uhc->PciIo,\r
+                         EfiPciIoOperationBusMasterRead,\r
+                         Uhc->BulkQh,\r
+                         &Len,\r
+                         &PhyAddr,\r
+                         &Mapping\r
+                         );\r
+  ASSERT (!EFI_ERROR (Status));\r
+\r
+  Uhc->CtrlQh->QhHw.HorizonLink     = QH_HLINK (PhyAddr, FALSE);\r
   Uhc->CtrlQh->NextQh               = Uhc->BulkQh;\r
 \r
   //\r
@@ -112,19 +136,31 @@ UhciInitFrameList (
   // in supporting the full speed bandwidth reclamation in the previous\r
   // mentioned form. Most new platforms don't suffer it.\r
   //\r
-  Uhc->BulkQh->QhHw.HorizonLink     = QH_HLINK (Uhc->BulkQh, FALSE);\r
+  Uhc->BulkQh->QhHw.HorizonLink     = QH_HLINK (PhyAddr, FALSE);\r
 \r
   Uhc->BulkQh->NextQh               = NULL;\r
 \r
+  Len    = sizeof (UHCI_QH_HW);\r
+  Status = Uhc->PciIo->Map (\r
+                         Uhc->PciIo,\r
+                         EfiPciIoOperationBusMasterRead,\r
+                         Uhc->SyncIntQh,\r
+                         &Len,\r
+                         &PhyAddr,\r
+                         &Mapping\r
+                         );\r
+  ASSERT (!EFI_ERROR (Status));\r
+\r
   for (Index = 0; Index < UHCI_FRAME_NUM; Index++) {\r
     Uhc->FrameBase[Index] = QH_HLINK (Uhc->SyncIntQh, FALSE);\r
+    Uhc->FrameBasePciMemAddr[Index] = QH_HLINK (PhyAddr, FALSE);\r
   }\r
 \r
   //\r
   // Tell the Host Controller where the Frame List lies,\r
   // by set the Frame List Base Address Register.\r
   //\r
-  UhciSetFrameListBaseAddr (Uhc->PciIo, (VOID *) (Uhc->FrameBase));\r
+  UhciSetFrameListBaseAddr (Uhc->PciIo, (VOID *) (Uhc->FrameBasePciMemAddr));\r
   return EFI_SUCCESS;\r
 \r
 ON_ERROR:\r
@@ -181,10 +217,11 @@ UhciDestoryFrameList (
     UsbHcFreeMem (Uhc->MemPool, Uhc->BulkQh, sizeof (UHCI_QH_SW));\r
   }\r
 \r
-  Uhc->FrameBase    = NULL;\r
-  Uhc->SyncIntQh    = NULL;\r
-  Uhc->CtrlQh       = NULL;\r
-  Uhc->BulkQh       = NULL;\r
+  Uhc->FrameBase           = NULL;\r
+  Uhc->FrameBasePciMemAddr = NULL;\r
+  Uhc->SyncIntQh           = NULL;\r
+  Uhc->CtrlQh              = NULL;\r
+  Uhc->BulkQh              = NULL;\r
 }\r
 \r
 \r
@@ -224,29 +261,45 @@ UhciConvertPollRate (
   Link a queue head (for asynchronous interrupt transfer) to\r
   the frame list.\r
 \r
-  @param  FrameBase              The base of the frame list.\r
+  @param  Uhc                    The UHCI device.\r
   @param  Qh                     The queue head to link into.\r
 \r
 **/\r
 VOID\r
 UhciLinkQhToFrameList (\r
-  UINT32                  *FrameBase,\r
+  USB_HC_DEV              *Uhc,\r
   UHCI_QH_SW              *Qh\r
   )\r
 {\r
   UINTN                   Index;\r
   UHCI_QH_SW              *Prev;\r
   UHCI_QH_SW              *Next;\r
+  UINTN                   Len;\r
+  EFI_PHYSICAL_ADDRESS    PhyAddr;\r
+  EFI_PHYSICAL_ADDRESS    QhPciAddr;\r
+  VOID*                   Map;\r
+  EFI_STATUS              Status;\r
+\r
+  ASSERT ((Uhc->FrameBase != NULL) && (Qh != NULL));\r
 \r
-  ASSERT ((FrameBase != NULL) && (Qh != NULL));\r
+  Len    = sizeof (UHCI_QH_HW);\r
+  Status = Uhc->PciIo->Map (\r
+                            Uhc->PciIo,\r
+                            EfiPciIoOperationBusMasterRead,\r
+                            Qh,\r
+                            &Len,\r
+                            &QhPciAddr,\r
+                            &Map\r
+                            );\r
+  ASSERT (!EFI_ERROR (Status));\r
 \r
   for (Index = 0; Index < UHCI_FRAME_NUM; Index += Qh->Interval) {\r
     //\r
     // First QH can't be NULL because we always keep static queue\r
     // heads on the frame list\r
     //\r
-    ASSERT (!LINK_TERMINATED (FrameBase[Index]));\r
-    Next  = UHCI_ADDR (FrameBase[Index]);\r
+    ASSERT (!LINK_TERMINATED (Uhc->FrameBase[Index]));\r
+    Next  = UHCI_ADDR (Uhc->FrameBase[Index]);\r
     Prev  = NULL;\r
 \r
     //\r
@@ -266,10 +319,9 @@ UhciLinkQhToFrameList (
     while (Next->Interval > Qh->Interval) {\r
       Prev  = Next;\r
       Next  = Next->NextQh;\r
+      ASSERT (Next != NULL);\r
     }\r
 \r
-    ASSERT (Next != NULL);\r
-\r
     //\r
     // The entry may have been linked into the frame by early insertation.\r
     // For example: if insert a Qh with Qh.Interval == 4, and there is a Qh\r
@@ -298,7 +350,8 @@ UhciLinkQhToFrameList (
       Prev->NextQh            = Qh;\r
 \r
       Qh->QhHw.HorizonLink    = Prev->QhHw.HorizonLink;\r
-      Prev->QhHw.HorizonLink  = QH_HLINK (Qh, FALSE);\r
+\r
+      Prev->QhHw.HorizonLink  = QH_HLINK (QhPciAddr, FALSE);\r
       break;\r
     }\r
 \r
@@ -309,14 +362,27 @@ UhciLinkQhToFrameList (
     //\r
     if (Qh->NextQh == NULL) {\r
       Qh->NextQh            = Next;\r
-      Qh->QhHw.HorizonLink  = QH_HLINK (Next, FALSE);\r
+\r
+      Len    = sizeof (UHCI_QH_HW);\r
+      Status = Uhc->PciIo->Map (\r
+                            Uhc->PciIo,\r
+                            EfiPciIoOperationBusMasterRead,\r
+                            Next,\r
+                            &Len,\r
+                            &PhyAddr,\r
+                            &Map\r
+                            );\r
+      ASSERT (!EFI_ERROR (Status));\r
+\r
+      Qh->QhHw.HorizonLink  = QH_HLINK (PhyAddr, FALSE);\r
     }\r
 \r
     if (Prev == NULL) {\r
-      FrameBase[Index]        = QH_HLINK (Qh, FALSE);\r
+      Uhc->FrameBase[Index]           = QH_HLINK (Qh, FALSE);\r
+      Uhc->FrameBasePciMemAddr[Index] = QH_HLINK (QhPciAddr, FALSE);\r
     } else {\r
       Prev->NextQh            = Qh;\r
-      Prev->QhHw.HorizonLink  = QH_HLINK (Qh, FALSE);\r
+      Prev->QhHw.HorizonLink  = QH_HLINK (QhPciAddr, FALSE);\r
     }\r
   }\r
 }\r
@@ -327,29 +393,29 @@ UhciLinkQhToFrameList (
   the precedence node, and pointer there next to QhSw's\r
   next.\r
 \r
-  @param  FrameBase              The base address of the frame list.\r
+  @param  Uhc                    The UHCI device.\r
   @param  Qh                     The queue head to unlink.\r
 \r
 **/\r
 VOID\r
 UhciUnlinkQhFromFrameList (\r
-  UINT32                *FrameBase,\r
-  UHCI_QH_SW            *Qh\r
+  USB_HC_DEV              *Uhc,\r
+  UHCI_QH_SW              *Qh\r
   )\r
 {\r
   UINTN                   Index;\r
   UHCI_QH_SW              *Prev;\r
   UHCI_QH_SW              *This;\r
 \r
-  ASSERT ((FrameBase != NULL) && (Qh != NULL));\r
+  ASSERT ((Uhc->FrameBase != NULL) && (Qh != NULL));\r
 \r
   for (Index = 0; Index < UHCI_FRAME_NUM; Index += Qh->Interval) {\r
     //\r
     // Frame link can't be NULL because we always keep static\r
     // queue heads on the frame list\r
     //\r
-    ASSERT (!LINK_TERMINATED (FrameBase[Index]));\r
-    This  = UHCI_ADDR (FrameBase[Index]);\r
+    ASSERT (!LINK_TERMINATED (Uhc->FrameBase[Index]));\r
+    This  = UHCI_ADDR (Uhc->FrameBase[Index]);\r
     Prev  = NULL;\r
 \r
     //\r
@@ -373,7 +439,8 @@ UhciUnlinkQhFromFrameList (
       //\r
       // Qh is the first entry in the frame\r
       //\r
-      FrameBase[Index]        = Qh->QhHw.HorizonLink;\r
+      Uhc->FrameBase[Index]           = (UINT32)(UINTN)Qh->NextQh;\r
+      Uhc->FrameBasePciMemAddr[Index] = Qh->QhHw.HorizonLink;\r
     } else {\r
       Prev->NextQh            = Qh->NextQh;\r
       Prev->QhHw.HorizonLink  = Qh->QhHw.HorizonLink;\r
@@ -592,6 +659,7 @@ UhciExecuteTransfer (
 /**\r
   Update Async Request, QH and TDs.\r
 \r
+  @param  Uhc                    The UHCI device.\r
   @param  AsyncReq               The UHCI asynchronous transfer to update.\r
   @param  Result                 Transfer reslut.\r
   @param  NextToggle             The toggle of next data.\r
@@ -599,6 +667,7 @@ UhciExecuteTransfer (
 **/\r
 VOID\r
 UhciUpdateAsyncReq (\r
+  IN USB_HC_DEV          *Uhc,\r
   IN UHCI_ASYNC_REQUEST  *AsyncReq,\r
   IN UINT32              Result,\r
   IN UINT32              NextToggle\r
@@ -627,7 +696,7 @@ UhciUpdateAsyncReq (
       Td->TdHw.Status    |= USBTD_ACTIVE;\r
     }\r
 \r
-    UhciLinkTdToQh (Qh, FirstTd);\r
+    UhciLinkTdToQh (Uhc, Qh, FirstTd);\r
     return ;\r
   }\r
 }\r
@@ -759,7 +828,7 @@ UhciUnlinkAsyncReq (
   ASSERT ((Uhc != NULL) && (AsyncReq != NULL));\r
 \r
   RemoveEntryList (&(AsyncReq->Link));\r
-  UhciUnlinkQhFromFrameList (Uhc->FrameBase, AsyncReq->QhSw);\r
+  UhciUnlinkQhFromFrameList (Uhc, AsyncReq->QhSw);\r
 \r
   if (FreeNow) {\r
     UhciFreeAsyncReq (Uhc, AsyncReq);\r
@@ -985,7 +1054,7 @@ UhciMonitorAsyncReqList (
       CopyMem (Data, AsyncReq->FirstTd->Data, QhResult.Complete);\r
     }\r
 \r
-    UhciUpdateAsyncReq (AsyncReq, QhResult.Result, QhResult.NextToggle);\r
+    UhciUpdateAsyncReq (Uhc, AsyncReq, QhResult.Result, QhResult.NextToggle);\r
 \r
     //\r
     // Now, either transfer is SUCCESS or met errors since\r

diff --git a/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.h b/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.h
index 17f0ea2abe3eb416d81b33b88c04b65ded9abb07..b4b7c4c0d6a0ee93ec961653e35907bdc6e991d6 100644 (file)
--- a/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.h
+++ b/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.h
@@ -131,15 +131,13 @@ UhciConvertPollRate (
   Link a queue head (for asynchronous interrupt transfer) to\r
   the frame list.\r
 \r
-  @param  FrameBase              The base of the frame list.\r
+  @param  Uhc                    The UHCI device.\r
   @param  Qh                     The queue head to link into.\r
 \r
-  @return None.\r
-\r
 **/\r
 VOID\r
 UhciLinkQhToFrameList (\r
-  UINT32                  *FrameBase,\r
+  USB_HC_DEV              *Uhc,\r
   UHCI_QH_SW              *Qh\r
   );\r
 \r
@@ -149,16 +147,14 @@ UhciLinkQhToFrameList (
   the precedence node, and pointer there next to QhSw's\r
   next.\r
 \r
-  @param  FrameBase              The base address of the frame list.\r
+  @param  Uhc                    The UHCI device.\r
   @param  Qh                     The queue head to unlink.\r
 \r
-  @return None.\r
-\r
 **/\r
 VOID\r
 UhciUnlinkQhFromFrameList (\r
-  UINT32                *FrameBase,\r
-  UHCI_QH_SW            *Qh\r
+  USB_HC_DEV              *Uhc,\r
+  UHCI_QH_SW              *Qh\r
   );\r
 \r
 \r

diff --git a/MdeModulePkg/Bus/Usb/UsbBusDxe/UsbEnumer.c b/MdeModulePkg/Bus/Usb/UsbBusDxe/UsbEnumer.c
index eba9017e4c78d27862521223c9d5810bc6ad7e1c..c64de3a204a3792e7b267e98ddc0de4538aec136 100644 (file)
--- a/MdeModulePkg/Bus/Usb/UsbBusDxe/UsbEnumer.c
+++ b/MdeModulePkg/Bus/Usb/UsbBusDxe/UsbEnumer.c
@@ -852,8 +852,8 @@ UsbEnumeratePort (
     return EFI_SUCCESS;\r
   }\r
 \r
-  DEBUG (( EFI_D_INFO, "UsbEnumeratePort: port %d state - %x, change - %x\n",\r
-              Port, PortState.PortStatus, PortState.PortChangeStatus));\r
+  DEBUG (( EFI_D_INFO, "UsbEnumeratePort: port %d state - %x, change - %x on %p\n",\r
+              Port, PortState.PortStatus, PortState.PortChangeStatus, HubIf));\r
 \r
   //\r
   // This driver only process two kinds of events now: over current and\r