UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h: Change structure definition.

V3 changes include:
  1. Keep the ReservedX not change if bit info not changed for this field.

V2 changes include:
  1. Use X in ReservedX fields from totally new value if MSR structure definition changed.
     For example, if in current structure, the max reserved variable is Reserved2, in new
     definition, reserved variable is begin with Reserved3.

V1 Changes:
Changes includes:
  1. Update MSR structure definition, change some reserved fields to useful fields:
     1. MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER
     2. MSR_XEON_PHI_SMM_MCA_CAP_REGISTER
  2. For MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER structure, it expand the field range.
     Old definition like below:
       typedef union {
         ///
         /// Individual bit fields
         ///
         struct {
           ///
           /// [Bits 15:0] LVL_2 Base Address (R/W).
           ///
           UINT32  Lvl2Base:16;
           ///
           /// [Bits 18:16] C-state Range (R/W)  Specifies the encoding value of the
           /// maximum C-State code name to be included when IO read to MWAIT
           /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 100b - C4
           /// is the max C-State to include 110b - C6 is the max C-State to include.
           ///
           UINT32  CStateRange:3;
           UINT32  Reserved1:13;
           UINT32  Reserved2:32;
         } Bits;
         ///
         /// All bit fields as a 32-bit value
         ///
         UINT32  Uint32;
         ///
         /// All bit fields as a 64-bit value
         ///
         UINT64  Uint64;
       } MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER;
    This patch make below changes for this data structure, it expand "CStateRange" field width.
      old one:
        UINT32  CStateRange:3;
        UINT32  Reserved1:13;
      new one:
        UINT32  CStateRange:7;
        UINT32  Reserved1:9;

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>

diff --git a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
index da74c2402cf32b94e352bd815edab1b5f77e299f..1e22d98ad8c93889ef2301f4018ad08b474a80b2 100644 (file)
--- a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
@@ -278,7 +278,25 @@ typedef union {
     /// [Bit 15] CFG Lock (R/WO).\r
     ///\r
     UINT32  CFGLock:1;\r
-    UINT32  Reserved3:16;\r
+    UINT32  Reserved5:10;\r
+    ///\r
+    /// [Bit 26] C1 State Auto Demotion Enable (R/W) When set, the processor\r
+    /// will conditionally demote C3/C6/C7 requests to C1 based on uncore\r
+    /// auto-demote information.\r
+    ///\r
+    UINT32  C1StateAutoDemotionEnable:1;\r
+    UINT32  Reserved6:1;\r
+    ///\r
+    /// [Bit 28] C1 State Auto Undemotion Enable (R/W) When set, enables\r
+    /// Undemotion from Demoted C1.\r
+    ///\r
+    UINT32  C1StateAutoUndemotionEnable:1;\r
+    ///\r
+    /// [Bit 29] PKG C-State Auto Demotion Enable (R/W) When set, enables\r
+    /// Package C state demotion.\r
+    ///\r
+    UINT32  PKGC_StateAutoDemotionEnable:1;\r
+    UINT32  Reserved7:2;\r
     UINT32  Reserved4:32;\r
   } Bits;\r
   ///\r
@@ -325,13 +343,12 @@ typedef union {
     ///\r
     UINT32  Lvl2Base:16;\r
     ///\r
-    /// [Bits 18:16] C-state Range (R/W)  Specifies the encoding value of the\r
-    /// maximum C-State code name to be included when IO read to MWAIT\r
-    /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 100b - C4\r
-    /// is the max C-State to include 110b - C6 is the max C-State to include.\r
+    /// [Bits 22:16] C-State Range (R/W) The IO-port block size in which\r
+    /// IO-redirection will be executed (0-127). Should be programmed based on\r
+    /// the number of LVLx registers existing in the chipset.\r
     ///\r
-    UINT32  CStateRange:3;\r
-    UINT32  Reserved1:13;\r
+    UINT32  CStateRange:7;\r
+    UINT32  Reserved3:9;\r
     UINT32  Reserved2:32;\r
   } Bits;\r
   ///\r
@@ -477,8 +494,22 @@ typedef union {
   /// Individual bit fields\r
   ///\r
   struct {\r
-    UINT32  Reserved1:32;\r
-    UINT32  Reserved2:26;\r
+    ///\r
+    /// [Bits 31:0] Bank Support (SMM-RO) One bit per MCA bank. If the bit is\r
+    /// set, that bank supports Enhanced MCA (Default all 0; does not support\r
+    /// EMCA).\r
+    ///\r
+    UINT32  BankSupport:32;\r
+    UINT32  Reserved4:24;\r
+    ///\r
+    /// [Bit 56] Targeted SMI (SMM-RO) Set if targeted SMI is supported.\r
+    ///\r
+    UINT32  TargetedSMI:1;\r
+    ///\r
+    /// [Bit 57] SMM_CPU_SVRSTR (SMM-RO) Set if SMM SRAM save/restore feature\r
+    /// is supported.\r
+    ///\r
+    UINT32  SMM_CPU_SVRSTR:1;\r
     ///\r
     /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r
     /// SMM code access restriction is supported and a host-space interface\r