MdeModulePkg XhciDxe: Set HSEE Bit if SERR# Enable Bit is set

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1167

When the HSEE in the USBCMD bit is a ‘1’ and the HSE bit in the
USBSTS register is a ‘1’, the xHC shall assert out-of-band error
signaling to the host and assert the SERR# pin.
To prevent masking any potential issues with SERR, this patch is
to set USBCMD Host System Error Enable(HSEE) Bit if PCICMD SERR#
Enable Bit is set.

Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Fei1 Wang <fei1.wang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>

diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
index 5f0736a516b6e4f0d23b7ec02ed1dcbdd6b0aefd..89f073e1d83f89037d7f4b35cae4a77eed48ca39 100644 (file)
--- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
@@ -586,6 +586,39 @@ XhcIsSysError (
   return XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HSE);\r
 }\r
 \r
+/**\r
+  Set USBCMD Host System Error Enable(HSEE) Bit if PCICMD SERR# Enable Bit is set.\r
+\r
+  The USBCMD HSEE Bit will be reset to default 0 by USBCMD Host Controller Reset(HCRST).\r
+  This function is to set USBCMD HSEE Bit if PCICMD SERR# Enable Bit is set.\r
+\r
+  @param Xhc            The XHCI Instance.\r
+\r
+**/\r
+VOID\r
+XhcSetHsee (\r
+  IN USB_XHCI_INSTANCE  *Xhc\r
+  )\r
+{\r
+  EFI_STATUS            Status;\r
+  EFI_PCI_IO_PROTOCOL   *PciIo;\r
+  UINT16                XhciCmd;\r
+\r
+  PciIo = Xhc->PciIo;\r
+  Status = PciIo->Pci.Read (\r
+                        PciIo,\r
+                        EfiPciIoWidthUint16,\r
+                        PCI_COMMAND_OFFSET,\r
+                        sizeof (XhciCmd),\r
+                        &XhciCmd\r
+                        );\r
+  if (!EFI_ERROR (Status)) {\r
+    if ((XhciCmd & EFI_PCI_COMMAND_SERR) != 0) {\r
+      XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_HSEE);\r
+    }\r
+  }\r
+}\r
+\r
 /**\r
   Reset the XHCI host controller.\r
 \r
@@ -628,6 +661,14 @@ XhcResetHC (
     //\r
     gBS->Stall (XHC_1_MILLISECOND);\r
     Status = XhcWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET, FALSE, Timeout);\r
+\r
+    if (!EFI_ERROR (Status)) {\r
+      //\r
+      // The USBCMD HSEE Bit will be reset to default 0 by USBCMD HCRST.\r
+      // Set USBCMD HSEE Bit if PCICMD SERR# Enable Bit is set.\r
+      //\r
+      XhcSetHsee (Xhc);\r
+    }\r
   }\r
 \r
   return Status;\r