#include <Library/ArmCpuLib.h>\r
#include <Chipset/ArmCortexA9.h>\r
\r
+ INCLUDE AsmMacroExport.inc\r
INCLUDE AsmMacroIoLib.inc\r
\r
- EXPORT ArmGetScuBaseAddress\r
\r
PRESERVE8\r
- AREA ArmCortexA9Helper, CODE, READONLY\r
\r
// IN None\r
// OUT r0 = SCU Base Address\r
-ArmGetScuBaseAddress\r
+ RVCT_ASM_EXPORT ArmGetScuBaseAddress\r
// Read Configuration Base Address Register. ArmCBar cannot be called to get\r
// the Configuration BAR as a stack is not necessary setup. The SCU is at the\r
// offset 0x0000 from the Private Memory Region.\r
\r
// For the moment we assume this will run in SVC mode on ARMv7\r
\r
- EXPORT ArmGicV3GetControlSystemRegisterEnable\r
- EXPORT ArmGicV3SetControlSystemRegisterEnable\r
- EXPORT ArmGicV3EnableInterruptInterface\r
- EXPORT ArmGicV3DisableInterruptInterface\r
- EXPORT ArmGicV3EndOfInterrupt\r
- EXPORT ArmGicV3AcknowledgeInterrupt\r
- EXPORT ArmGicV3SetPriorityMask\r
- EXPORT ArmGicV3SetBinaryPointer\r
\r
- AREA ArmGicV3, CODE, READONLY\r
+ INCLUDE AsmMacroExport.inc\r
\r
//UINT32\r
//EFIAPI\r
//ArmGicGetControlSystemRegisterEnable (\r
// VOID\r
// );\r
-ArmGicV3GetControlSystemRegisterEnable\r
+ RVCT_ASM_EXPORT ArmGicV3GetControlSystemRegisterEnable\r
mrc p15, 0, r0, c12, c12, 5 // ICC_SRE\r
bx lr\r
\r
//ArmGicSetControlSystemRegisterEnable (\r
// IN UINT32 ControlSystemRegisterEnable\r
// );\r
-ArmGicV3SetControlSystemRegisterEnable\r
+ RVCT_ASM_EXPORT ArmGicV3SetControlSystemRegisterEnable\r
mcr p15, 0, r0, c12, c12, 5 // ICC_SRE\r
isb\r
bx lr\r
//ArmGicV3EnableInterruptInterface (\r
// VOID\r
// );\r
-ArmGicV3EnableInterruptInterface\r
+ RVCT_ASM_EXPORT ArmGicV3EnableInterruptInterface\r
mov r0, #1\r
mcr p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1\r
bx lr\r
//ArmGicV3DisableInterruptInterface (\r
// VOID\r
// );\r
-ArmGicV3DisableInterruptInterface\r
+ RVCT_ASM_EXPORT ArmGicV3DisableInterruptInterface\r
mov r0, #0\r
mcr p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1\r
bx lr\r
//ArmGicV3EndOfInterrupt (\r
// IN UINTN InterruptId\r
// );\r
-ArmGicV3EndOfInterrupt\r
+ RVCT_ASM_EXPORT ArmGicV3EndOfInterrupt\r
mcr p15, 0, r0, c12, c12, 1 //ICC_EOIR1\r
bx lr\r
\r
//ArmGicV3AcknowledgeInterrupt (\r
// VOID\r
// );\r
-ArmGicV3AcknowledgeInterrupt\r
+ RVCT_ASM_EXPORT ArmGicV3AcknowledgeInterrupt\r
mrc p15, 0, r0, c12, c8, 0 //ICC_IAR1\r
bx lr\r
\r
//ArmGicV3SetPriorityMask (\r
// IN UINTN Priority\r
// );\r
-ArmGicV3SetPriorityMask\r
+ RVCT_ASM_EXPORT ArmGicV3SetPriorityMask\r
mcr p15, 0, r0, c4, c6, 0 //ICC_PMR\r
bx lr\r
\r
//ArmGicV3SetBinaryPointer (\r
// IN UINTN BinaryPoint\r
// );\r
-ArmGicV3SetBinaryPointer\r
+ RVCT_ASM_EXPORT ArmGicV3SetBinaryPointer\r
mcr p15, 0, r0, c12, c12, 3 //ICC_BPR1\r
bx lr\r
\r
//\r
//\r
\r
- EXPORT ArmCallHvc\r
\r
- AREA ArmHvc, CODE, READONLY\r
+ INCLUDE AsmMacroExport.inc\r
\r
-ArmCallHvc\r
+ RVCT_ASM_EXPORT ArmCallHvc\r
push {r4-r8}\r
// r0 will be popped just after the HVC call\r
push {r0}\r
//------------------------------------------------------------------------------\r
\r
\r
- EXPORT ArmIsMpCore\r
- EXPORT ArmHasMpExtensions\r
- EXPORT ArmEnableAsynchronousAbort\r
- EXPORT ArmDisableAsynchronousAbort\r
- EXPORT ArmEnableIrq\r
- EXPORT ArmDisableIrq\r
- EXPORT ArmEnableFiq\r
- EXPORT ArmDisableFiq\r
- EXPORT ArmEnableInterrupts\r
- EXPORT ArmDisableInterrupts\r
- EXPORT ReadCCSIDR\r
- EXPORT ReadCLIDR\r
- EXPORT ArmReadNsacr\r
- EXPORT ArmWriteNsacr\r
-\r
- AREA ArmLibSupportV7, CODE, READONLY\r
+\r
+ INCLUDE AsmMacroExport.inc\r
\r
\r
//------------------------------------------------------------------------------\r
\r
-ArmIsMpCore\r
+ RVCT_ASM_EXPORT ArmIsMpCore\r
mrc p15,0,R0,c0,c0,5\r
// Get Multiprocessing extension (bit31) & U bit (bit30)\r
and R0, R0, #0xC0000000\r
movne R0, #0\r
bx LR\r
\r
-ArmHasMpExtensions\r
+ RVCT_ASM_EXPORT ArmHasMpExtensions\r
mrc p15,0,R0,c0,c0,5\r
// Get Multiprocessing extension (bit31)\r
lsr R0, R0, #31\r
bx LR\r
\r
-ArmEnableAsynchronousAbort\r
+ RVCT_ASM_EXPORT ArmEnableAsynchronousAbort\r
cpsie a\r
isb\r
bx LR\r
\r
-ArmDisableAsynchronousAbort\r
+ RVCT_ASM_EXPORT ArmDisableAsynchronousAbort\r
cpsid a\r
isb\r
bx LR\r
\r
-ArmEnableIrq\r
+ RVCT_ASM_EXPORT ArmEnableIrq\r
cpsie i\r
isb\r
bx LR\r
\r
-ArmDisableIrq\r
+ RVCT_ASM_EXPORT ArmDisableIrq\r
cpsid i\r
isb\r
bx LR\r
\r
-ArmEnableFiq\r
+ RVCT_ASM_EXPORT ArmEnableFiq\r
cpsie f\r
isb\r
bx LR\r
\r
-ArmDisableFiq\r
+ RVCT_ASM_EXPORT ArmDisableFiq\r
cpsid f\r
isb\r
bx LR\r
\r
-ArmEnableInterrupts\r
+ RVCT_ASM_EXPORT ArmEnableInterrupts\r
cpsie if\r
isb\r
bx LR\r
\r
-ArmDisableInterrupts\r
+ RVCT_ASM_EXPORT ArmDisableInterrupts\r
cpsid if\r
isb\r
bx LR\r
// ReadCCSIDR (\r
// IN UINT32 CSSELR\r
// )\r
-ReadCCSIDR\r
+ RVCT_ASM_EXPORT ReadCCSIDR\r
mcr p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR)\r
isb\r
mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)\r
// ReadCLIDR (\r
// IN UINT32 CSSELR\r
// )\r
-ReadCLIDR\r
+ RVCT_ASM_EXPORT ReadCLIDR\r
mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register\r
bx lr\r
\r
-ArmReadNsacr\r
+ RVCT_ASM_EXPORT ArmReadNsacr\r
mrc p15, 0, r0, c1, c1, 2\r
bx lr\r
\r
-ArmWriteNsacr\r
+ RVCT_ASM_EXPORT ArmWriteNsacr\r
mcr p15, 0, r0, c1, c1, 2\r
bx lr\r
\r
//\r
//------------------------------------------------------------------------------\r
\r
- EXPORT ArmReadCntFrq\r
- EXPORT ArmWriteCntFrq\r
- EXPORT ArmReadCntPct\r
- EXPORT ArmReadCntkCtl\r
- EXPORT ArmWriteCntkCtl\r
- EXPORT ArmReadCntpTval\r
- EXPORT ArmWriteCntpTval\r
- EXPORT ArmReadCntpCtl\r
- EXPORT ArmWriteCntpCtl\r
- EXPORT ArmReadCntvTval\r
- EXPORT ArmWriteCntvTval\r
- EXPORT ArmReadCntvCtl\r
- EXPORT ArmWriteCntvCtl\r
- EXPORT ArmReadCntvCt\r
- EXPORT ArmReadCntpCval\r
- EXPORT ArmWriteCntpCval\r
- EXPORT ArmReadCntvCval\r
- EXPORT ArmWriteCntvCval\r
- EXPORT ArmReadCntvOff\r
- EXPORT ArmWriteCntvOff\r
-\r
- AREA ArmV7ArchTimerSupport, CODE, READONLY\r
+\r
+ INCLUDE AsmMacroExport.inc\r
PRESERVE8\r
\r
-ArmReadCntFrq\r
+ RVCT_ASM_EXPORT ArmReadCntFrq\r
mrc p15, 0, r0, c14, c0, 0 ; Read CNTFRQ\r
bx lr\r
\r
-ArmWriteCntFrq\r
+ RVCT_ASM_EXPORT ArmWriteCntFrq\r
mcr p15, 0, r0, c14, c0, 0 ; Write to CNTFRQ\r
bx lr\r
\r
-ArmReadCntPct\r
+ RVCT_ASM_EXPORT ArmReadCntPct\r
mrrc p15, 0, r0, r1, c14 ; Read CNTPT (Physical counter register)\r
bx lr\r
\r
-ArmReadCntkCtl\r
+ RVCT_ASM_EXPORT ArmReadCntkCtl\r
mrc p15, 0, r0, c14, c1, 0 ; Read CNTK_CTL (Timer PL1 Control Register)\r
bx lr\r
\r
-ArmWriteCntkCtl\r
+ RVCT_ASM_EXPORT ArmWriteCntkCtl\r
mcr p15, 0, r0, c14, c1, 0 ; Write to CNTK_CTL (Timer PL1 Control Register)\r
bx lr\r
\r
-ArmReadCntpTval\r
+ RVCT_ASM_EXPORT ArmReadCntpTval\r
mrc p15, 0, r0, c14, c2, 0 ; Read CNTP_TVAL (PL1 physical timer value register)\r
bx lr\r
\r
-ArmWriteCntpTval\r
+ RVCT_ASM_EXPORT ArmWriteCntpTval\r
mcr p15, 0, r0, c14, c2, 0 ; Write to CNTP_TVAL (PL1 physical timer value register)\r
bx lr\r
\r
-ArmReadCntpCtl\r
+ RVCT_ASM_EXPORT ArmReadCntpCtl\r
mrc p15, 0, r0, c14, c2, 1 ; Read CNTP_CTL (PL1 Physical Timer Control Register)\r
bx lr\r
\r
-ArmWriteCntpCtl\r
+ RVCT_ASM_EXPORT ArmWriteCntpCtl\r
mcr p15, 0, r0, c14, c2, 1 ; Write to CNTP_CTL (PL1 Physical Timer Control Register)\r
bx lr\r
\r
-ArmReadCntvTval\r
+ RVCT_ASM_EXPORT ArmReadCntvTval\r
mrc p15, 0, r0, c14, c3, 0 ; Read CNTV_TVAL (Virtual Timer Value register)\r
bx lr\r
\r
-ArmWriteCntvTval\r
+ RVCT_ASM_EXPORT ArmWriteCntvTval\r
mcr p15, 0, r0, c14, c3, 0 ; Write to CNTV_TVAL (Virtual Timer Value register)\r
bx lr\r
\r
-ArmReadCntvCtl\r
+ RVCT_ASM_EXPORT ArmReadCntvCtl\r
mrc p15, 0, r0, c14, c3, 1 ; Read CNTV_CTL (Virtual Timer Control Register)\r
bx lr\r
\r
-ArmWriteCntvCtl\r
+ RVCT_ASM_EXPORT ArmWriteCntvCtl\r
mcr p15, 0, r0, c14, c3, 1 ; Write to CNTV_CTL (Virtual Timer Control Register)\r
bx lr\r
\r
-ArmReadCntvCt\r
+ RVCT_ASM_EXPORT ArmReadCntvCt\r
mrrc p15, 1, r0, r1, c14 ; Read CNTVCT (Virtual Count Register)\r
bx lr\r
\r
-ArmReadCntpCval\r
+ RVCT_ASM_EXPORT ArmReadCntpCval\r
mrrc p15, 2, r0, r1, c14 ; Read CNTP_CTVAL (Physical Timer Compare Value Register)\r
bx lr\r
\r
-ArmWriteCntpCval\r
+ RVCT_ASM_EXPORT ArmWriteCntpCval\r
mcrr p15, 2, r0, r1, c14 ; Write to CNTP_CTVAL (Physical Timer Compare Value Register)\r
bx lr\r
\r
-ArmReadCntvCval\r
+ RVCT_ASM_EXPORT ArmReadCntvCval\r
mrrc p15, 3, r0, r1, c14 ; Read CNTV_CTVAL (Virtual Timer Compare Value Register)\r
bx lr\r
\r
-ArmWriteCntvCval\r
+ RVCT_ASM_EXPORT ArmWriteCntvCval\r
mcrr p15, 3, r0, r1, c14 ; write to CNTV_CTVAL (Virtual Timer Compare Value Register)\r
bx lr\r
\r
-ArmReadCntvOff\r
+ RVCT_ASM_EXPORT ArmReadCntvOff\r
mrrc p15, 4, r0, r1, c14 ; Read CNTVOFF (virtual Offset register)\r
bx lr\r
\r
-ArmWriteCntvOff\r
+ RVCT_ASM_EXPORT ArmWriteCntvOff\r
mcrr p15, 4, r0, r1, c14 ; Write to CNTVOFF (Virtual Offset register)\r
bx lr\r
\r
//\r
//------------------------------------------------------------------------------\r
\r
- EXPORT ArmInvalidateInstructionCache\r
- EXPORT ArmInvalidateDataCacheEntryByMVA\r
- EXPORT ArmCleanDataCacheEntryByMVA\r
- EXPORT ArmCleanInvalidateDataCacheEntryByMVA\r
- EXPORT ArmInvalidateDataCacheEntryBySetWay\r
- EXPORT ArmCleanDataCacheEntryBySetWay\r
- EXPORT ArmCleanInvalidateDataCacheEntryBySetWay\r
- EXPORT ArmEnableMmu\r
- EXPORT ArmDisableMmu\r
- EXPORT ArmDisableCachesAndMmu\r
- EXPORT ArmMmuEnabled\r
- EXPORT ArmEnableDataCache\r
- EXPORT ArmDisableDataCache\r
- EXPORT ArmEnableInstructionCache\r
- EXPORT ArmDisableInstructionCache\r
- EXPORT ArmEnableSWPInstruction\r
- EXPORT ArmEnableBranchPrediction\r
- EXPORT ArmDisableBranchPrediction\r
- EXPORT ArmSetLowVectors\r
- EXPORT ArmSetHighVectors\r
- EXPORT ArmV7AllDataCachesOperation\r
- EXPORT ArmDataMemoryBarrier\r
- EXPORT ArmDataSynchronizationBarrier\r
- EXPORT ArmInstructionSynchronizationBarrier\r
- EXPORT ArmReadVBar\r
- EXPORT ArmWriteVBar\r
- EXPORT ArmEnableVFP\r
- EXPORT ArmCallWFI\r
- EXPORT ArmReadCbar\r
- EXPORT ArmReadMpidr\r
- EXPORT ArmReadTpidrurw\r
- EXPORT ArmWriteTpidrurw\r
- EXPORT ArmIsArchTimerImplemented\r
- EXPORT ArmReadIdPfr1\r
- EXPORT ArmReadIdMmfr0\r
-\r
- AREA ArmV7Support, CODE, READONLY\r
+\r
+ INCLUDE AsmMacroExport.inc\r
PRESERVE8\r
\r
DC_ON EQU ( 0x1:SHL:2 )\r
CTRL_I_BIT EQU (1 << 12)\r
\r
\r
-ArmInvalidateDataCacheEntryByMVA\r
+ RVCT_ASM_EXPORT ArmInvalidateDataCacheEntryByMVA\r
mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line\r
bx lr\r
\r
-ArmCleanDataCacheEntryByMVA\r
+ RVCT_ASM_EXPORT ArmCleanDataCacheEntryByMVA\r
mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line\r
bx lr\r
\r
\r
-ArmCleanInvalidateDataCacheEntryByMVA\r
+ RVCT_ASM_EXPORT ArmCleanInvalidateDataCacheEntryByMVA\r
mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line\r
bx lr\r
\r
\r
-ArmInvalidateDataCacheEntryBySetWay\r
+ RVCT_ASM_EXPORT ArmInvalidateDataCacheEntryBySetWay\r
mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line\r
bx lr\r
\r
\r
-ArmCleanInvalidateDataCacheEntryBySetWay\r
+ RVCT_ASM_EXPORT ArmCleanInvalidateDataCacheEntryBySetWay\r
mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line\r
bx lr\r
\r
\r
-ArmCleanDataCacheEntryBySetWay\r
+ RVCT_ASM_EXPORT ArmCleanDataCacheEntryBySetWay\r
mcr p15, 0, r0, c7, c10, 2 ; Clean this line\r
bx lr\r
\r
\r
-ArmInvalidateInstructionCache\r
+ RVCT_ASM_EXPORT ArmInvalidateInstructionCache\r
mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache\r
isb\r
bx LR\r
\r
-ArmEnableMmu\r
+ RVCT_ASM_EXPORT ArmEnableMmu\r
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
orr R0,R0,#1 ; Set SCTLR.M bit : Enable MMU\r
mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
isb\r
bx LR\r
\r
-ArmDisableMmu\r
+ RVCT_ASM_EXPORT ArmDisableMmu\r
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU\r
mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
isb\r
bx LR\r
\r
-ArmDisableCachesAndMmu\r
+ RVCT_ASM_EXPORT ArmDisableCachesAndMmu\r
mrc p15, 0, r0, c1, c0, 0 ; Get control register\r
bic r0, r0, #CTRL_M_BIT ; Disable MMU\r
bic r0, r0, #CTRL_C_BIT ; Disable D Cache\r
isb\r
bx LR\r
\r
-ArmMmuEnabled\r
+ RVCT_ASM_EXPORT ArmMmuEnabled\r
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
and R0,R0,#1\r
bx LR\r
\r
-ArmEnableDataCache\r
+ RVCT_ASM_EXPORT ArmEnableDataCache\r
ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit\r
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
orr R0,R0,R1 ; Set SCTLR.C bit : Data and unified caches enabled\r
isb\r
bx LR\r
\r
-ArmDisableDataCache\r
+ RVCT_ASM_EXPORT ArmDisableDataCache\r
ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit\r
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
bic R0,R0,R1 ; Clear SCTLR.C bit : Data and unified caches disabled\r
isb\r
bx LR\r
\r
-ArmEnableInstructionCache\r
+ RVCT_ASM_EXPORT ArmEnableInstructionCache\r
ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit\r
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
orr R0,R0,R1 ; Set SCTLR.I bit : Instruction caches enabled\r
isb\r
bx LR\r
\r
-ArmDisableInstructionCache\r
+ RVCT_ASM_EXPORT ArmDisableInstructionCache\r
ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit\r
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
BIC R0,R0,R1 ; Clear SCTLR.I bit : Instruction caches disabled\r
isb\r
bx LR\r
\r
-ArmEnableSWPInstruction\r
+ RVCT_ASM_EXPORT ArmEnableSWPInstruction\r
mrc p15, 0, r0, c1, c0, 0\r
orr r0, r0, #0x00000400\r
mcr p15, 0, r0, c1, c0, 0\r
isb\r
bx LR\r
\r
-ArmEnableBranchPrediction\r
+ RVCT_ASM_EXPORT ArmEnableBranchPrediction\r
mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
orr r0, r0, #0x00000800 ;\r
mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
isb\r
bx LR\r
\r
-ArmDisableBranchPrediction\r
+ RVCT_ASM_EXPORT ArmDisableBranchPrediction\r
mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
bic r0, r0, #0x00000800 ;\r
mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
isb\r
bx LR\r
\r
-ArmSetLowVectors\r
+ RVCT_ASM_EXPORT ArmSetLowVectors\r
mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
bic r0, r0, #0x00002000 ; clear V bit\r
mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
isb\r
bx LR\r
\r
-ArmSetHighVectors\r
+ RVCT_ASM_EXPORT ArmSetHighVectors\r
mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
orr r0, r0, #0x00002000 ; Set V bit\r
mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
isb\r
bx LR\r
\r
-ArmV7AllDataCachesOperation\r
+ RVCT_ASM_EXPORT ArmV7AllDataCachesOperation\r
stmfd SP!,{r4-r12, LR}\r
mov R1, R0 ; Save Function call in R1\r
mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR\r
ldmfd SP!, {r4-r12, lr}\r
bx LR\r
\r
-ArmDataMemoryBarrier\r
+ RVCT_ASM_EXPORT ArmDataMemoryBarrier\r
dmb\r
bx LR\r
\r
-ArmDataSynchronizationBarrier\r
+ RVCT_ASM_EXPORT ArmDataSynchronizationBarrier\r
dsb\r
bx LR\r
\r
-ArmInstructionSynchronizationBarrier\r
+ RVCT_ASM_EXPORT ArmInstructionSynchronizationBarrier\r
isb\r
bx LR\r
\r
-ArmReadVBar\r
+ RVCT_ASM_EXPORT ArmReadVBar\r
// Set the Address of the Vector Table in the VBAR register\r
mrc p15, 0, r0, c12, c0, 0\r
bx lr\r
\r
-ArmWriteVBar\r
+ RVCT_ASM_EXPORT ArmWriteVBar\r
// Set the Address of the Vector Table in the VBAR register\r
mcr p15, 0, r0, c12, c0, 0\r
// Ensure the SCTLR.V bit is clear\r
isb\r
bx lr\r
\r
-ArmEnableVFP\r
+ RVCT_ASM_EXPORT ArmEnableVFP\r
// Read CPACR (Coprocessor Access Control Register)\r
mrc p15, 0, r0, c1, c0, 2\r
// Enable VPF access (Full Access to CP10, CP11) (V* instructions)\r
mcr p10,#0x7,r0,c8,c0,#0\r
bx lr\r
\r
-ArmCallWFI\r
+ RVCT_ASM_EXPORT ArmCallWFI\r
wfi\r
bx lr\r
\r
//Note: Return 0 in Uniprocessor implementation\r
-ArmReadCbar\r
+ RVCT_ASM_EXPORT ArmReadCbar\r
mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register\r
bx lr\r
\r
-ArmReadMpidr\r
+ RVCT_ASM_EXPORT ArmReadMpidr\r
mrc p15, 0, r0, c0, c0, 5 ; read MPIDR\r
bx lr\r
\r
-ArmReadTpidrurw\r
+ RVCT_ASM_EXPORT ArmReadTpidrurw\r
mrc p15, 0, r0, c13, c0, 2 ; read TPIDRURW\r
bx lr\r
\r
-ArmWriteTpidrurw\r
+ RVCT_ASM_EXPORT ArmWriteTpidrurw\r
mcr p15, 0, r0, c13, c0, 2 ; write TPIDRURW\r
bx lr\r
\r
-ArmIsArchTimerImplemented\r
+ RVCT_ASM_EXPORT ArmIsArchTimerImplemented\r
mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1\r
and r0, r0, #0x000F0000\r
bx lr\r
\r
-ArmReadIdPfr1\r
+ RVCT_ASM_EXPORT ArmReadIdPfr1\r
mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1 Register\r
bx lr\r
\r
-ArmReadIdMmfr0\r
+ RVCT_ASM_EXPORT ArmReadIdMmfr0\r
mrc p15, 0, r0, c0, c1, 4 ; Read ID_MMFR0 Register\r
bx lr\r
\r
\r
INCLUDE AsmMacroIoLib.inc\r
\r
- EXPORT ArmReadMidr\r
- EXPORT ArmCacheInfo\r
- EXPORT ArmGetInterruptState\r
- EXPORT ArmGetFiqState\r
- EXPORT ArmGetTTBR0BaseAddress\r
- EXPORT ArmSetTTBR0\r
- EXPORT ArmSetDomainAccessControl\r
- EXPORT CPSRMaskInsert\r
- EXPORT CPSRRead\r
- EXPORT ArmReadCpacr\r
- EXPORT ArmWriteCpacr\r
- EXPORT ArmWriteAuxCr\r
- EXPORT ArmReadAuxCr\r
- EXPORT ArmInvalidateTlb\r
- EXPORT ArmUpdateTranslationTableEntry\r
- EXPORT ArmReadScr\r
- EXPORT ArmWriteScr\r
- EXPORT ArmReadMVBar\r
- EXPORT ArmWriteMVBar\r
- EXPORT ArmReadHVBar\r
- EXPORT ArmWriteHVBar\r
- EXPORT ArmCallWFE\r
- EXPORT ArmCallSEV\r
- EXPORT ArmReadSctlr\r
- EXPORT ArmReadCpuActlr\r
- EXPORT ArmWriteCpuActlr\r
-\r
- AREA ArmLibSupport, CODE, READONLY\r
-\r
-ArmReadMidr\r
+\r
+ INCLUDE AsmMacroExport.inc\r
+\r
+ RVCT_ASM_EXPORT ArmReadMidr\r
mrc p15,0,R0,c0,c0,0\r
bx LR\r
\r
-ArmCacheInfo\r
+ RVCT_ASM_EXPORT ArmCacheInfo\r
mrc p15,0,R0,c0,c0,1\r
bx LR\r
\r
-ArmGetInterruptState\r
+ RVCT_ASM_EXPORT ArmGetInterruptState\r
mrs R0,CPSR\r
tst R0,#0x80 // Check if IRQ is enabled.\r
moveq R0,#1\r
movne R0,#0\r
bx LR\r
\r
-ArmGetFiqState\r
+ RVCT_ASM_EXPORT ArmGetFiqState\r
mrs R0,CPSR\r
tst R0,#0x40 // Check if FIQ is enabled.\r
moveq R0,#1\r
movne R0,#0\r
bx LR\r
\r
-ArmSetDomainAccessControl\r
+ RVCT_ASM_EXPORT ArmSetDomainAccessControl\r
mcr p15,0,r0,c3,c0,0\r
bx lr\r
\r
-CPSRMaskInsert // on entry, r0 is the mask and r1 is the field to insert\r
+ RVCT_ASM_EXPORT CPSRMaskInsert\r
stmfd sp!, {r4-r12, lr} // save all the banked registers\r
mov r3, sp // copy the stack pointer into a non-banked register\r
mrs r2, cpsr // read the cpsr\r
ldmfd sp!, {r4-r12, lr} // restore registers\r
bx lr // return (hopefully thumb-safe!) // return (hopefully thumb-safe!)\r
\r
-CPSRRead\r
+ RVCT_ASM_EXPORT CPSRRead\r
mrs r0, cpsr\r
bx lr\r
\r
-ArmReadCpacr\r
+ RVCT_ASM_EXPORT ArmReadCpacr\r
mrc p15, 0, r0, c1, c0, 2\r
bx lr\r
\r
-ArmWriteCpacr\r
+ RVCT_ASM_EXPORT ArmWriteCpacr\r
mcr p15, 0, r0, c1, c0, 2\r
isb\r
bx lr\r
\r
-ArmWriteAuxCr\r
+ RVCT_ASM_EXPORT ArmWriteAuxCr\r
mcr p15, 0, r0, c1, c0, 1\r
bx lr\r
\r
-ArmReadAuxCr\r
+ RVCT_ASM_EXPORT ArmReadAuxCr\r
mrc p15, 0, r0, c1, c0, 1\r
bx lr\r
\r
-ArmSetTTBR0\r
+ RVCT_ASM_EXPORT ArmSetTTBR0\r
mcr p15,0,r0,c2,c0,0\r
isb\r
bx lr\r
\r
-ArmGetTTBR0BaseAddress\r
+ RVCT_ASM_EXPORT ArmGetTTBR0BaseAddress\r
mrc p15,0,r0,c2,c0,0\r
LoadConstantToReg(0xFFFFC000, r1)\r
and r0, r0, r1\r
// IN VOID *TranslationTableEntry // R0\r
// IN VOID *MVA // R1\r
// );\r
-ArmUpdateTranslationTableEntry\r
+ RVCT_ASM_EXPORT ArmUpdateTranslationTableEntry\r
mcr p15,0,R0,c7,c14,1 // DCCIMVAC Clean data cache by MVA\r
dsb\r
mcr p15,0,R1,c8,c7,1 // TLBIMVA TLB Invalidate MVA\r
isb\r
bx lr\r
\r
-ArmInvalidateTlb\r
+ RVCT_ASM_EXPORT ArmInvalidateTlb\r
mov r0,#0\r
mcr p15,0,r0,c8,c7,0\r
mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp\r
isb\r
bx lr\r
\r
-ArmReadScr\r
+ RVCT_ASM_EXPORT ArmReadScr\r
mrc p15, 0, r0, c1, c1, 0\r
bx lr\r
\r
-ArmWriteScr\r
+ RVCT_ASM_EXPORT ArmWriteScr\r
mcr p15, 0, r0, c1, c1, 0\r
bx lr\r
\r
-ArmReadHVBar\r
+ RVCT_ASM_EXPORT ArmReadHVBar\r
mrc p15, 4, r0, c12, c0, 0\r
bx lr\r
\r
-ArmWriteHVBar\r
+ RVCT_ASM_EXPORT ArmWriteHVBar\r
mcr p15, 4, r0, c12, c0, 0\r
bx lr\r
\r
-ArmReadMVBar\r
+ RVCT_ASM_EXPORT ArmReadMVBar\r
mrc p15, 0, r0, c12, c0, 1\r
bx lr\r
\r
-ArmWriteMVBar\r
+ RVCT_ASM_EXPORT ArmWriteMVBar\r
mcr p15, 0, r0, c12, c0, 1\r
bx lr\r
\r
-ArmCallWFE\r
+ RVCT_ASM_EXPORT ArmCallWFE\r
wfe\r
bx lr\r
\r
-ArmCallSEV\r
+ RVCT_ASM_EXPORT ArmCallSEV\r
sev\r
bx lr\r
\r
-ArmReadSctlr\r
+ RVCT_ASM_EXPORT ArmReadSctlr\r
mrc p15, 0, r0, c1, c0, 0 // Read SCTLR into R0 (Read control register configuration data)\r
bx lr\r
\r
\r
-ArmReadCpuActlr\r
+ RVCT_ASM_EXPORT ArmReadCpuActlr\r
mrc p15, 0, r0, c1, c0, 1\r
bx lr\r
\r
-ArmWriteCpuActlr\r
+ RVCT_ASM_EXPORT ArmWriteCpuActlr\r
mcr p15, 0, r0, c1, c0, 1\r
dsb\r
isb\r
//\r
//\r
\r
- EXPORT ArmCallSmc\r
\r
- AREA ArmSmc, CODE, READONLY\r
+ INCLUDE AsmMacroExport.inc\r
\r
-ArmCallSmc\r
+ RVCT_ASM_EXPORT ArmCallSmc\r
push {r4-r8}\r
// r0 will be popped just after the SMC call\r
push {r0}\r
//\r
//\r
\r
- EXPORT ArmCallSmc\r
\r
- AREA ArmSmc, CODE, READONLY\r
+ INCLUDE AsmMacroExport.inc\r
\r
-ArmCallSmc\r
+ RVCT_ASM_EXPORT ArmCallSmc\r
bx lr\r
\r
END\r
IN UINTN Length\r
)\r
**/\r
- EXPORT InternalMemCopyMem\r
\r
- AREA AsmMemStuff, CODE, READONLY\r
+ INCLUDE AsmMacroExport.inc\r
\r
-InternalMemCopyMem\r
+ RVCT_ASM_EXPORT InternalMemCopyMem\r
stmfd sp!, {r4-r11, lr}\r
// Save the input parameters in extra registers (r11 = destination, r14 = source, r12 = length)\r
mov r11, r0\r
)\r
**/\r
\r
- EXPORT InternalMemSetMem\r
\r
- AREA AsmMemStuff, CODE, READONLY\r
+ INCLUDE AsmMacroExport.inc\r
\r
-InternalMemSetMem\r
+ RVCT_ASM_EXPORT InternalMemSetMem\r
stmfd sp!, {r4-r11, lr}\r
tst r0, #3\r
movne r3, #0\r
\r
[Packages]\r
MdePkg/MdePkg.dec\r
+ ArmPkg/ArmPkg.dec\r
\r
[LibraryClasses]\r
DebugLib\r
IN UINTN Length\r
)\r
**/\r
- EXPORT InternalMemCopyMem\r
\r
- AREA AsmMemStuff, CODE, READONLY\r
+ INCLUDE AsmMacroExport.inc\r
\r
-InternalMemCopyMem\r
+ RVCT_ASM_EXPORT InternalMemCopyMem\r
stmfd sp!, {r4, r9, lr}\r
tst r0, #3\r
mov r4, r0\r
)\r
**/\r
\r
- EXPORT InternalMemSetMem\r
\r
- AREA AsmMemStuff, CODE, READONLY\r
+ INCLUDE AsmMacroExport.inc\r
\r
-InternalMemSetMem\r
+ RVCT_ASM_EXPORT InternalMemSetMem\r
stmfd sp!, {lr}\r
tst r0, #3\r
movne r3, #0\r
\r
[Packages]\r
MdePkg/MdePkg.dec\r
+ ArmPkg/ArmPkg.dec\r
\r
[LibraryClasses]\r
DebugLib\r
//------------------------------------------------------------------------------\r
\r
\r
- EXPORT __aeabi_lasr\r
\r
- AREA Math, CODE, READONLY\r
+ INCLUDE AsmMacroExport.inc\r
\r
;\r
;UINT32\r
; IN UINT32 Divisor\r
; );\r
;\r
-__aeabi_lasr\r
+ RVCT_ASM_EXPORT __aeabi_lasr\r
SUBS r3,r2,#0x20\r
BPL {pc} + 0x18 ; 0x1c\r
RSB r3,r2,#0x20\r
//------------------------------------------------------------------------------\r
\r
\r
- EXPORT __aeabi_ldivmod\r
EXTERN __aeabi_uldivmod\r
\r
- AREA Math, CODE, READONLY\r
+ INCLUDE AsmMacroExport.inc\r
\r
;\r
;UINT32\r
; );\r
;\r
\r
-__aeabi_ldivmod\r
+ RVCT_ASM_EXPORT __aeabi_ldivmod\r
PUSH {r4,lr}\r
ASRS r4,r1,#1\r
EOR r4,r4,r3,LSR #1\r
//------------------------------------------------------------------------------\r
\r
\r
- EXPORT __aeabi_llsl\r
\r
- AREA Math, CODE, READONLY\r
+ INCLUDE AsmMacroExport.inc\r
\r
;\r
;VOID\r
; );\r
;\r
\r
-__aeabi_llsl\r
+ RVCT_ASM_EXPORT __aeabi_llsl\r
SUBS r3,r2,#0x20\r
BPL {pc} + 0x18 ; 0x1c\r
RSB r3,r2,#0x20\r
//------------------------------------------------------------------------------\r
\r
\r
- EXPORT __aeabi_llsr\r
\r
- AREA Math, CODE, READONLY\r
+ INCLUDE AsmMacroExport.inc\r
\r
;\r
;VOID\r
; IN UINT32 Size\r
; );\r
;\r
-__aeabi_llsr\r
+ RVCT_ASM_EXPORT __aeabi_llsr\r
SUBS r3,r2,#0x20\r
BPL {pc} + 0x18 ; 0x1c\r
RSB r3,r2,#0x20\r
//------------------------------------------------------------------------------\r
\r
\r
- EXPORT __aeabi_memcpy\r
\r
- AREA Memcpy, CODE, READONLY\r
+ INCLUDE AsmMacroExport.inc\r
\r
;\r
;VOID\r
; IN UINT32 Size\r
; );\r
;\r
-__aeabi_memcpy\r
+ RVCT_ASM_EXPORT __aeabi_memcpy\r
cmp r2, #0\r
bxeq lr\r
push {lr}\r
//------------------------------------------------------------------------------\r
\r
\r
- EXPORT __aeabi_memcpy4\r
\r
- AREA Memcpy4, CODE, READONLY\r
+ INCLUDE AsmMacroExport.inc\r
\r
;\r
;VOID\r
; IN UINT32 Size\r
; );\r
;\r
-__aeabi_memcpy4\r
+ RVCT_ASM_EXPORT __aeabi_memcpy4\r
stmdb sp!, {r4, lr}\r
subs r2, r2, #32 ; 0x20\r
bcc memcpy4_label2\r
//------------------------------------------------------------------------------\r
\r
\r
- EXPORT __aeabi_memmove\r
\r
- AREA Memmove, CODE, READONLY\r
+ INCLUDE AsmMacroExport.inc\r
\r
;\r
;VOID\r
; IN UINT32 Size\r
; );\r
;\r
-__aeabi_memmove\r
+ RVCT_ASM_EXPORT __aeabi_memmove\r
CMP r2, #0\r
BXEQ lr\r
CMP r0, r1\r
\r
\r
\r
- EXPORT __ARM_switch8\r
\r
- AREA ArmSwitch, CODE, READONLY\r
+ INCLUDE AsmMacroExport.inc\r
\r
-__ARM_switch8\r
+ RVCT_ASM_EXPORT __ARM_switch8\r
LDRB r12,[lr,#-1]\r
CMP r3,r12\r
LDRBCC r3,[lr,r3]\r
\r
\r
\r
- EXPORT __aeabi_uldivmod\r
\r
- AREA Uldivmod, CODE, READONLY\r
+ INCLUDE AsmMacroExport.inc\r
\r
;\r
;UINT64\r
; IN UINT64 Divisor\r
; )\r
;\r
-__aeabi_uldivmod\r
+ RVCT_ASM_EXPORT __aeabi_uldivmod\r
stmdb sp!, {r4, r5, r6, lr}\r
mov r4, r1\r
mov r5, r0\r
\r
\r
\r
- EXPORT __aeabi_uread4\r
- EXPORT __aeabi_uread8\r
\r
- AREA Uread4, CODE, READONLY\r
+ INCLUDE AsmMacroExport.inc\r
\r
;\r
;UINT32\r
; IN VOID *Pointer\r
; );\r
;\r
-__aeabi_uread4\r
+ RVCT_ASM_EXPORT __aeabi_uread4\r
ldrb r1, [r0]\r
ldrb r2, [r0, #1]\r
ldrb r3, [r0, #2]\r
; IN VOID *Pointer\r
; );\r
;\r
-__aeabi_uread8\r
+ RVCT_ASM_EXPORT __aeabi_uread8\r
mov r3, r0\r
\r
ldrb r1, [r3]\r
//------------------------------------------------------------------------------\r
\r
\r
- EXPORT __aeabi_uwrite4\r
- EXPORT __aeabi_uwrite8\r
\r
- AREA Uwrite4, CODE, READONLY\r
+ INCLUDE AsmMacroExport.inc\r
\r
;\r
;UINT32\r
; );\r
;\r
;\r
-__aeabi_uwrite4\r
+ RVCT_ASM_EXPORT __aeabi_uwrite4\r
mov r2, r0, lsr #8\r
strb r0, [r1]\r
strb r2, [r1, #1]\r
; );\r
;\r
;\r
-__aeabi_uwrite8\r
+ RVCT_ASM_EXPORT __aeabi_uwrite8\r
mov r3, r0, lsr #8\r
strb r0, [r2]\r
strb r3, [r2, #1]\r
\r
[Packages]\r
MdePkg/MdePkg.dec\r
+ ArmPkg/ArmPkg.dec\r
\r
[LibraryClasses]\r
\r
projects / mirror_edk2.git / commitdiff