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| 2019-09-17 | Bin Meng | riscv: sifive_e: prci: Update the PRCI register block... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Bin Meng | riscv: sifive_e: prci: Fix a typo of hfxosccfg register... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Bin Meng | riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Bin Meng | riscv: sifive_u: Remove the unnecessary include of... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Bin Meng | riscv: roms: Remove executable attribute of opensbi... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Bin Meng | riscv: hw: Remove the unnecessary include of target... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Bin Meng | riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Bin Meng | riscv: hw: Change create_fdt() to return void Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Bin Meng | riscv: hw: Remove not needed PLIC properties in device... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Bin Meng | riscv: hw: Use qemu_fdt_setprop_cell() for property... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Bin Meng | riscv: hw: Remove superfluous "linux, phandle" property Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Bin Meng | riscv: hw: Remove duplicated "hw/hw.h" inclusion Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Bin Meng | riscv: sifive_test: Add reset functionality Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Bin Meng | riscv: hmp: Add a command to show virtual memory mappings Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Bin Meng | riscv: Resolve full path of the given bios image Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Bin Meng | riscv: Add a helper routine for finding firmware Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Bin Meng | riscv: rv32: Root page table address can be larger... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Alistair Francis | target/riscv: Update the Hypervisor CSRs to v0.4 Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Alistair Francis | target/riscv: Create function to test if FP is enabled Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Alistair Francis | riscv: plic: Remove unused interrupt functions Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Philippe Mathieu... | target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE)... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Philippe Mathieu... | target/riscv/pmp: Restrict priviledged PMP to system... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Guenter Roeck | riscv: sifive_u: Fix clock-names property for ethernet... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Guenter Roeck | riscv: sivive_u: Add dummy serial clock and aliases... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-09-17 | Guenter Roeck | riscv: sifive_u: Add support for loading initrd Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-07-26 | Alistair Francis | riscv/boot: Fixup the RISC-V firmware warning Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-07-18 | Alistair Francis | hw/riscv: Load OpenSBI as the default firmware Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-07-18 | Alistair Francis | roms: Add OpenSBI version 0.4 Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-06-27 | Alistair Francis | hw/riscv: Extend the kernel loading support Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-06-27 | Alistair Francis | hw/riscv: Add support for loading a firmware Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-06-27 | Alistair Francis | hw/riscv: Split out the boot functions Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-06-27 | Bin Meng | riscv: sifive_u: Update the plic hart config to support... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-06-27 | Bin Meng | riscv: sifive_u: Do not create hard-coded phandles... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-06-27 | Wladimir J. van... | disas/riscv: Fix `rdinstreth` constraint Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-06-27 | Michael Clark | disas/riscv: Disassemble reserved compressed encodings... Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-06-26 | Atish Patra | riscv: virt: Add cpu-topology DT node. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-06-26 | Jim Wilson | RISC-V: Update syscall list for 32-bit support. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-06-26 | Joel Sing | RISC-V: Clear load reservations on context switch and SC Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-06-26 | Palmer Dabbelt | RISC-V: Add support for the Zicsr extension Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-06-26 | Palmer Dabbelt | RISC-V: Add support for the Zifencei extension Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-06-25 | Alistair Francis | target/riscv: Add support for disabling/enabling Counters Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-06-25 | Alistair Francis | target/riscv: Remove user version information Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-06-25 | Alistair Francis | target/riscv: Require either I or E base extension Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-06-25 | Alistair Francis | qemu-deprecated.texi: Deprecate the RISC-V privledge... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-06-25 | Alistair Francis | target/riscv: Set privledge spec 1.11.0 as default Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-06-25 | Alistair Francis | target/riscv: Add the mcountinhibit CSR Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-06-24 | Alistair Francis | target/riscv: Add the privledge spec version 1.11.0 Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-06-24 | Alistair Francis | target/riscv: Restructure deprecatd CPUs Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-06-24 | Palmer Dabbelt | RISC-V: Fix a memory leak when realizing a sifive_e Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-06-24 | Bin Meng | riscv: virt: Correct pci "bus-range" encoding Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-06-24 | Hesham Almatary | RISC-V: Fix a PMP check with the correct access size Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-06-24 | Hesham Almatary | RISC-V: Fix a PMP bug where it succeeds even if PMP... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-06-24 | Hesham Almatary | RISC-V: Check PMP during Page Table Walks Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-06-24 | Hesham Almatary | RISC-V: Check for the effective memory privilege mode... Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-06-24 | Hesham Almatary | RISC-V: Raise access fault exceptions on PMP violations Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-06-24 | Hesham Almatary | RISC-V: Only Check PMP if MMU translation succeeds Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-06-24 | Michael Clark | target/riscv: Implement riscv_cpu_unassigned_access Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-06-24 | Dayeol Lee | target/riscv: Fix PMP range boundary address bug Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-06-24 | Nathaniel Graff | sifive_prci: Read and write PRCI registers Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-06-24 | Alistair Francis | target/riscv: Allow setting ISA extensions via CPU... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-05-24 | Jonathan Behrens | target/riscv: Only flush TLB if SATP.ASID changes Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-05-24 | Jonathan Behrens | target/riscv: More accurate handling of `sip` CSR Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-05-24 | Richard Henderson | target/riscv: Add checks for several RVC reserved operands Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-05-24 | Alistair Francis | target/riscv: Add the HGATP register masks Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-05-24 | Alistair Francis | target/riscv: Add the HSTATUS register masks Reviwed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-05-24 | Alistair Francis | target/riscv: Add Hypervisor CSR macros Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-05-24 | Alistair Francis | target/riscv: Allow setting mstatus virtulisation bits Revieweb-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-05-24 | Alistair Francis | target/riscv: Add the MPV and MTL mstatus bits Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-05-24 | Alistair Francis | target/riscv: Improve the scause logic Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-05-24 | Alistair Francis | target/riscv: Trigger interrupt on MIP update asynchronously Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-05-24 | Alistair Francis | target/riscv: Mark privilege level 2 as reserved Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-05-24 | Alistair Francis | riscv: spike: Add a generic spike machine Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-05-24 | Alistair Francis | target/riscv: Deprecate the generic no MMU CPUs Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-05-24 | Alistair Francis | target/riscv: Add a base 32 and 64 bit CPU Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-05-24 | Alistair Francis | target/riscv: Create settable CPU properties Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-05-24 | Alistair Francis | riscv: virt: Allow specifying a CPU via commandline Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-05-24 | Alistair Francis | linux-user/riscv: Add the CPU type as a comment Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-05-24 | Jonathan Behrens | target/riscv: Remove unused include of riscv_htif.h... Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-05-24 | Richard Henderson | target/riscv: Remove spaces from register names Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-05-24 | Richard Henderson | target/riscv: Split gen_arith_imm into functional and... Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-05-24 | Richard Henderson | target/riscv: Split RVC32 and RVC64 insns into separate... Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-05-24 | Richard Henderson | target/riscv: Use pattern groups in insn16.decode Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-05-24 | Richard Henderson | target/riscv: Merge argument decode for RVC shifti Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-05-24 | Richard Henderson | target/riscv: Merge argument sets for insn32 and insn16 Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-05-24 | Richard Henderson | target/riscv: Use --static-decode for decodetree Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-05-24 | Richard Henderson | target/riscv: Name the argument sets for all of insn32... Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-05-24 | Fabien Chouteau | RISC-V: fix single stepping over ret and other branching... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-05-24 | Jonathan Behrens | target/riscv: Do not allow sfence.vma from user mode Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-05-24 | Fabien Chouteau | SiFive RISC-V GPIO Device Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-04-04 | Alistair Francis | riscv: plic: Log guest errors Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-04-04 | Alistair Francis | riscv: plic: Fix incorrect irq calculation Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-03-26 | Kito Cheng | target/riscv: Fix wrong expanding for c.fswsp Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-03-22 | Palmer Dabbelt | target/riscv: Zero extend the inputs of divuw and remuw Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-03-19 | Bin Meng | riscv: sifive_u: Correct UART0's IRQ in the device... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-03-19 | Bin Meng | riscv: sifive_uart: Generate TX interrupt Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-03-19 | Alistair Francis | target/riscv: Remove unused struct Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-03-19 | Alistair Francis | riscv: sifive_u: Allow up to 4 CPUs to be created Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-03-19 | Michael Clark | RISC-V: Update load reservation comment in do_interrupt Cc: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-03-19 | Michael Clark | RISC-V: Convert trap debugging to trace events Cc: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-03-19 | Michael Clark | RISC-V: Add support for vectored interrupts Cc: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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