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1 | /********************************************************************** |
2 | Copyright(c) 2019 Arm Corporation All rights reserved. | |
3 | ||
4 | Redistribution and use in source and binary forms, with or without | |
5 | modification, are permitted provided that the following conditions | |
6 | are met: | |
7 | * Redistributions of source code must retain the above copyright | |
8 | notice, this list of conditions and the following disclaimer. | |
9 | * Redistributions in binary form must reproduce the above copyright | |
10 | notice, this list of conditions and the following disclaimer in | |
11 | the documentation and/or other materials provided with the | |
12 | distribution. | |
13 | * Neither the name of Arm Corporation nor the names of its | |
14 | contributors may be used to endorse or promote products derived | |
15 | from this software without specific prior written permission. | |
16 | ||
17 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
18 | "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
19 | LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
20 | A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
21 | OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
22 | SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
23 | LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
24 | DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
25 | THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
26 | (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
27 | OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
28 | **********************************************************************/ | |
29 | .arch armv8-a+crypto | |
30 | .text | |
31 | .align 2 | |
32 | .p2align 3,,7 | |
33 | ||
34 | /* | |
35 | Macros | |
36 | */ | |
37 | ||
38 | .macro declare_var_vector_reg name:req,reg:req | |
39 | \name\()_q .req q\reg | |
40 | \name\()_v .req v\reg | |
41 | \name\()_s .req s\reg | |
42 | .endm | |
43 | ||
44 | /** | |
45 | maros for round 4-67 | |
46 | */ | |
47 | .macro sha1_4_rounds inst:req,msg0:req,msg1:req,msg2:req,msg3:req,abcd:req,e0:req,tmp0:req,e1:req,tmp1:req,k:req | |
48 | sha1h \e0\()_s, \abcd\()_s | |
49 | \inst \abcd\()_q,\e1\()_s,\tmp1\()_v.4s | |
50 | add \tmp1\()_v.4s,\msg3\()_v.4s,\k\()_v.4s | |
51 | sha1su1 \msg0\()_v.4s,\msg3\()_v.4s | |
52 | sha1su0 \msg1\()_v.4s,\msg2\()_v.4s,\msg3\()_v.4s | |
53 | .endm | |
54 | ||
55 | ||
56 | /* | |
57 | Variable list | |
58 | */ | |
59 | ||
60 | declare_var_vector_reg key_0,28 | |
61 | declare_var_vector_reg key_1,29 | |
62 | declare_var_vector_reg key_2,30 | |
63 | declare_var_vector_reg key_3,31 | |
64 | ||
65 | ||
66 | /* | |
67 | digest variables | |
68 | */ | |
69 | declare_var_vector_reg abcd,0 | |
70 | declare_var_vector_reg e0,1 | |
71 | declare_var_vector_reg e1,2 | |
72 | declare_var_vector_reg abcd_saved,3 | |
73 | declare_var_vector_reg e0_saved,4 | |
74 | /* | |
75 | Message variables | |
76 | */ | |
77 | declare_var_vector_reg msg_0,16 | |
78 | declare_var_vector_reg msg_1,17 | |
79 | declare_var_vector_reg msg_2,18 | |
80 | declare_var_vector_reg msg_3,19 | |
81 | /* | |
82 | Temporay variables | |
83 | */ | |
84 | declare_var_vector_reg tmp_0,5 | |
85 | declare_var_vector_reg tmp_1,6 | |
86 | ||
87 | /* | |
88 | void sha1_mb_ce_x1(SHA1_JOB * job, int len); | |
89 | */ | |
90 | /* | |
91 | Arguements list | |
92 | */ | |
93 | job .req x0 | |
94 | len .req w1 | |
95 | data .req x2 | |
96 | tmp .req x3 | |
97 | .global sha1_mb_ce_x1 | |
98 | .type sha1_mb_ce_x1, %function | |
99 | sha1_mb_ce_x1: | |
100 | ldr data, [job] | |
101 | ldr abcd_q, [job, 64] | |
102 | ldr e0_s, [job, 80] | |
103 | adr tmp, KEY | |
104 | ld1 {key_0_v.4s-key_3_v.4s},[tmp] | |
105 | ||
106 | start_loop: | |
107 | ||
108 | //load msgs | |
109 | ld1 {msg_0_v.4s-msg_3_v.4s},[data] | |
110 | ||
111 | //adjust loop parameter | |
112 | add data,data,64 | |
113 | sub len, len, #1 | |
114 | cmp len, 0 | |
115 | //backup digest | |
116 | mov abcd_saved_v.16b,abcd_v.16b | |
117 | mov e0_saved_v.16b,e0_v.16b | |
118 | ||
119 | rev32 msg_0_v.16b,msg_0_v.16b | |
120 | rev32 msg_1_v.16b,msg_1_v.16b | |
121 | add tmp_0_v.4s,msg_0_v.4s,key_0_v.4s | |
122 | rev32 msg_2_v.16b,msg_2_v.16b | |
123 | add tmp_1_v.4s,msg_1_v.4s,key_0_v.4s | |
124 | rev32 msg_3_v.16b,msg_3_v.16b | |
125 | ||
126 | /* rounds 0-3 */ | |
127 | sha1h e1_s,abcd_s | |
128 | sha1c abcd_q,e0_s,tmp_0_v.4s | |
129 | add tmp_0_v.4s,msg_2_v.4s,key_0_v.4s | |
130 | sha1su0 msg_0_v.4s,msg_1_v.4s,msg_2_v.4s | |
131 | ||
132 | sha1_4_rounds sha1c,msg_0,msg_1,msg_2,msg_3,abcd,e0,tmp_0,e1,tmp_1,key_0 /* rounds 4-7 */ | |
133 | sha1_4_rounds sha1c,msg_1,msg_2,msg_3,msg_0,abcd,e1,tmp_1,e0,tmp_0,key_0 | |
134 | sha1_4_rounds sha1c,msg_2,msg_3,msg_0,msg_1,abcd,e0,tmp_0,e1,tmp_1,key_1 /* rounds 12-15 */ | |
135 | sha1_4_rounds sha1c,msg_3,msg_0,msg_1,msg_2,abcd,e1,tmp_1,e0,tmp_0,key_1 | |
136 | sha1_4_rounds sha1p,msg_0,msg_1,msg_2,msg_3,abcd,e0,tmp_0,e1,tmp_1,key_1 /* rounds 20-23 */ | |
137 | sha1_4_rounds sha1p,msg_1,msg_2,msg_3,msg_0,abcd,e1,tmp_1,e0,tmp_0,key_1 | |
138 | sha1_4_rounds sha1p,msg_2,msg_3,msg_0,msg_1,abcd,e0,tmp_0,e1,tmp_1,key_1 | |
139 | sha1_4_rounds sha1p,msg_3,msg_0,msg_1,msg_2,abcd,e1,tmp_1,e0,tmp_0,key_2 | |
140 | sha1_4_rounds sha1p,msg_0,msg_1,msg_2,msg_3,abcd,e0,tmp_0,e1,tmp_1,key_2 /* rounds 36-39 */ | |
141 | sha1_4_rounds sha1m,msg_1,msg_2,msg_3,msg_0,abcd,e1,tmp_1,e0,tmp_0,key_2 | |
142 | sha1_4_rounds sha1m,msg_2,msg_3,msg_0,msg_1,abcd,e0,tmp_0,e1,tmp_1,key_2 | |
143 | sha1_4_rounds sha1m,msg_3,msg_0,msg_1,msg_2,abcd,e1,tmp_1,e0,tmp_0,key_2 | |
144 | sha1_4_rounds sha1m,msg_0,msg_1,msg_2,msg_3,abcd,e0,tmp_0,e1,tmp_1,key_3 /* rounds 52-55 */ | |
145 | sha1_4_rounds sha1m,msg_1,msg_2,msg_3,msg_0,abcd,e1,tmp_1,e0,tmp_0,key_3 | |
146 | sha1_4_rounds sha1p,msg_2,msg_3,msg_0,msg_1,abcd,e0,tmp_0,e1,tmp_1,key_3 | |
147 | sha1_4_rounds sha1p,msg_3,msg_0,msg_1,msg_2,abcd,e1,tmp_1,e0,tmp_0,key_3 | |
148 | ||
149 | /* rounds 68-71 */ | |
150 | sha1h e0_s,abcd_s | |
151 | sha1p abcd_q,e1_s,tmp_1_v.4s | |
152 | add tmp_1_v.4s,msg_3_v.4s,key_3_v.4s | |
153 | sha1su1 msg_0_v.4s,msg_3_v.4s | |
154 | ||
155 | /* rounds 72-75 */ | |
156 | sha1h e1_s,abcd_s | |
157 | sha1p abcd_q,e0_s,tmp_0_v.4s | |
158 | ||
159 | /* rounds 76-79 */ | |
160 | sha1h e0_s,abcd_s | |
161 | sha1p abcd_q,e1_s,tmp_1_v.4s | |
162 | ||
163 | ||
164 | ||
165 | add abcd_v.4s,abcd_v.4s,abcd_saved_v.4s | |
166 | add e0_v.2s,e0_v.2s,e0_saved_v.2s | |
167 | ||
168 | ||
169 | bgt start_loop | |
170 | str abcd_q, [job, 64] | |
171 | str e0_s, [job, 80] | |
172 | ||
173 | ret | |
174 | ||
175 | .size sha1_mb_ce_x1, .-sha1_mb_ce_x1 | |
176 | .section .rodata.cst16,"aM",@progbits,16 | |
177 | .align 4 | |
178 | KEY: | |
179 | .word 0x5a827999 | |
180 | .word 0x5a827999 | |
181 | .word 0x5a827999 | |
182 | .word 0x5a827999 | |
183 | .word 0x6ed9eba1 | |
184 | .word 0x6ed9eba1 | |
185 | .word 0x6ed9eba1 | |
186 | .word 0x6ed9eba1 | |
187 | .word 0x8f1bbcdc | |
188 | .word 0x8f1bbcdc | |
189 | .word 0x8f1bbcdc | |
190 | .word 0x8f1bbcdc | |
191 | .word 0xca62c1d6 | |
192 | .word 0xca62c1d6 | |
193 | .word 0xca62c1d6 | |
194 | .word 0xca62c1d6 |