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1 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
2 | ; Copyright(c) 2011-2017 Intel Corporation All rights reserved. | |
3 | ; | |
4 | ; Redistribution and use in source and binary forms, with or without | |
5 | ; modification, are permitted provided that the following conditions | |
6 | ; are met: | |
7 | ; * Redistributions of source code must retain the above copyright | |
8 | ; notice, this list of conditions and the following disclaimer. | |
9 | ; * Redistributions in binary form must reproduce the above copyright | |
10 | ; notice, this list of conditions and the following disclaimer in | |
11 | ; the documentation and/or other materials provided with the | |
12 | ; distribution. | |
13 | ; * Neither the name of Intel Corporation nor the names of its | |
14 | ; contributors may be used to endorse or promote products derived | |
15 | ; from this software without specific prior written permission. | |
16 | ; | |
17 | ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
18 | ; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
19 | ; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
20 | ; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
21 | ; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
22 | ; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
23 | ; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
24 | ; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
25 | ; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
26 | ; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
27 | ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
28 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | |
29 | ||
30 | %include "sha1_job.asm" | |
31 | %include "sha1_mb_mgr_datastruct.asm" | |
32 | ||
33 | %include "reg_sizes.asm" | |
34 | ||
35 | %ifdef HAVE_AS_KNOWS_SHANI | |
36 | extern sha1_mb_x4_sse | |
37 | extern sha1_ni_x1 | |
38 | ||
39 | [bits 64] | |
40 | default rel | |
41 | section .text | |
42 | ||
43 | %ifidn __OUTPUT_FORMAT__, elf64 | |
44 | ; LINUX register definitions | |
45 | %define arg1 rdi ; rcx | |
46 | %define arg2 rsi ; rdx | |
47 | ||
48 | ; idx needs to be other than ARG1, ARG2, rax, r8-r11 | |
49 | %define idx rdx ; rsi | |
50 | %else | |
51 | ; WINDOWS register definitions | |
52 | %define arg1 rcx | |
53 | %define arg2 rdx | |
54 | ||
55 | ; idx needs to be other than ARG1, ARG2, rax, r8-r11 | |
56 | %define idx rsi | |
57 | %endif | |
58 | ||
59 | ; Common definitions | |
60 | %define state arg1 | |
61 | %define job arg2 | |
62 | %define len2 arg2 | |
63 | ||
64 | %define unused_lanes rbx | |
65 | %define lane_data rbx | |
66 | %define tmp2 rbx | |
67 | ||
68 | %define job_rax rax | |
69 | %define tmp1 rax | |
70 | %define size_offset rax | |
71 | %define tmp rax | |
72 | %define start_offset rax | |
73 | ||
74 | %define tmp3 arg1 | |
75 | ||
76 | %define extra_blocks arg2 | |
77 | %define p arg2 | |
78 | ||
79 | %define tmp4 r8 | |
80 | %define lens0 r8 | |
81 | ||
82 | %define lens1 r9 | |
83 | %define lens2 r10 | |
84 | %define lens3 r11 | |
85 | ||
86 | ||
87 | ; STACK_SPACE needs to be an odd multiple of 8 | |
88 | _XMM_SAVE_SIZE equ 10*16 | |
89 | _GPR_SAVE_SIZE equ 8*2 | |
90 | _ALIGN_SIZE equ 8 | |
91 | ||
92 | _XMM_SAVE equ 0 | |
93 | _GPR_SAVE equ _XMM_SAVE + _XMM_SAVE_SIZE | |
94 | STACK_SPACE equ _GPR_SAVE + _GPR_SAVE_SIZE + _ALIGN_SIZE | |
95 | ||
96 | %define APPEND(a,b) a %+ b | |
97 | ||
98 | ; SHA1_JOB* sha1_mb_mgr_flush_sse_ni(SHA1_MB_JOB_MGR *state) | |
99 | ; arg 1 : rcx : state | |
100 | mk_global sha1_mb_mgr_flush_sse_ni, function | |
101 | sha1_mb_mgr_flush_sse_ni: | |
102 | endbranch | |
103 | ||
104 | sub rsp, STACK_SPACE | |
105 | mov [rsp + _GPR_SAVE + 8*0], rbx | |
106 | %ifidn __OUTPUT_FORMAT__, win64 | |
107 | mov [rsp + _GPR_SAVE + 8*1], rsi | |
108 | movdqa [rsp + _XMM_SAVE + 16*0], xmm6 | |
109 | movdqa [rsp + _XMM_SAVE + 16*1], xmm7 | |
110 | movdqa [rsp + _XMM_SAVE + 16*2], xmm8 | |
111 | movdqa [rsp + _XMM_SAVE + 16*3], xmm9 | |
112 | movdqa [rsp + _XMM_SAVE + 16*4], xmm10 | |
113 | movdqa [rsp + _XMM_SAVE + 16*5], xmm11 | |
114 | movdqa [rsp + _XMM_SAVE + 16*6], xmm12 | |
115 | movdqa [rsp + _XMM_SAVE + 16*7], xmm13 | |
116 | movdqa [rsp + _XMM_SAVE + 16*8], xmm14 | |
117 | movdqa [rsp + _XMM_SAVE + 16*9], xmm15 | |
118 | %endif | |
119 | ||
120 | ; use num_lanes_inuse to judge all lanes are empty | |
121 | cmp dword [state + _num_lanes_inuse], 0 | |
122 | jz return_null | |
123 | ||
124 | ; find a lane with a non-null job | |
125 | xor idx, idx | |
126 | cmp qword [state + _ldata + 1 * _LANE_DATA_size + _job_in_lane], 0 | |
127 | cmovne idx, [one] | |
128 | cmp qword [state + _ldata + 2 * _LANE_DATA_size + _job_in_lane], 0 | |
129 | cmovne idx, [two] | |
130 | cmp qword [state + _ldata + 3 * _LANE_DATA_size + _job_in_lane], 0 | |
131 | cmovne idx, [three] | |
132 | ||
133 | ; copy idx to empty lanes | |
134 | copy_lane_data: | |
135 | mov tmp, [state + _args + _data_ptr + 8*idx] | |
136 | ||
137 | %assign I 0 | |
138 | %rep 4 | |
139 | cmp qword [state + _ldata + I * _LANE_DATA_size + _job_in_lane], 0 | |
140 | jne APPEND(skip_,I) | |
141 | mov [state + _args + _data_ptr + 8*I], tmp | |
142 | mov dword [state + _lens + 4*I], 0xFFFFFFFF | |
143 | APPEND(skip_,I): | |
144 | %assign I (I+1) | |
145 | %endrep | |
146 | ||
147 | ; Find min length | |
148 | mov DWORD(lens0), [state + _lens + 0*4] | |
149 | mov idx, lens0 | |
150 | mov DWORD(lens1), [state + _lens + 1*4] | |
151 | cmp lens1, idx | |
152 | cmovb idx, lens1 | |
153 | mov DWORD(lens2), [state + _lens + 2*4] | |
154 | cmp lens2, idx | |
155 | cmovb idx, lens2 | |
156 | mov DWORD(lens3), [state + _lens + 3*4] | |
157 | cmp lens3, idx | |
158 | cmovb idx, lens3 | |
159 | mov len2, idx | |
160 | and idx, 0xF | |
161 | and len2, ~0xF | |
162 | jz len_is_0 | |
163 | ||
164 | ; compare with sha-sb threshold, if num_lanes_inuse <= threshold, using sb func | |
165 | cmp dword [state + _num_lanes_inuse], SHA1_NI_SB_THRESHOLD_SSE | |
166 | ja mb_processing | |
167 | ||
168 | ; lensN-len2=idx | |
169 | shr len2, 4 | |
170 | mov [state + _lens + idx*4], DWORD(idx) | |
171 | mov r10, idx | |
172 | or r10, 0x1000 ; sse has 4 lanes *4, r10b is idx, r10b2 is 16 | |
173 | ; "state" and "args" are the same address, arg1 | |
174 | ; len is arg2, idx and nlane in r10 | |
175 | call sha1_ni_x1 | |
176 | ; state and idx are intact | |
177 | jmp len_is_0 | |
178 | ||
179 | mb_processing: | |
180 | ||
181 | sub lens0, len2 | |
182 | sub lens1, len2 | |
183 | sub lens2, len2 | |
184 | sub lens3, len2 | |
185 | shr len2, 4 | |
186 | mov [state + _lens + 0*4], DWORD(lens0) | |
187 | mov [state + _lens + 1*4], DWORD(lens1) | |
188 | mov [state + _lens + 2*4], DWORD(lens2) | |
189 | mov [state + _lens + 3*4], DWORD(lens3) | |
190 | ||
191 | ; "state" and "args" are the same address, arg1 | |
192 | ; len is arg2 | |
193 | call sha1_mb_x4_sse | |
194 | ; state and idx are intact | |
195 | ||
196 | len_is_0: | |
197 | ; process completed job "idx" | |
198 | imul lane_data, idx, _LANE_DATA_size | |
199 | lea lane_data, [state + _ldata + lane_data] | |
200 | ||
201 | mov job_rax, [lane_data + _job_in_lane] | |
202 | mov qword [lane_data + _job_in_lane], 0 | |
203 | mov dword [job_rax + _status], STS_COMPLETED | |
204 | mov unused_lanes, [state + _unused_lanes] | |
205 | shl unused_lanes, 4 | |
206 | or unused_lanes, idx | |
207 | mov [state + _unused_lanes], unused_lanes | |
208 | ||
209 | sub dword [state + _num_lanes_inuse], 1 | |
210 | ||
211 | movd xmm0, [state + _args_digest + 4*idx + 0*16] | |
212 | pinsrd xmm0, [state + _args_digest + 4*idx + 1*16], 1 | |
213 | pinsrd xmm0, [state + _args_digest + 4*idx + 2*16], 2 | |
214 | pinsrd xmm0, [state + _args_digest + 4*idx + 3*16], 3 | |
215 | mov DWORD(tmp2), [state + _args_digest + 4*idx + 4*16] | |
216 | ||
217 | movdqa [job_rax + _result_digest + 0*16], xmm0 | |
218 | mov [job_rax + _result_digest + 1*16], DWORD(tmp2) | |
219 | ||
220 | return: | |
221 | ||
222 | %ifidn __OUTPUT_FORMAT__, win64 | |
223 | movdqa xmm6, [rsp + _XMM_SAVE + 16*0] | |
224 | movdqa xmm7, [rsp + _XMM_SAVE + 16*1] | |
225 | movdqa xmm8, [rsp + _XMM_SAVE + 16*2] | |
226 | movdqa xmm9, [rsp + _XMM_SAVE + 16*3] | |
227 | movdqa xmm10, [rsp + _XMM_SAVE + 16*4] | |
228 | movdqa xmm11, [rsp + _XMM_SAVE + 16*5] | |
229 | movdqa xmm12, [rsp + _XMM_SAVE + 16*6] | |
230 | movdqa xmm13, [rsp + _XMM_SAVE + 16*7] | |
231 | movdqa xmm14, [rsp + _XMM_SAVE + 16*8] | |
232 | movdqa xmm15, [rsp + _XMM_SAVE + 16*9] | |
233 | mov rsi, [rsp + _GPR_SAVE + 8*1] | |
234 | %endif | |
235 | mov rbx, [rsp + _GPR_SAVE + 8*0] | |
236 | add rsp, STACK_SPACE | |
237 | ||
238 | ret | |
239 | ||
240 | return_null: | |
241 | xor job_rax, job_rax | |
242 | jmp return | |
243 | ||
244 | section .data align=16 | |
245 | ||
246 | align 16 | |
247 | one: dq 1 | |
248 | two: dq 2 | |
249 | three: dq 3 | |
250 | ||
251 | %else | |
252 | %ifidn __OUTPUT_FORMAT__, win64 | |
253 | global no_sha1_mb_mgr_flush_sse_ni | |
254 | no_sha1_mb_mgr_flush_sse_ni: | |
255 | %endif | |
256 | %endif ; HAVE_AS_KNOWS_SHANI |