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1;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2; Copyright(c) 2011-2017 Intel Corporation All rights reserved.
3;
4; Redistribution and use in source and binary forms, with or without
5; modification, are permitted provided that the following conditions
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7; * Redistributions of source code must retain the above copyright
8; notice, this list of conditions and the following disclaimer.
9; * Redistributions in binary form must reproduce the above copyright
10; notice, this list of conditions and the following disclaimer in
11; the documentation and/or other materials provided with the
12; distribution.
13; * Neither the name of Intel Corporation nor the names of its
14; contributors may be used to endorse or promote products derived
15; from this software without specific prior written permission.
16;
17; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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27; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
29
30%include "sha256_job.asm"
31%include "sha256_mb_mgr_datastruct.asm"
32
33%include "reg_sizes.asm"
34
35%ifdef HAVE_AS_KNOWS_SHANI
36extern sha256_mb_x4_sse
37extern sha256_ni_x1
38
39[bits 64]
40default rel
41section .text
42
43%ifidn __OUTPUT_FORMAT__, elf64
44; LINUX register definitions
45%define arg1 rdi ; rcx
46%define arg2 rsi ; rdx
47
48; idx needs to be other than arg1, arg2, rbx, r12
49%define idx rdx ; rsi
50%else
51; WINDOWS register definitions
52%define arg1 rcx
53%define arg2 rdx
54
55; idx needs to be other than arg1, arg2, rbx, r12
56%define idx rsi
57%endif
58
59; Common definitions
60%define state arg1
61%define job arg2
62%define len2 arg2
63
64%define unused_lanes rbx
65%define lane_data rbx
66%define tmp2 rbx
67
68%define job_rax rax
69%define tmp1 rax
70%define size_offset rax
71%define tmp rax
72%define start_offset rax
73
74%define tmp3 arg1
75
76%define extra_blocks arg2
77%define p arg2
78
79%define tmp4 r8
80%define lens0 r8
81
82%define lens1 r9
83%define lens2 r10
84%define lens3 r11
85
86
87; STACK_SPACE needs to be an odd multiple of 8
88_XMM_SAVE_SIZE equ 10*16
89_GPR_SAVE_SIZE equ 8*3
90_ALIGN_SIZE equ 0
91
92_XMM_SAVE equ 0
93_GPR_SAVE equ _XMM_SAVE + _XMM_SAVE_SIZE
94STACK_SPACE equ _GPR_SAVE + _GPR_SAVE_SIZE + _ALIGN_SIZE
95
96%define APPEND(a,b) a %+ b
97
98; SHA256_JOB* sha256_mb_mgr_flush_sse_ni(SHA256_MB_JOB_MGR *state)
99; arg 1 : rcx : state
100mk_global sha256_mb_mgr_flush_sse_ni, function
101sha256_mb_mgr_flush_sse_ni:
102 endbranch
103
104 sub rsp, STACK_SPACE
105 mov [rsp + _GPR_SAVE + 8*0], rbx
106 mov [rsp + _GPR_SAVE + 8*1], r12
107%ifidn __OUTPUT_FORMAT__, win64
108 mov [rsp + _GPR_SAVE + 8*2], rsi
109 movdqa [rsp + _XMM_SAVE + 16*0], xmm6
110 movdqa [rsp + _XMM_SAVE + 16*1], xmm7
111 movdqa [rsp + _XMM_SAVE + 16*2], xmm8
112 movdqa [rsp + _XMM_SAVE + 16*3], xmm9
113 movdqa [rsp + _XMM_SAVE + 16*4], xmm10
114 movdqa [rsp + _XMM_SAVE + 16*5], xmm11
115 movdqa [rsp + _XMM_SAVE + 16*6], xmm12
116 movdqa [rsp + _XMM_SAVE + 16*7], xmm13
117 movdqa [rsp + _XMM_SAVE + 16*8], xmm14
118 movdqa [rsp + _XMM_SAVE + 16*9], xmm15
119%endif
120
121 ; use num_lanes_inuse to judge all lanes are empty
122 cmp dword [state + _num_lanes_inuse], 0
123 jz return_null
124
125 ; find a lane with a non-null job
126 xor idx, idx
127 cmp qword [state + _ldata + 1 * _LANE_DATA_size + _job_in_lane], 0
128 cmovne idx, [one]
129 cmp qword [state + _ldata + 2 * _LANE_DATA_size + _job_in_lane], 0
130 cmovne idx, [two]
131 cmp qword [state + _ldata + 3 * _LANE_DATA_size + _job_in_lane], 0
132 cmovne idx, [three]
133
134 ; copy idx to empty lanes
135copy_lane_data:
136 mov tmp, [state + _args + _data_ptr + 8*idx]
137
138%assign I 0
139%rep 4
140 cmp qword [state + _ldata + I * _LANE_DATA_size + _job_in_lane], 0
141 jne APPEND(skip_,I)
142 mov [state + _args + _data_ptr + 8*I], tmp
143 mov dword [state + _lens + 4*I], 0xFFFFFFFF
144APPEND(skip_,I):
145%assign I (I+1)
146%endrep
147
148 ; Find min length
149 mov DWORD(lens0), [state + _lens + 0*4]
150 mov idx, lens0
151 mov DWORD(lens1), [state + _lens + 1*4]
152 cmp lens1, idx
153 cmovb idx, lens1
154 mov DWORD(lens2), [state + _lens + 2*4]
155 cmp lens2, idx
156 cmovb idx, lens2
157 mov DWORD(lens3), [state + _lens + 3*4]
158 cmp lens3, idx
159 cmovb idx, lens3
160 mov len2, idx
161 and idx, 0xF
162 and len2, ~0xF
163 jz len_is_0
164
165 ; compare with shani-sb threshold, if num_lanes_inuse <= threshold, using shani func
166 cmp dword [state + _num_lanes_inuse], SHA256_NI_SB_THRESHOLD_SSE
167 ja mb_processing
168
169 ; lensN-len2=idx
170 shr len2, 4
171 mov [state + _lens + idx*4], DWORD(idx)
172 mov r10, idx
173 or r10, 0x1000 ; sse has 4 lanes *4, r10b is idx, r10b2 is 16
174 ; "state" and "args" are the same address, arg1
175 ; len is arg2, idx and nlane in r10
176 call sha256_ni_x1
177 ; state and idx are intact
178 jmp len_is_0
179
180mb_processing:
181
182 sub lens0, len2
183 sub lens1, len2
184 sub lens2, len2
185 sub lens3, len2
186 shr len2, 4
187 mov [state + _lens + 0*4], DWORD(lens0)
188 mov [state + _lens + 1*4], DWORD(lens1)
189 mov [state + _lens + 2*4], DWORD(lens2)
190 mov [state + _lens + 3*4], DWORD(lens3)
191
192 ; "state" and "args" are the same address, arg1
193 ; len is arg2
194 call sha256_mb_x4_sse
195 ; state and idx are intact
196
197len_is_0:
198 ; process completed job "idx"
199 imul lane_data, idx, _LANE_DATA_size
200 lea lane_data, [state + _ldata + lane_data]
201
202 mov job_rax, [lane_data + _job_in_lane]
203 mov qword [lane_data + _job_in_lane], 0
204 mov dword [job_rax + _status], STS_COMPLETED
205 mov unused_lanes, [state + _unused_lanes]
206 shl unused_lanes, 4
207 or unused_lanes, idx
208 mov [state + _unused_lanes], unused_lanes
209
210 sub dword [state + _num_lanes_inuse], 1
211
212 movd xmm0, [state + _args_digest + 4*idx + 0*16]
213 pinsrd xmm0, [state + _args_digest + 4*idx + 1*16], 1
214 pinsrd xmm0, [state + _args_digest + 4*idx + 2*16], 2
215 pinsrd xmm0, [state + _args_digest + 4*idx + 3*16], 3
216 movd xmm1, [state + _args_digest + 4*idx + 4*16]
217 pinsrd xmm1, [state + _args_digest + 4*idx + 5*16], 1
218 pinsrd xmm1, [state + _args_digest + 4*idx + 6*16], 2
219 pinsrd xmm1, [state + _args_digest + 4*idx + 7*16], 3
220
221 movdqa [job_rax + _result_digest + 0*16], xmm0
222 movdqa [job_rax + _result_digest + 1*16], xmm1
223
224return:
225
226%ifidn __OUTPUT_FORMAT__, win64
227 movdqa xmm6, [rsp + _XMM_SAVE + 16*0]
228 movdqa xmm7, [rsp + _XMM_SAVE + 16*1]
229 movdqa xmm8, [rsp + _XMM_SAVE + 16*2]
230 movdqa xmm9, [rsp + _XMM_SAVE + 16*3]
231 movdqa xmm10, [rsp + _XMM_SAVE + 16*4]
232 movdqa xmm11, [rsp + _XMM_SAVE + 16*5]
233 movdqa xmm12, [rsp + _XMM_SAVE + 16*6]
234 movdqa xmm13, [rsp + _XMM_SAVE + 16*7]
235 movdqa xmm14, [rsp + _XMM_SAVE + 16*8]
236 movdqa xmm15, [rsp + _XMM_SAVE + 16*9]
237 mov rsi, [rsp + _GPR_SAVE + 8*2]
238%endif
239 mov rbx, [rsp + _GPR_SAVE + 8*0]
240 mov r12, [rsp + _GPR_SAVE + 8*1]
241 add rsp, STACK_SPACE
242
243 ret
244
245return_null:
246 xor job_rax, job_rax
247 jmp return
248
249section .data align=16
250
251align 16
252one: dq 1
253two: dq 2
254three: dq 3
255
256%else
257 %ifidn __OUTPUT_FORMAT__, win64
258 global no_sha256_mb_mgr_flush_sse_ni
259 no_sha256_mb_mgr_flush_sse_ni:
260 %endif
261%endif ; HAVE_AS_KNOWS_SHANI