1 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2 ; Copyright(c) 2011-2015 Intel Corporation All rights reserved.
4 ; Redistribution and use in source and binary forms, with or without
5 ; modification, are permitted provided that the following conditions
7 ; * Redistributions of source code must retain the above copyright
8 ; notice, this list of conditions and the following disclaimer.
9 ; * Redistributions in binary form must reproduce the above copyright
10 ; notice, this list of conditions and the following disclaimer in
11 ; the documentation and/or other materials provided with the
13 ; * Neither the name of Intel Corporation nor the names of its
14 ; contributors may be used to endorse or promote products derived
15 ; from this software without specific prior written permission.
17 ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 ; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 ; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 ; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 ; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 ; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 ; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 ; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 ; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 ; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
31 ;;; gf_5vect_dot_prod_avx2(len, vec, *g_tbls, **buffs, **dests);
34 %include "reg_sizes.asm"
36 %ifidn __OUTPUT_FORMAT__, elf64
48 %define tmp3 r13 ; must be saved and restored
49 %define tmp4 r12 ; must be saved and restored
50 %define tmp5 r14 ; must be saved and restored
51 %define tmp6 r15 ; must be saved and restored
71 %ifidn __OUTPUT_FORMAT__, win64
77 %define arg4 r12 ; must be saved, loaded and restored
78 %define arg5 r15 ; must be saved and restored
83 %define tmp3 r13 ; must be saved and restored
84 %define tmp4 r14 ; must be saved and restored
85 %define tmp5 rdi ; must be saved and restored
86 %define tmp6 rsi ; must be saved and restored
90 %define stack_size 10*16 + 7*8 ; must be an odd multiple of 8
91 %define arg(x) [rsp + stack_size + PS + PS*x]
93 %define func(x) proc_frame x
95 alloc_stack stack_size
96 vmovdqa [rsp + 0*16], xmm6
97 vmovdqa [rsp + 1*16], xmm7
98 vmovdqa [rsp + 2*16], xmm8
99 vmovdqa [rsp + 3*16], xmm9
100 vmovdqa [rsp + 4*16], xmm10
101 vmovdqa [rsp + 5*16], xmm11
102 vmovdqa [rsp + 6*16], xmm12
103 vmovdqa [rsp + 7*16], xmm13
104 vmovdqa [rsp + 8*16], xmm14
105 vmovdqa [rsp + 9*16], xmm15
106 save_reg r12, 10*16 + 0*8
107 save_reg r13, 10*16 + 1*8
108 save_reg r14, 10*16 + 2*8
109 save_reg r15, 10*16 + 3*8
110 save_reg rdi, 10*16 + 4*8
111 save_reg rsi, 10*16 + 5*8
116 %macro FUNC_RESTORE 0
117 vmovdqa xmm6, [rsp + 0*16]
118 vmovdqa xmm7, [rsp + 1*16]
119 vmovdqa xmm8, [rsp + 2*16]
120 vmovdqa xmm9, [rsp + 3*16]
121 vmovdqa xmm10, [rsp + 4*16]
122 vmovdqa xmm11, [rsp + 5*16]
123 vmovdqa xmm12, [rsp + 6*16]
124 vmovdqa xmm13, [rsp + 7*16]
125 vmovdqa xmm14, [rsp + 8*16]
126 vmovdqa xmm15, [rsp + 9*16]
127 mov r12, [rsp + 10*16 + 0*8]
128 mov r13, [rsp + 10*16 + 1*8]
129 mov r14, [rsp + 10*16 + 2*8]
130 mov r15, [rsp + 10*16 + 3*8]
131 mov rdi, [rsp + 10*16 + 4*8]
132 mov rsi, [rsp + 10*16 + 5*8]
139 %define mul_array arg2
151 %ifndef EC_ALIGNED_ADDR
152 ;;; Use Un-aligned load/store
156 ;;; Use Non-temporal load/stor
161 %define XLDR vmovntdqa
162 %define XSTR vmovntdq
171 %define xmask0f ymm15
172 %define xmask0fx xmm15
173 %define xgft1_lo ymm14
174 %define xgft1_hi ymm13
175 %define xgft2_lo ymm12
176 %define xgft2_hi ymm11
177 %define xgft3_lo ymm10
178 %define xgft3_hi ymm9
179 %define xgft4_lo ymm8
180 %define xgft4_hi ymm7
192 global gf_5vect_dot_prod_avx2:function
193 func(gf_5vect_dot_prod_avx2)
199 vpinsrb xmask0fx, xmask0fx, tmp.w, 0
200 vpbroadcastb xmask0f, xmask0fx ;Construct mask 0x0f0f0f...
205 sal vec, LOG_PS ;vec *= PS. Make vec_i count by PS
222 XLDR x0, [ptr+pos] ;Get next source vector
225 vpand xgft4_lo, x0, xmask0f ;Mask low src nibble in bits 4-0
226 vpsraw x0, x0, 4 ;Shift to put high nibble into bits 4-0
227 vpand x0, x0, xmask0f ;Mask high src nibble in bits 4-0
228 vperm2i128 xtmpa, xgft4_lo, x0, 0x30 ;swap xtmpa from 1lo|2lo to 1lo|2hi
229 vperm2i128 x0, xgft4_lo, x0, 0x12 ;swap x0 from 1hi|2hi to 1hi|2lo
231 vmovdqu xgft1_lo, [tmp] ;Load array Ax{00}, Ax{01}, ..., Ax{0f}
232 ; " Ax{00}, Ax{10}, ..., Ax{f0}
233 vmovdqu xgft2_lo, [tmp+vskip1*1] ;Load array Bx{00}, Bx{01}, ..., Bx{0f}
234 ; " Bx{00}, Bx{10}, ..., Bx{f0}
235 vmovdqu xgft3_lo, [tmp+vskip1*2] ;Load array Cx{00}, Cx{01}, ..., Cx{0f}
236 ; " Cx{00}, Cx{10}, ..., Cx{f0}
237 vmovdqu xgft4_lo, [tmp+vskip3] ;Load array Dx{00}, Dx{01}, ..., Dx{0f}
238 ; " Dx{00}, Dx{10}, ..., Dx{f0}
240 vperm2i128 xgft1_hi, xgft1_lo, xgft1_lo, 0x01 ; swapped to hi | lo
241 vperm2i128 xgft2_hi, xgft2_lo, xgft2_lo, 0x01 ; swapped to hi | lo
242 vperm2i128 xgft3_hi, xgft3_lo, xgft3_lo, 0x01 ; swapped to hi | lo
243 vperm2i128 xgft4_hi, xgft4_lo, xgft4_lo, 0x01 ; swapped to hi | lo
245 vpshufb xgft1_hi, x0 ;Lookup mul table of high nibble
246 vpshufb xgft1_lo, xtmpa ;Lookup mul table of low nibble
247 vpxor xgft1_hi, xgft1_lo ;GF add high and low partials
248 vpxor xp1, xgft1_hi ;xp1 += partial
250 vpshufb xgft2_hi, x0 ;Lookup mul table of high nibble
251 vpshufb xgft2_lo, xtmpa ;Lookup mul table of low nibble
252 vpxor xgft2_hi, xgft2_lo ;GF add high and low partials
253 vpxor xp2, xgft2_hi ;xp2 += partial
255 vmovdqu xgft1_lo, [tmp+vskip1*4] ;Load array Ex{00}, Ex{01}, ..., Ex{0f}
256 ; " Ex{00}, Ex{10}, ..., Ex{f0}
257 vperm2i128 xgft1_hi, xgft1_lo, xgft1_lo, 0x01 ; swapped to hi | lo
260 vpshufb xgft3_hi, x0 ;Lookup mul table of high nibble
261 vpshufb xgft3_lo, xtmpa ;Lookup mul table of low nibble
262 vpxor xgft3_hi, xgft3_lo ;GF add high and low partials
263 vpxor xp3, xgft3_hi ;xp3 += partial
265 vpshufb xgft4_hi, x0 ;Lookup mul table of high nibble
266 vpshufb xgft4_lo, xtmpa ;Lookup mul table of low nibble
267 vpxor xgft4_hi, xgft4_lo ;GF add high and low partials
268 vpxor xp4, xgft4_hi ;xp4 += partial
270 vpshufb xgft1_hi, x0 ;Lookup mul table of high nibble
271 vpshufb xgft1_lo, xtmpa ;Lookup mul table of low nibble
272 vpxor xgft1_hi, xgft1_lo ;GF add high and low partials
273 vpxor xp5, xgft1_hi ;xp5 += partial
280 mov vec_i, [dest+4*PS]
282 XSTR [dest1+pos], xp1
283 XSTR [dest2+pos], xp2
286 XSTR [vec_i+pos], xp5
288 add pos, 32 ;Loop on 32 bytes at a time
297 mov pos, len ;Overlapped offset length-16
298 jmp .loop32 ;Do one more overlap pass
314 ;;; func core, ver, snum
315 slversion gf_5vect_dot_prod_avx2, 04, 04, 0199