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31 ;;; gf_2vect_mad_avx512(len, vec, vec_i, mul_array, src, dest);
34 %include "reg_sizes.asm"
36 %ifdef HAVE_AS_KNOWS_AVX512
38 %ifidn __OUTPUT_FORMAT__, elf64
53 %ifidn __OUTPUT_FORMAT__, win64
63 %define stack_size 16*9 + 3*8 ; must be an odd multiple of 8
64 %define arg(x) [rsp + stack_size + PS + PS*x]
66 %define func(x) proc_frame x
69 vmovdqa [rsp+16*0],xmm6
70 vmovdqa [rsp+16*1],xmm7
71 vmovdqa [rsp+16*2],xmm8
72 vmovdqa [rsp+16*3],xmm9
73 vmovdqa [rsp+16*4],xmm10
74 vmovdqa [rsp+16*5],xmm11
75 vmovdqa [rsp+16*6],xmm12
76 vmovdqa [rsp+16*7],xmm13
77 vmovdqa [rsp+16*8],xmm14
78 save_reg r12, 9*16 + 0*8
79 save_reg r15, 9*16 + 1*8
86 vmovdqa xmm6, [rsp+16*0]
87 vmovdqa xmm7, [rsp+16*1]
88 vmovdqa xmm8, [rsp+16*2]
89 vmovdqa xmm9, [rsp+16*3]
90 vmovdqa xmm10, [rsp+16*4]
91 vmovdqa xmm11, [rsp+16*5]
92 vmovdqa xmm12, [rsp+16*6]
93 vmovdqa xmm13, [rsp+16*7]
94 vmovdqa xmm14, [rsp+16*8]
95 mov r12, [rsp + 9*16 + 0*8]
96 mov r15, [rsp + 9*16 + 1*8]
107 %define mul_array arg3
111 %define pos.w return.w
114 %ifndef EC_ALIGNED_ADDR
115 ;;; Use Un-aligned load/store
116 %define XLDR vmovdqu8
117 %define XSTR vmovdqu8
119 ;;; Use Non-temporal load/stor
124 %define XLDR vmovntdqa
125 %define XSTR vmovntdq
143 %define xgft1_hi zmm10
144 %define xgft1_lo zmm11
145 %define xgft1_loy ymm11
146 %define xgft2_hi zmm12
147 %define xgft2_lo zmm13
148 %define xgft2_loy ymm13
149 %define xmask0f zmm14
152 global gf_2vect_mad_avx512:ISAL_SYM_TYPE_FUNCTION
153 func(gf_2vect_mad_avx512)
159 vpbroadcastb xmask0f, tmp ;Construct mask 0x0f0f0f...
160 sal vec_i, 5 ;Multiply by 32
162 lea tmp, [mul_array + vec_i]
163 vmovdqu xgft1_loy, [tmp] ;Load array Ax{00}..{0f}, Ax{00}..{f0}
164 vmovdqu xgft2_loy, [tmp+vec] ;Load array Bx{00}..{0f}, Bx{00}..{f0}
165 vshufi64x2 xgft1_hi, xgft1_lo, xgft1_lo, 0x55
166 vshufi64x2 xgft1_lo, xgft1_lo, xgft1_lo, 0x00
167 vshufi64x2 xgft2_hi, xgft2_lo, xgft2_lo, 0x55
168 vshufi64x2 xgft2_lo, xgft2_lo, xgft2_lo, 0x00
169 mov dest2, [dest1+PS] ; reuse mul_array
175 XLDR xd1, [dest1+pos] ;Get next dest vector
176 XLDR xd2, [dest2+pos] ;Get next dest vector
177 XLDR x0, [src+pos] ;Get next source vector
179 vpandq xtmpa, x0, xmask0f ;Mask low src nibble in bits 4-0
180 vpsraw x0, x0, 4 ;Shift to put high nibble into bits 4-0
181 vpandq x0, x0, xmask0f ;Mask high src nibble in bits 4-0
183 vpshufb xtmph1 {k1}{z}, xgft1_hi, x0 ;Lookup mul table of high nibble
184 vpshufb xtmpl1 {k1}{z}, xgft1_lo, xtmpa ;Lookup mul table of low nibble
185 vpxorq xtmph1, xtmph1, xtmpl1 ;GF add high and low partials
186 vpxorq xd1, xd1, xtmph1 ;xd1 += partial
188 vpshufb xtmph2 {k1}{z}, xgft2_hi, x0 ;Lookup mul table of high nibble
189 vpshufb xtmpl2 {k1}{z}, xgft2_lo, xtmpa ;Lookup mul table of low nibble
190 vpxorq xtmph2, xtmph2, xtmpl2 ;GF add high and low partials
191 vpxorq xd2, xd2, xtmph2 ;xd2 += partial
193 XSTR [dest1+pos], xd1
194 XSTR [dest2+pos], xd2
196 add pos, 64 ;Loop on 64 bytes at a time
206 lea tmp, [len + 64 - 1]
210 mov pos, len ;Overlapped offset length-64
211 jmp .loop64 ;Do one more overlap pass
226 %ifidn __OUTPUT_FORMAT__, win64
227 global no_gf_2vect_mad_avx512
228 no_gf_2vect_mad_avx512:
230 %endif ; ifdef HAVE_AS_KNOWS_AVX512