ceph/src/isa-l/igzip/igzip_multibinary.asm

   1 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
   2 ;  Copyright(c) 2011-2016 Intel Corporation All rights reserved.
   3 ;
   4 ;  Redistribution and use in source and binary forms, with or without
   5 ;  modification, are permitted provided that the following conditions
   6 ;  are met:
   7 ;    * Redistributions of source code must retain the above copyright
   8 ;      notice, this list of conditions and the following disclaimer.
   9 ;    * Redistributions in binary form must reproduce the above copyright
  10 ;      notice, this list of conditions and the following disclaimer in
  11 ;      the documentation and/or other materials provided with the
  12 ;      distribution.
  13 ;    * Neither the name of Intel Corporation nor the names of its
  14 ;      contributors may be used to endorse or promote products derived
  15 ;      from this software without specific prior written permission.
  16 ;
  17 ;  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18 ;  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19 ;  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20 ;  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21 ;  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22 ;  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23 ;  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24 ;  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25 ;  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26 ;  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27 ;  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  29
  30 default rel
  31 [bits 64]
  32
  33 %ifidn __OUTPUT_FORMAT__, elf64
  34 %define WRT_OPT         wrt ..plt
  35 %else
  36 %define WRT_OPT
  37 %endif
  38
  39 %include "reg_sizes.asm"
  40
  41 extern isal_deflate_body_stateless_base
  42 extern isal_deflate_body_stateless_01
  43 extern isal_deflate_body_stateless_04
  44
  45 extern isal_deflate_body_base
  46 extern isal_deflate_body_01
  47 extern isal_deflate_body_04
  48 extern isal_deflate_finish_base
  49 extern isal_deflate_finish_01
  50
  51 extern get_crc_base
  52 extern get_crc_01
  53
  54 extern isal_deflate_init_base
  55 extern isal_deflate_init_01
  56
  57 section .text
  58
  59 %include "multibinary.asm"
  60
  61 mbin_interface          isal_deflate_init
  62 mbin_dispatch_init5     isal_deflate_init, isal_deflate_init_base, isal_deflate_init_01, isal_deflate_init_01, isal_deflate_init_01
  63
  64 mbin_interface          isal_deflate_body_stateless
  65 mbin_dispatch_init5     isal_deflate_body_stateless, isal_deflate_body_stateless_base, isal_deflate_body_stateless_01, isal_deflate_body_stateless_01, isal_deflate_body_stateless_04
  66
  67 mbin_interface          isal_deflate_body
  68 mbin_dispatch_init5     isal_deflate_body, isal_deflate_body_base, isal_deflate_body_01, isal_deflate_body_01, isal_deflate_body_04
  69 mbin_interface          isal_deflate_finish
  70 mbin_dispatch_init5     isal_deflate_finish, isal_deflate_finish_base, isal_deflate_finish_01, isal_deflate_finish_01, isal_deflate_finish_01
  71
  72 mbin_interface          get_crc
  73 mbin_dispatch_init5     get_crc, get_crc_base, get_crc_01, get_crc_01, get_crc_01