ceph/src/seastar/dpdk/drivers/net/axgbe/axgbe_ethdev.h

   1 /*   SPDX-License-Identifier: BSD-3-Clause
   2  *   Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved.
   3  *   Copyright(c) 2018 Synopsys, Inc. All rights reserved.
   4  */
   5
   6 #ifndef RTE_ETH_AXGBE_H_
   7 #define RTE_ETH_AXGBE_H_
   8
   9 #include <rte_mempool.h>
  10 #include <rte_lcore.h>
  11 #include "axgbe_common.h"
  12
  13 #define IRQ                             0xff
  14 #define VLAN_HLEN                       4
  15
  16 #define AXGBE_TX_MAX_BUF_SIZE           (0x3fff & ~(64 - 1))
  17 #define AXGBE_RX_MAX_BUF_SIZE           (0x3fff & ~(64 - 1))
  18 #define AXGBE_RX_MIN_BUF_SIZE           (ETHER_MAX_LEN + VLAN_HLEN)
  19 #define AXGBE_MAX_MAC_ADDRS             1
  20
  21 #define AXGBE_RX_BUF_ALIGN              64
  22
  23 #define AXGBE_MAX_DMA_CHANNELS          16
  24 #define AXGBE_MAX_QUEUES                16
  25 #define AXGBE_PRIORITY_QUEUES           8
  26 #define AXGBE_DMA_STOP_TIMEOUT          1
  27
  28 /* DMA cache settings - Outer sharable, write-back, write-allocate */
  29 #define AXGBE_DMA_OS_AXDOMAIN           0x2
  30 #define AXGBE_DMA_OS_ARCACHE            0xb
  31 #define AXGBE_DMA_OS_AWCACHE            0xf
  32
  33 /* DMA cache settings - System, no caches used */
  34 #define AXGBE_DMA_SYS_AXDOMAIN          0x3
  35 #define AXGBE_DMA_SYS_ARCACHE           0x0
  36 #define AXGBE_DMA_SYS_AWCACHE           0x0
  37
  38 /* DMA channel interrupt modes */
  39 #define AXGBE_IRQ_MODE_EDGE             0
  40 #define AXGBE_IRQ_MODE_LEVEL            1
  41
  42 #define AXGBE_DMA_INTERRUPT_MASK        0x31c7
  43
  44 #define AXGMAC_MIN_PACKET               60
  45 #define AXGMAC_STD_PACKET_MTU           1500
  46 #define AXGMAC_MAX_STD_PACKET           1518
  47 #define AXGMAC_JUMBO_PACKET_MTU         9000
  48 #define AXGMAC_MAX_JUMBO_PACKET         9018
  49 /* Inter-frame gap + preamble */
  50 #define AXGMAC_ETH_PREAMBLE             (12 + 8)
  51
  52 #define AXGMAC_PFC_DATA_LEN             46
  53 #define AXGMAC_PFC_DELAYS               14000
  54
  55 /* PCI BAR mapping */
  56 #define AXGBE_AXGMAC_BAR                0
  57 #define AXGBE_XPCS_BAR                  1
  58 #define AXGBE_MAC_PROP_OFFSET           0x1d000
  59 #define AXGBE_I2C_CTRL_OFFSET           0x1e000
  60
  61 /* PCI clock frequencies */
  62 #define AXGBE_V2_DMA_CLOCK_FREQ         500000000
  63 #define AXGBE_V2_PTP_CLOCK_FREQ         125000000
  64
  65 #define AXGMAC_FIFO_MIN_ALLOC           2048
  66 #define AXGMAC_FIFO_UNIT                256
  67 #define AXGMAC_FIFO_ALIGN(_x)                            \
  68         (((_x) + AXGMAC_FIFO_UNIT - 1) & ~(XGMAC_FIFO_UNIT - 1))
  69 #define AXGMAC_FIFO_FC_OFF              2048
  70 #define AXGMAC_FIFO_FC_MIN              4096
  71
  72 #define AXGBE_TC_MIN_QUANTUM            10
  73
  74 /* Flow control queue count */
  75 #define AXGMAC_MAX_FLOW_CONTROL_QUEUES  8
  76
  77 /* Flow control threshold units */
  78 #define AXGMAC_FLOW_CONTROL_UNIT        512
  79 #define AXGMAC_FLOW_CONTROL_ALIGN(_x)                           \
  80         (((_x) + AXGMAC_FLOW_CONTROL_UNIT - 1) &                \
  81         ~(AXGMAC_FLOW_CONTROL_UNIT - 1))
  82 #define AXGMAC_FLOW_CONTROL_VALUE(_x)                           \
  83         (((_x) < 1024) ? 0 : ((_x) / AXGMAC_FLOW_CONTROL_UNIT) - 2)
  84 #define AXGMAC_FLOW_CONTROL_MAX         33280
  85
  86 /* Maximum MAC address hash table size (256 bits = 8 bytes) */
  87 #define AXGBE_MAC_HASH_TABLE_SIZE       8
  88
  89 /* Receive Side Scaling */
  90 #define AXGBE_RSS_OFFLOAD  ( \
  91         ETH_RSS_IPV4 | \
  92         ETH_RSS_NONFRAG_IPV4_TCP | \
  93         ETH_RSS_NONFRAG_IPV4_UDP | \
  94         ETH_RSS_IPV6 | \
  95         ETH_RSS_NONFRAG_IPV6_TCP | \
  96         ETH_RSS_NONFRAG_IPV6_UDP)
  97
  98 #define AXGBE_RSS_HASH_KEY_SIZE         40
  99 #define AXGBE_RSS_MAX_TABLE_SIZE        256
 100 #define AXGBE_RSS_LOOKUP_TABLE_TYPE     0
 101 #define AXGBE_RSS_HASH_KEY_TYPE         1
 102
 103 /* Auto-negotiation */
 104 #define AXGBE_AN_MS_TIMEOUT             500
 105 #define AXGBE_LINK_TIMEOUT              5
 106
 107 #define AXGBE_SGMII_AN_LINK_STATUS      BIT(1)
 108 #define AXGBE_SGMII_AN_LINK_SPEED       (BIT(2) | BIT(3))
 109 #define AXGBE_SGMII_AN_LINK_SPEED_100   0x04
 110 #define AXGBE_SGMII_AN_LINK_SPEED_1000  0x08
 111 #define AXGBE_SGMII_AN_LINK_DUPLEX      BIT(4)
 112
 113 /* ECC correctable error notification window (seconds) */
 114 #define AXGBE_ECC_LIMIT                 60
 115
 116 /* MDIO port types */
 117 #define AXGMAC_MAX_C22_PORT             3
 118
 119 /* Helper macro for descriptor handling
 120  *  Always use AXGBE_GET_DESC_DATA to access the descriptor data
 121  *  since the index is free-running and needs to be and-ed
 122  *  with the descriptor count value of the ring to index to
 123  *  the proper descriptor data.
 124  */
 125 #define AXGBE_GET_DESC_DATA(_ring, _idx)                        \
 126         ((_ring)->rdata +                                       \
 127          ((_idx) & ((_ring)->rdesc_count - 1)))
 128
 129 struct axgbe_port;
 130
 131 enum axgbe_state {
 132         AXGBE_DOWN,
 133         AXGBE_LINK_INIT,
 134         AXGBE_LINK_ERR,
 135         AXGBE_STOPPED,
 136 };
 137
 138 enum axgbe_int {
 139         AXGMAC_INT_DMA_CH_SR_TI,
 140         AXGMAC_INT_DMA_CH_SR_TPS,
 141         AXGMAC_INT_DMA_CH_SR_TBU,
 142         AXGMAC_INT_DMA_CH_SR_RI,
 143         AXGMAC_INT_DMA_CH_SR_RBU,
 144         AXGMAC_INT_DMA_CH_SR_RPS,
 145         AXGMAC_INT_DMA_CH_SR_TI_RI,
 146         AXGMAC_INT_DMA_CH_SR_FBE,
 147         AXGMAC_INT_DMA_ALL,
 148 };
 149
 150 enum axgbe_int_state {
 151         AXGMAC_INT_STATE_SAVE,
 152         AXGMAC_INT_STATE_RESTORE,
 153 };
 154
 155 enum axgbe_ecc_sec {
 156         AXGBE_ECC_SEC_TX,
 157         AXGBE_ECC_SEC_RX,
 158         AXGBE_ECC_SEC_DESC,
 159 };
 160
 161 enum axgbe_speed {
 162         AXGBE_SPEED_1000 = 0,
 163         AXGBE_SPEED_2500,
 164         AXGBE_SPEED_10000,
 165         AXGBE_SPEEDS,
 166 };
 167
 168 enum axgbe_xpcs_access {
 169         AXGBE_XPCS_ACCESS_V1 = 0,
 170         AXGBE_XPCS_ACCESS_V2,
 171 };
 172
 173 enum axgbe_an_mode {
 174         AXGBE_AN_MODE_CL73 = 0,
 175         AXGBE_AN_MODE_CL73_REDRV,
 176         AXGBE_AN_MODE_CL37,
 177         AXGBE_AN_MODE_CL37_SGMII,
 178         AXGBE_AN_MODE_NONE,
 179 };
 180
 181 enum axgbe_an {
 182         AXGBE_AN_READY = 0,
 183         AXGBE_AN_PAGE_RECEIVED,
 184         AXGBE_AN_INCOMPAT_LINK,
 185         AXGBE_AN_COMPLETE,
 186         AXGBE_AN_NO_LINK,
 187         AXGBE_AN_ERROR,
 188 };
 189
 190 enum axgbe_rx {
 191         AXGBE_RX_BPA = 0,
 192         AXGBE_RX_XNP,
 193         AXGBE_RX_COMPLETE,
 194         AXGBE_RX_ERROR,
 195 };
 196
 197 enum axgbe_mode {
 198         AXGBE_MODE_KX_1000 = 0,
 199         AXGBE_MODE_KX_2500,
 200         AXGBE_MODE_KR,
 201         AXGBE_MODE_X,
 202         AXGBE_MODE_SGMII_100,
 203         AXGBE_MODE_SGMII_1000,
 204         AXGBE_MODE_SFI,
 205         AXGBE_MODE_UNKNOWN,
 206 };
 207
 208 enum axgbe_speedset {
 209         AXGBE_SPEEDSET_1000_10000 = 0,
 210         AXGBE_SPEEDSET_2500_10000,
 211 };
 212
 213 enum axgbe_mdio_mode {
 214         AXGBE_MDIO_MODE_NONE = 0,
 215         AXGBE_MDIO_MODE_CL22,
 216         AXGBE_MDIO_MODE_CL45,
 217 };
 218
 219 struct axgbe_phy {
 220         uint32_t supported;
 221         uint32_t advertising;
 222         uint32_t lp_advertising;
 223
 224         int address;
 225
 226         int autoneg;
 227         int speed;
 228         int duplex;
 229
 230         int link;
 231
 232         int pause_autoneg;
 233         int tx_pause;
 234         int rx_pause;
 235 };
 236
 237 enum axgbe_i2c_cmd {
 238         AXGBE_I2C_CMD_READ = 0,
 239         AXGBE_I2C_CMD_WRITE,
 240 };
 241
 242 struct axgbe_i2c_op {
 243         enum axgbe_i2c_cmd cmd;
 244
 245         unsigned int target;
 246
 247         uint8_t *buf;
 248         unsigned int len;
 249 };
 250
 251 struct axgbe_i2c_op_state {
 252         struct axgbe_i2c_op *op;
 253
 254         unsigned int tx_len;
 255         unsigned char *tx_buf;
 256
 257         unsigned int rx_len;
 258         unsigned char *rx_buf;
 259
 260         unsigned int tx_abort_source;
 261
 262         int ret;
 263 };
 264
 265 struct axgbe_i2c {
 266         unsigned int started;
 267         unsigned int max_speed_mode;
 268         unsigned int rx_fifo_size;
 269         unsigned int tx_fifo_size;
 270
 271         struct axgbe_i2c_op_state op_state;
 272 };
 273
 274 struct axgbe_hw_if {
 275         void (*config_flow_control)(struct axgbe_port *);
 276         int (*config_rx_mode)(struct axgbe_port *);
 277
 278         int (*init)(struct axgbe_port *);
 279
 280         int (*read_mmd_regs)(struct axgbe_port *, int, int);
 281         void (*write_mmd_regs)(struct axgbe_port *, int, int, int);
 282         int (*set_speed)(struct axgbe_port *, int);
 283
 284         int (*set_ext_mii_mode)(struct axgbe_port *, unsigned int,
 285                                 enum axgbe_mdio_mode);
 286         int (*read_ext_mii_regs)(struct axgbe_port *, int, int);
 287         int (*write_ext_mii_regs)(struct axgbe_port *, int, int, uint16_t);
 288
 289         /* For FLOW ctrl */
 290         int (*config_tx_flow_control)(struct axgbe_port *);
 291         int (*config_rx_flow_control)(struct axgbe_port *);
 292
 293         int (*exit)(struct axgbe_port *);
 294 };
 295
 296 /* This structure represents implementation specific routines for an
 297  * implementation of a PHY. All routines are required unless noted below.
 298  *   Optional routines:
 299  *     kr_training_pre, kr_training_post
 300  */
 301 struct axgbe_phy_impl_if {
 302         /* Perform Setup/teardown actions */
 303         int (*init)(struct axgbe_port *);
 304         void (*exit)(struct axgbe_port *);
 305
 306         /* Perform start/stop specific actions */
 307         int (*reset)(struct axgbe_port *);
 308         int (*start)(struct axgbe_port *);
 309         void (*stop)(struct axgbe_port *);
 310
 311         /* Return the link status */
 312         int (*link_status)(struct axgbe_port *, int *);
 313
 314         /* Indicate if a particular speed is valid */
 315         int (*valid_speed)(struct axgbe_port *, int);
 316
 317         /* Check if the specified mode can/should be used */
 318         bool (*use_mode)(struct axgbe_port *, enum axgbe_mode);
 319         /* Switch the PHY into various modes */
 320         void (*set_mode)(struct axgbe_port *, enum axgbe_mode);
 321         /* Retrieve mode needed for a specific speed */
 322         enum axgbe_mode (*get_mode)(struct axgbe_port *, int);
 323         /* Retrieve new/next mode when trying to auto-negotiate */
 324         enum axgbe_mode (*switch_mode)(struct axgbe_port *);
 325         /* Retrieve current mode */
 326         enum axgbe_mode (*cur_mode)(struct axgbe_port *);
 327
 328         /* Retrieve current auto-negotiation mode */
 329         enum axgbe_an_mode (*an_mode)(struct axgbe_port *);
 330
 331         /* Configure auto-negotiation settings */
 332         int (*an_config)(struct axgbe_port *);
 333
 334         /* Set/override auto-negotiation advertisement settings */
 335         unsigned int (*an_advertising)(struct axgbe_port *port);
 336
 337         /* Process results of auto-negotiation */
 338         enum axgbe_mode (*an_outcome)(struct axgbe_port *);
 339
 340         /* Pre/Post auto-negotiation support */
 341         void (*an_pre)(struct axgbe_port *port);
 342         void (*an_post)(struct axgbe_port *port);
 343
 344         /* Pre/Post KR training enablement support */
 345         void (*kr_training_pre)(struct axgbe_port *);
 346         void (*kr_training_post)(struct axgbe_port *);
 347 };
 348
 349 struct axgbe_phy_if {
 350         /* For PHY setup/teardown */
 351         int (*phy_init)(struct axgbe_port *);
 352         void (*phy_exit)(struct axgbe_port *);
 353
 354         /* For PHY support when setting device up/down */
 355         int (*phy_reset)(struct axgbe_port *);
 356         int (*phy_start)(struct axgbe_port *);
 357         void (*phy_stop)(struct axgbe_port *);
 358
 359         /* For PHY support while device is up */
 360         void (*phy_status)(struct axgbe_port *);
 361         int (*phy_config_aneg)(struct axgbe_port *);
 362
 363         /* For PHY settings validation */
 364         int (*phy_valid_speed)(struct axgbe_port *, int);
 365         /* For single interrupt support */
 366         void (*an_isr)(struct axgbe_port *);
 367         /* PHY implementation specific services */
 368         struct axgbe_phy_impl_if phy_impl;
 369 };
 370
 371 struct axgbe_i2c_if {
 372         /* For initial I2C setup */
 373         int (*i2c_init)(struct axgbe_port *);
 374
 375         /* For I2C support when setting device up/down */
 376         int (*i2c_start)(struct axgbe_port *);
 377         void (*i2c_stop)(struct axgbe_port *);
 378
 379         /* For performing I2C operations */
 380         int (*i2c_xfer)(struct axgbe_port *, struct axgbe_i2c_op *);
 381 };
 382
 383 /* This structure contains flags that indicate what hardware features
 384  * or configurations are present in the device.
 385  */
 386 struct axgbe_hw_features {
 387         /* HW Version */
 388         unsigned int version;
 389
 390         /* HW Feature Register0 */
 391         unsigned int gmii;              /* 1000 Mbps support */
 392         unsigned int vlhash;            /* VLAN Hash Filter */
 393         unsigned int sma;               /* SMA(MDIO) Interface */
 394         unsigned int rwk;               /* PMT remote wake-up packet */
 395         unsigned int mgk;               /* PMT magic packet */
 396         unsigned int mmc;               /* RMON module */
 397         unsigned int aoe;               /* ARP Offload */
 398         unsigned int ts;                /* IEEE 1588-2008 Advanced Timestamp */
 399         unsigned int eee;               /* Energy Efficient Ethernet */
 400         unsigned int tx_coe;            /* Tx Checksum Offload */
 401         unsigned int rx_coe;            /* Rx Checksum Offload */
 402         unsigned int addn_mac;          /* Additional MAC Addresses */
 403         unsigned int ts_src;            /* Timestamp Source */
 404         unsigned int sa_vlan_ins;       /* Source Address or VLAN Insertion */
 405
 406         /* HW Feature Register1 */
 407         unsigned int rx_fifo_size;      /* MTL Receive FIFO Size */
 408         unsigned int tx_fifo_size;      /* MTL Transmit FIFO Size */
 409         unsigned int adv_ts_hi;         /* Advance Timestamping High Word */
 410         unsigned int dma_width;         /* DMA width */
 411         unsigned int dcb;               /* DCB Feature */
 412         unsigned int sph;               /* Split Header Feature */
 413         unsigned int tso;               /* TCP Segmentation Offload */
 414         unsigned int dma_debug;         /* DMA Debug Registers */
 415         unsigned int rss;               /* Receive Side Scaling */
 416         unsigned int tc_cnt;            /* Number of Traffic Classes */
 417         unsigned int hash_table_size;   /* Hash Table Size */
 418         unsigned int l3l4_filter_num;   /* Number of L3-L4 Filters */
 419
 420         /* HW Feature Register2 */
 421         unsigned int rx_q_cnt;          /* Number of MTL Receive Queues */
 422         unsigned int tx_q_cnt;          /* Number of MTL Transmit Queues */
 423         unsigned int rx_ch_cnt;         /* Number of DMA Receive Channels */
 424         unsigned int tx_ch_cnt;         /* Number of DMA Transmit Channels */
 425         unsigned int pps_out_num;       /* Number of PPS outputs */
 426         unsigned int aux_snap_num;      /* Number of Aux snapshot inputs */
 427 };
 428
 429 struct axgbe_version_data {
 430         void (*init_function_ptrs_phy_impl)(struct axgbe_phy_if *);
 431         enum axgbe_xpcs_access xpcs_access;
 432         unsigned int mmc_64bit;
 433         unsigned int tx_max_fifo_size;
 434         unsigned int rx_max_fifo_size;
 435         unsigned int tx_tstamp_workaround;
 436         unsigned int ecc_support;
 437         unsigned int i2c_support;
 438         unsigned int an_cdr_workaround;
 439 };
 440
 441 /*
 442  * Structure to store private data for each port.
 443  */
 444 struct axgbe_port {
 445         /*  Ethdev where port belongs*/
 446         struct rte_eth_dev *eth_dev;
 447         /* Pci dev info */
 448         const struct rte_pci_device *pci_dev;
 449         /* Version related data */
 450         struct axgbe_version_data *vdata;
 451
 452         /* AXGMAC/XPCS related mmio registers */
 453         void *xgmac_regs;       /* AXGMAC CSRs */
 454         void *xpcs_regs;        /* XPCS MMD registers */
 455         void *xprop_regs;       /* AXGBE property registers */
 456         void *xi2c_regs;        /* AXGBE I2C CSRs */
 457
 458         bool cdr_track_early;
 459         /* XPCS indirect addressing lock */
 460         unsigned int xpcs_window_def_reg;
 461         unsigned int xpcs_window_sel_reg;
 462         unsigned int xpcs_window;
 463         unsigned int xpcs_window_size;
 464         unsigned int xpcs_window_mask;
 465
 466         /* Flags representing axgbe_state */
 467         unsigned long dev_state;
 468
 469         struct axgbe_hw_if hw_if;
 470         struct axgbe_phy_if phy_if;
 471         struct axgbe_i2c_if i2c_if;
 472
 473         /* AXI DMA settings */
 474         unsigned int coherent;
 475         unsigned int axdomain;
 476         unsigned int arcache;
 477         unsigned int awcache;
 478
 479         unsigned int tx_max_channel_count;
 480         unsigned int rx_max_channel_count;
 481         unsigned int channel_count;
 482         unsigned int tx_ring_count;
 483         unsigned int tx_desc_count;
 484         unsigned int rx_ring_count;
 485         unsigned int rx_desc_count;
 486
 487         unsigned int tx_max_q_count;
 488         unsigned int rx_max_q_count;
 489         unsigned int tx_q_count;
 490         unsigned int rx_q_count;
 491
 492         /* Tx/Rx common settings */
 493         unsigned int pblx8;
 494
 495         /* Tx settings */
 496         unsigned int tx_sf_mode;
 497         unsigned int tx_threshold;
 498         unsigned int tx_pbl;
 499         unsigned int tx_osp_mode;
 500         unsigned int tx_max_fifo_size;
 501
 502         /* Rx settings */
 503         unsigned int rx_sf_mode;
 504         unsigned int rx_threshold;
 505         unsigned int rx_pbl;
 506         unsigned int rx_max_fifo_size;
 507         unsigned int rx_buf_size;
 508
 509         /* Device clocks */
 510         unsigned long sysclk_rate;
 511         unsigned long ptpclk_rate;
 512
 513         /* Keeps track of power mode */
 514         unsigned int power_down;
 515
 516         /* Current PHY settings */
 517         int phy_link;
 518         int phy_speed;
 519
 520         pthread_mutex_t xpcs_mutex;
 521         pthread_mutex_t i2c_mutex;
 522         pthread_mutex_t an_mutex;
 523         pthread_mutex_t phy_mutex;
 524
 525         /* Flow control settings */
 526         unsigned int pause_autoneg;
 527         unsigned int tx_pause;
 528         unsigned int rx_pause;
 529         unsigned int rx_rfa[AXGBE_MAX_QUEUES];
 530         unsigned int rx_rfd[AXGBE_MAX_QUEUES];
 531         unsigned int fifo;
 532
 533         /* Receive Side Scaling settings */
 534         u8 rss_key[AXGBE_RSS_HASH_KEY_SIZE];
 535         uint32_t rss_table[AXGBE_RSS_MAX_TABLE_SIZE];
 536         uint32_t rss_options;
 537         int rss_enable;
 538
 539         /* Hardware features of the device */
 540         struct axgbe_hw_features hw_feat;
 541
 542         struct ether_addr mac_addr;
 543
 544         /* Software Tx/Rx structure pointers*/
 545         void **rx_queues;
 546         void **tx_queues;
 547
 548         /* MDIO/PHY related settings */
 549         unsigned int phy_started;
 550         void *phy_data;
 551         struct axgbe_phy phy;
 552         int mdio_mmd;
 553         unsigned long link_check;
 554         volatile int mdio_completion;
 555
 556         unsigned int kr_redrv;
 557
 558         /* Auto-negotiation atate machine support */
 559         unsigned int an_int;
 560         unsigned int an_status;
 561         enum axgbe_an an_result;
 562         enum axgbe_an an_state;
 563         enum axgbe_rx kr_state;
 564         enum axgbe_rx kx_state;
 565         unsigned int an_supported;
 566         unsigned int parallel_detect;
 567         unsigned int fec_ability;
 568         unsigned long an_start;
 569         enum axgbe_an_mode an_mode;
 570
 571         /* I2C support */
 572         struct axgbe_i2c i2c;
 573         volatile int i2c_complete;
 574
 575         /* CRC stripping by H/w for Rx packet*/
 576         int crc_strip_enable;
 577         /* csum enable to hardware */
 578         uint32_t rx_csum_enable;
 579 };
 580
 581 void axgbe_init_function_ptrs_dev(struct axgbe_hw_if *hw_if);
 582 void axgbe_init_function_ptrs_phy(struct axgbe_phy_if *phy_if);
 583 void axgbe_init_function_ptrs_phy_v2(struct axgbe_phy_if *phy_if);
 584 void axgbe_init_function_ptrs_i2c(struct axgbe_i2c_if *i2c_if);
 585
 586 #endif /* RTE_ETH_AXGBE_H_ */