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[ceph.git] / ceph / src / seastar / dpdk / kernel / linux / kni / ethtool / ixgbe / ixgbe_82599.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*******************************************************************************
3
4 Intel 10 Gigabit PCI Express Linux driver
5 Copyright(c) 1999 - 2012 Intel Corporation.
6
7 Contact Information:
8 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
9 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
10
11 *******************************************************************************/
12
13 #include "ixgbe_type.h"
14 #include "ixgbe_82599.h"
15 #include "ixgbe_api.h"
16 #include "ixgbe_common.h"
17 #include "ixgbe_phy.h"
18
19 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
20 ixgbe_link_speed speed,
21 bool autoneg,
22 bool autoneg_wait_to_complete);
23 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
24 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
25 u16 offset, u16 *data);
26 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
27 u16 words, u16 *data);
28 static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
29 u8 dev_addr, u8 *data);
30 static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
31 u8 dev_addr, u8 data);
32
33 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
34 {
35 struct ixgbe_mac_info *mac = &hw->mac;
36
37 /* enable the laser control functions for SFP+ fiber */
38 if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) {
39 mac->ops.disable_tx_laser =
40 &ixgbe_disable_tx_laser_multispeed_fiber;
41 mac->ops.enable_tx_laser =
42 &ixgbe_enable_tx_laser_multispeed_fiber;
43 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
44
45 } else {
46 mac->ops.disable_tx_laser = NULL;
47 mac->ops.enable_tx_laser = NULL;
48 mac->ops.flap_tx_laser = NULL;
49 }
50
51 if (hw->phy.multispeed_fiber) {
52 /* Set up dual speed SFP+ support */
53 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
54 } else {
55 if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) &&
56 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
57 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
58 !ixgbe_verify_lesm_fw_enabled_82599(hw)) {
59 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
60 } else {
61 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
62 }
63 }
64 }
65
66 /**
67 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
68 * @hw: pointer to hardware structure
69 *
70 * Initialize any function pointers that were not able to be
71 * set during init_shared_code because the PHY/SFP type was
72 * not known. Perform the SFP init if necessary.
73 *
74 **/
75 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
76 {
77 struct ixgbe_mac_info *mac = &hw->mac;
78 struct ixgbe_phy_info *phy = &hw->phy;
79 s32 ret_val = 0;
80 u32 esdp;
81
82 if (hw->device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) {
83 /* Store flag indicating I2C bus access control unit. */
84 hw->phy.qsfp_shared_i2c_bus = TRUE;
85
86 /* Initialize access to QSFP+ I2C bus */
87 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
88 esdp |= IXGBE_ESDP_SDP0_DIR;
89 esdp &= ~IXGBE_ESDP_SDP1_DIR;
90 esdp &= ~IXGBE_ESDP_SDP0;
91 esdp &= ~IXGBE_ESDP_SDP0_NATIVE;
92 esdp &= ~IXGBE_ESDP_SDP1_NATIVE;
93 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
94 IXGBE_WRITE_FLUSH(hw);
95
96 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_82599;
97 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_82599;
98 }
99 /* Identify the PHY or SFP module */
100 ret_val = phy->ops.identify(hw);
101 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
102 goto init_phy_ops_out;
103
104 /* Setup function pointers based on detected SFP module and speeds */
105 ixgbe_init_mac_link_ops_82599(hw);
106 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown)
107 hw->phy.ops.reset = NULL;
108
109 /* If copper media, overwrite with copper function pointers */
110 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
111 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
112 mac->ops.get_link_capabilities =
113 &ixgbe_get_copper_link_capabilities_generic;
114 }
115
116 /* Set necessary function pointers based on phy type */
117 switch (hw->phy.type) {
118 case ixgbe_phy_tn:
119 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
120 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
121 phy->ops.get_firmware_version =
122 &ixgbe_get_phy_firmware_version_tnx;
123 break;
124 default:
125 break;
126 }
127 init_phy_ops_out:
128 return ret_val;
129 }
130
131 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
132 {
133 s32 ret_val = 0;
134 u32 reg_anlp1 = 0;
135 u32 i = 0;
136 u16 list_offset, data_offset, data_value;
137
138 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
139 ixgbe_init_mac_link_ops_82599(hw);
140
141 hw->phy.ops.reset = NULL;
142
143 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
144 &data_offset);
145 if (ret_val != 0)
146 goto setup_sfp_out;
147
148 /* PHY config will finish before releasing the semaphore */
149 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
150 IXGBE_GSSR_MAC_CSR_SM);
151 if (ret_val != 0) {
152 ret_val = IXGBE_ERR_SWFW_SYNC;
153 goto setup_sfp_out;
154 }
155
156 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
157 while (data_value != 0xffff) {
158 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
159 IXGBE_WRITE_FLUSH(hw);
160 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
161 }
162
163 /* Release the semaphore */
164 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
165 /* Delay obtaining semaphore again to allow FW access */
166 msleep(hw->eeprom.semaphore_delay);
167
168 /* Now restart DSP by setting Restart_AN and clearing LMS */
169 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((IXGBE_READ_REG(hw,
170 IXGBE_AUTOC) & ~IXGBE_AUTOC_LMS_MASK) |
171 IXGBE_AUTOC_AN_RESTART));
172
173 /* Wait for AN to leave state 0 */
174 for (i = 0; i < 10; i++) {
175 msleep(4);
176 reg_anlp1 = IXGBE_READ_REG(hw, IXGBE_ANLP1);
177 if (reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)
178 break;
179 }
180 if (!(reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)) {
181 hw_dbg(hw, "sfp module setup not complete\n");
182 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
183 goto setup_sfp_out;
184 }
185
186 /* Restart DSP by setting Restart_AN and return to SFI mode */
187 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw,
188 IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL |
189 IXGBE_AUTOC_AN_RESTART));
190 }
191
192 setup_sfp_out:
193 return ret_val;
194 }
195
196 /**
197 * ixgbe_init_ops_82599 - Inits func ptrs and MAC type
198 * @hw: pointer to hardware structure
199 *
200 * Initialize the function pointers and assign the MAC type for 82599.
201 * Does not touch the hardware.
202 **/
203
204 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)
205 {
206 struct ixgbe_mac_info *mac = &hw->mac;
207 struct ixgbe_phy_info *phy = &hw->phy;
208 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
209 s32 ret_val;
210
211 ixgbe_init_phy_ops_generic(hw);
212 ret_val = ixgbe_init_ops_generic(hw);
213
214 /* PHY */
215 phy->ops.identify = &ixgbe_identify_phy_82599;
216 phy->ops.init = &ixgbe_init_phy_ops_82599;
217
218 /* MAC */
219 mac->ops.reset_hw = &ixgbe_reset_hw_82599;
220 mac->ops.get_media_type = &ixgbe_get_media_type_82599;
221 mac->ops.get_supported_physical_layer =
222 &ixgbe_get_supported_physical_layer_82599;
223 mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic;
224 mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic;
225 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_82599;
226 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82599;
227 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82599;
228 mac->ops.start_hw = &ixgbe_start_hw_82599;
229 mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
230 mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
231 mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
232 mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
233 mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;
234
235 /* RAR, Multicast, VLAN */
236 mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
237 mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic;
238 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
239 mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
240 mac->rar_highwater = 1;
241 mac->ops.set_vfta = &ixgbe_set_vfta_generic;
242 mac->ops.set_vlvf = &ixgbe_set_vlvf_generic;
243 mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
244 mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
245 mac->ops.setup_sfp = &ixgbe_setup_sfp_modules_82599;
246 mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;
247 mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;
248
249 /* Link */
250 mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82599;
251 mac->ops.check_link = &ixgbe_check_mac_link_generic;
252 mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;
253 ixgbe_init_mac_link_ops_82599(hw);
254
255 mac->mcft_size = 128;
256 mac->vft_size = 128;
257 mac->num_rar_entries = 128;
258 mac->rx_pb_size = 512;
259 mac->max_tx_queues = 128;
260 mac->max_rx_queues = 128;
261 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
262
263 mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
264 IXGBE_FWSM_MODE_MASK) ? true : false;
265
266 //hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
267
268 /* EEPROM */
269 eeprom->ops.read = &ixgbe_read_eeprom_82599;
270 eeprom->ops.read_buffer = &ixgbe_read_eeprom_buffer_82599;
271
272 /* Manageability interface */
273 mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
274
275 mac->ops.get_thermal_sensor_data =
276 &ixgbe_get_thermal_sensor_data_generic;
277 mac->ops.init_thermal_sensor_thresh =
278 &ixgbe_init_thermal_sensor_thresh_generic;
279
280 return ret_val;
281 }
282
283 /**
284 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
285 * @hw: pointer to hardware structure
286 * @speed: pointer to link speed
287 * @negotiation: true when autoneg or autotry is enabled
288 *
289 * Determines the link capabilities by reading the AUTOC register.
290 **/
291 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
292 ixgbe_link_speed *speed,
293 bool *negotiation)
294 {
295 s32 status = 0;
296 u32 autoc = 0;
297
298 /* Check if 1G SFP module. */
299 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
300 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
301 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
302 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
303 *speed = IXGBE_LINK_SPEED_1GB_FULL;
304 *negotiation = true;
305 goto out;
306 }
307
308 /*
309 * Determine link capabilities based on the stored value of AUTOC,
310 * which represents EEPROM defaults. If AUTOC value has not
311 * been stored, use the current register values.
312 */
313 if (hw->mac.orig_link_settings_stored)
314 autoc = hw->mac.orig_autoc;
315 else
316 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
317
318 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
319 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
320 *speed = IXGBE_LINK_SPEED_1GB_FULL;
321 *negotiation = false;
322 break;
323
324 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
325 *speed = IXGBE_LINK_SPEED_10GB_FULL;
326 *negotiation = false;
327 break;
328
329 case IXGBE_AUTOC_LMS_1G_AN:
330 *speed = IXGBE_LINK_SPEED_1GB_FULL;
331 *negotiation = true;
332 break;
333
334 case IXGBE_AUTOC_LMS_10G_SERIAL:
335 *speed = IXGBE_LINK_SPEED_10GB_FULL;
336 *negotiation = false;
337 break;
338
339 case IXGBE_AUTOC_LMS_KX4_KX_KR:
340 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
341 *speed = IXGBE_LINK_SPEED_UNKNOWN;
342 if (autoc & IXGBE_AUTOC_KR_SUPP)
343 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
344 if (autoc & IXGBE_AUTOC_KX4_SUPP)
345 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
346 if (autoc & IXGBE_AUTOC_KX_SUPP)
347 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
348 *negotiation = true;
349 break;
350
351 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
352 *speed = IXGBE_LINK_SPEED_100_FULL;
353 if (autoc & IXGBE_AUTOC_KR_SUPP)
354 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
355 if (autoc & IXGBE_AUTOC_KX4_SUPP)
356 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
357 if (autoc & IXGBE_AUTOC_KX_SUPP)
358 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
359 *negotiation = true;
360 break;
361
362 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
363 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
364 *negotiation = false;
365 break;
366
367 default:
368 status = IXGBE_ERR_LINK_SETUP;
369 goto out;
370 break;
371 }
372
373 if (hw->phy.multispeed_fiber) {
374 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
375 IXGBE_LINK_SPEED_1GB_FULL;
376 *negotiation = true;
377 }
378
379 out:
380 return status;
381 }
382
383 /**
384 * ixgbe_get_media_type_82599 - Get media type
385 * @hw: pointer to hardware structure
386 *
387 * Returns the media type (fiber, copper, backplane)
388 **/
389 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
390 {
391 enum ixgbe_media_type media_type;
392
393 /* Detect if there is a copper PHY attached. */
394 switch (hw->phy.type) {
395 case ixgbe_phy_cu_unknown:
396 case ixgbe_phy_tn:
397 media_type = ixgbe_media_type_copper;
398 goto out;
399 default:
400 break;
401 }
402
403 switch (hw->device_id) {
404 case IXGBE_DEV_ID_82599_KX4:
405 case IXGBE_DEV_ID_82599_KX4_MEZZ:
406 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
407 case IXGBE_DEV_ID_82599_KR:
408 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
409 case IXGBE_DEV_ID_82599_XAUI_LOM:
410 /* Default device ID is mezzanine card KX/KX4 */
411 media_type = ixgbe_media_type_backplane;
412 break;
413 case IXGBE_DEV_ID_82599_SFP:
414 case IXGBE_DEV_ID_82599_SFP_FCOE:
415 case IXGBE_DEV_ID_82599_SFP_EM:
416 case IXGBE_DEV_ID_82599_SFP_SF2:
417 case IXGBE_DEV_ID_82599EN_SFP:
418 media_type = ixgbe_media_type_fiber;
419 break;
420 case IXGBE_DEV_ID_82599_CX4:
421 media_type = ixgbe_media_type_cx4;
422 break;
423 case IXGBE_DEV_ID_82599_T3_LOM:
424 media_type = ixgbe_media_type_copper;
425 break;
426 case IXGBE_DEV_ID_82599_LS:
427 media_type = ixgbe_media_type_fiber_lco;
428 break;
429 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
430 media_type = ixgbe_media_type_fiber_qsfp;
431 break;
432 default:
433 media_type = ixgbe_media_type_unknown;
434 break;
435 }
436 out:
437 return media_type;
438 }
439
440 /**
441 * ixgbe_start_mac_link_82599 - Setup MAC link settings
442 * @hw: pointer to hardware structure
443 * @autoneg_wait_to_complete: true when waiting for completion is needed
444 *
445 * Configures link settings based on values in the ixgbe_hw struct.
446 * Restarts the link. Performs autonegotiation if needed.
447 **/
448 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
449 bool autoneg_wait_to_complete)
450 {
451 u32 autoc_reg;
452 u32 links_reg = 0;
453 u32 i;
454 s32 status = 0;
455
456 /* Restart link */
457 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
458 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
459 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
460
461 /* Only poll for autoneg to complete if specified to do so */
462 if (autoneg_wait_to_complete) {
463 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
464 IXGBE_AUTOC_LMS_KX4_KX_KR ||
465 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
466 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
467 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
468 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
469 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
470 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
471 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
472 break;
473 msleep(100);
474 }
475 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
476 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
477 hw_dbg(hw, "Autoneg did not complete.\n");
478 }
479 }
480 }
481
482 /* Add delay to filter out noises during initial link setup */
483 msleep(50);
484
485 return status;
486 }
487
488 /**
489 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
490 * @hw: pointer to hardware structure
491 *
492 * The base drivers may require better control over SFP+ module
493 * PHY states. This includes selectively shutting down the Tx
494 * laser on the PHY, effectively halting physical link.
495 **/
496 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
497 {
498 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
499
500 /* Disable tx laser; allow 100us to go dark per spec */
501 esdp_reg |= IXGBE_ESDP_SDP3;
502 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
503 IXGBE_WRITE_FLUSH(hw);
504 udelay(100);
505 }
506
507 /**
508 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
509 * @hw: pointer to hardware structure
510 *
511 * The base drivers may require better control over SFP+ module
512 * PHY states. This includes selectively turning on the Tx
513 * laser on the PHY, effectively starting physical link.
514 **/
515 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
516 {
517 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
518
519 /* Enable tx laser; allow 100ms to light up */
520 esdp_reg &= ~IXGBE_ESDP_SDP3;
521 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
522 IXGBE_WRITE_FLUSH(hw);
523 msleep(100);
524 }
525
526 /**
527 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
528 * @hw: pointer to hardware structure
529 *
530 * When the driver changes the link speeds that it can support,
531 * it sets autotry_restart to true to indicate that we need to
532 * initiate a new autotry session with the link partner. To do
533 * so, we set the speed then disable and re-enable the tx laser, to
534 * alert the link partner that it also needs to restart autotry on its
535 * end. This is consistent with true clause 37 autoneg, which also
536 * involves a loss of signal.
537 **/
538 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
539 {
540 if (hw->mac.autotry_restart) {
541 ixgbe_disable_tx_laser_multispeed_fiber(hw);
542 ixgbe_enable_tx_laser_multispeed_fiber(hw);
543 hw->mac.autotry_restart = false;
544 }
545 }
546
547 /**
548 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
549 * @hw: pointer to hardware structure
550 * @speed: new link speed
551 * @autoneg: true if autonegotiation enabled
552 * @autoneg_wait_to_complete: true when waiting for completion is needed
553 *
554 * Set the link speed in the AUTOC register and restarts link.
555 **/
556 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
557 ixgbe_link_speed speed, bool autoneg,
558 bool autoneg_wait_to_complete)
559 {
560 s32 status = 0;
561 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
562 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
563 u32 speedcnt = 0;
564 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
565 u32 i = 0;
566 bool link_up = false;
567 bool negotiation;
568
569 /* Mask off requested but non-supported speeds */
570 status = ixgbe_get_link_capabilities(hw, &link_speed, &negotiation);
571 if (status != 0)
572 return status;
573
574 speed &= link_speed;
575
576 /*
577 * Try each speed one by one, highest priority first. We do this in
578 * software because 10gb fiber doesn't support speed autonegotiation.
579 */
580 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
581 speedcnt++;
582 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
583
584 /* If we already have link at this speed, just jump out */
585 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
586 if (status != 0)
587 return status;
588
589 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
590 goto out;
591
592 /* Set the module link speed */
593 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
594 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
595 IXGBE_WRITE_FLUSH(hw);
596
597 /* Allow module to change analog characteristics (1G->10G) */
598 msleep(40);
599
600 status = ixgbe_setup_mac_link_82599(hw,
601 IXGBE_LINK_SPEED_10GB_FULL,
602 autoneg,
603 autoneg_wait_to_complete);
604 if (status != 0)
605 return status;
606
607 /* Flap the tx laser if it has not already been done */
608 ixgbe_flap_tx_laser(hw);
609
610 /*
611 * Wait for the controller to acquire link. Per IEEE 802.3ap,
612 * Section 73.10.2, we may have to wait up to 500ms if KR is
613 * attempted. 82599 uses the same timing for 10g SFI.
614 */
615 for (i = 0; i < 5; i++) {
616 /* Wait for the link partner to also set speed */
617 msleep(100);
618
619 /* If we have link, just jump out */
620 status = ixgbe_check_link(hw, &link_speed,
621 &link_up, false);
622 if (status != 0)
623 return status;
624
625 if (link_up)
626 goto out;
627 }
628 }
629
630 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
631 speedcnt++;
632 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
633 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
634
635 /* If we already have link at this speed, just jump out */
636 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
637 if (status != 0)
638 return status;
639
640 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
641 goto out;
642
643 /* Set the module link speed */
644 esdp_reg &= ~IXGBE_ESDP_SDP5;
645 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
646 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
647 IXGBE_WRITE_FLUSH(hw);
648
649 /* Allow module to change analog characteristics (10G->1G) */
650 msleep(40);
651
652 status = ixgbe_setup_mac_link_82599(hw,
653 IXGBE_LINK_SPEED_1GB_FULL,
654 autoneg,
655 autoneg_wait_to_complete);
656 if (status != 0)
657 return status;
658
659 /* Flap the tx laser if it has not already been done */
660 ixgbe_flap_tx_laser(hw);
661
662 /* Wait for the link partner to also set speed */
663 msleep(100);
664
665 /* If we have link, just jump out */
666 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
667 if (status != 0)
668 return status;
669
670 if (link_up)
671 goto out;
672 }
673
674 /*
675 * We didn't get link. Configure back to the highest speed we tried,
676 * (if there was more than one). We call ourselves back with just the
677 * single highest speed that the user requested.
678 */
679 if (speedcnt > 1)
680 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
681 highest_link_speed, autoneg, autoneg_wait_to_complete);
682
683 out:
684 /* Set autoneg_advertised value based on input link speed */
685 hw->phy.autoneg_advertised = 0;
686
687 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
688 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
689
690 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
691 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
692
693 return status;
694 }
695
696 /**
697 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
698 * @hw: pointer to hardware structure
699 * @speed: new link speed
700 * @autoneg: true if autonegotiation enabled
701 * @autoneg_wait_to_complete: true when waiting for completion is needed
702 *
703 * Implements the Intel SmartSpeed algorithm.
704 **/
705 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
706 ixgbe_link_speed speed, bool autoneg,
707 bool autoneg_wait_to_complete)
708 {
709 s32 status = 0;
710 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
711 s32 i, j;
712 bool link_up = false;
713 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
714
715 /* Set autoneg_advertised value based on input link speed */
716 hw->phy.autoneg_advertised = 0;
717
718 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
719 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
720
721 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
722 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
723
724 if (speed & IXGBE_LINK_SPEED_100_FULL)
725 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
726
727 /*
728 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
729 * autoneg advertisement if link is unable to be established at the
730 * highest negotiated rate. This can sometimes happen due to integrity
731 * issues with the physical media connection.
732 */
733
734 /* First, try to get link with full advertisement */
735 hw->phy.smart_speed_active = false;
736 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
737 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
738 autoneg_wait_to_complete);
739 if (status != 0)
740 goto out;
741
742 /*
743 * Wait for the controller to acquire link. Per IEEE 802.3ap,
744 * Section 73.10.2, we may have to wait up to 500ms if KR is
745 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
746 * Table 9 in the AN MAS.
747 */
748 for (i = 0; i < 5; i++) {
749 msleep(100);
750
751 /* If we have link, just jump out */
752 status = ixgbe_check_link(hw, &link_speed, &link_up,
753 false);
754 if (status != 0)
755 goto out;
756
757 if (link_up)
758 goto out;
759 }
760 }
761
762 /*
763 * We didn't get link. If we advertised KR plus one of KX4/KX
764 * (or BX4/BX), then disable KR and try again.
765 */
766 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
767 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
768 goto out;
769
770 /* Turn SmartSpeed on to disable KR support */
771 hw->phy.smart_speed_active = true;
772 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
773 autoneg_wait_to_complete);
774 if (status != 0)
775 goto out;
776
777 /*
778 * Wait for the controller to acquire link. 600ms will allow for
779 * the AN link_fail_inhibit_timer as well for multiple cycles of
780 * parallel detect, both 10g and 1g. This allows for the maximum
781 * connect attempts as defined in the AN MAS table 73-7.
782 */
783 for (i = 0; i < 6; i++) {
784 msleep(100);
785
786 /* If we have link, just jump out */
787 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
788 if (status != 0)
789 goto out;
790
791 if (link_up)
792 goto out;
793 }
794
795 /* We didn't get link. Turn SmartSpeed back off. */
796 hw->phy.smart_speed_active = false;
797 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
798 autoneg_wait_to_complete);
799
800 out:
801 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
802 hw_dbg(hw, "Smartspeed has downgraded the link speed "
803 "from the maximum advertised\n");
804 return status;
805 }
806
807 /**
808 * ixgbe_setup_mac_link_82599 - Set MAC link speed
809 * @hw: pointer to hardware structure
810 * @speed: new link speed
811 * @autoneg: true if autonegotiation enabled
812 * @autoneg_wait_to_complete: true when waiting for completion is needed
813 *
814 * Set the link speed in the AUTOC register and restarts link.
815 **/
816 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
817 ixgbe_link_speed speed, bool autoneg,
818 bool autoneg_wait_to_complete)
819 {
820 s32 status = 0;
821 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
822 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
823 u32 start_autoc = autoc;
824 u32 orig_autoc = 0;
825 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
826 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
827 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
828 u32 links_reg = 0;
829 u32 i;
830 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
831
832 /* Check to see if speed passed in is supported. */
833 status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
834 if (status != 0)
835 goto out;
836
837 speed &= link_capabilities;
838
839 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
840 status = IXGBE_ERR_LINK_SETUP;
841 goto out;
842 }
843
844 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
845 if (hw->mac.orig_link_settings_stored)
846 orig_autoc = hw->mac.orig_autoc;
847 else
848 orig_autoc = autoc;
849
850 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
851 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
852 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
853 /* Set KX4/KX/KR support according to speed requested */
854 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
855 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
856 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
857 autoc |= IXGBE_AUTOC_KX4_SUPP;
858 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
859 (hw->phy.smart_speed_active == false))
860 autoc |= IXGBE_AUTOC_KR_SUPP;
861 }
862 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
863 autoc |= IXGBE_AUTOC_KX_SUPP;
864 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
865 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
866 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
867 /* Switch from 1G SFI to 10G SFI if requested */
868 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
869 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
870 autoc &= ~IXGBE_AUTOC_LMS_MASK;
871 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
872 }
873 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
874 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
875 /* Switch from 10G SFI to 1G SFI if requested */
876 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
877 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
878 autoc &= ~IXGBE_AUTOC_LMS_MASK;
879 if (autoneg)
880 autoc |= IXGBE_AUTOC_LMS_1G_AN;
881 else
882 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
883 }
884 }
885
886 if (autoc != start_autoc) {
887 /* Restart link */
888 autoc |= IXGBE_AUTOC_AN_RESTART;
889 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
890
891 /* Only poll for autoneg to complete if specified to do so */
892 if (autoneg_wait_to_complete) {
893 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
894 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
895 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
896 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
897 links_reg =
898 IXGBE_READ_REG(hw, IXGBE_LINKS);
899 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
900 break;
901 msleep(100);
902 }
903 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
904 status =
905 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
906 hw_dbg(hw, "Autoneg did not complete.\n");
907 }
908 }
909 }
910
911 /* Add delay to filter out noises during initial link setup */
912 msleep(50);
913 }
914
915 out:
916 return status;
917 }
918
919 /**
920 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
921 * @hw: pointer to hardware structure
922 * @speed: new link speed
923 * @autoneg: true if autonegotiation enabled
924 * @autoneg_wait_to_complete: true if waiting is needed to complete
925 *
926 * Restarts link on PHY and MAC based on settings passed in.
927 **/
928 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
929 ixgbe_link_speed speed,
930 bool autoneg,
931 bool autoneg_wait_to_complete)
932 {
933 s32 status;
934
935 /* Setup the PHY according to input speed */
936 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
937 autoneg_wait_to_complete);
938 /* Set up MAC */
939 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
940
941 return status;
942 }
943
944 /**
945 * ixgbe_reset_hw_82599 - Perform hardware reset
946 * @hw: pointer to hardware structure
947 *
948 * Resets the hardware by resetting the transmit and receive units, masks
949 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
950 * reset.
951 **/
952 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
953 {
954 // ixgbe_link_speed link_speed;
955 s32 status = 0;
956 // u32 ctrl, i, autoc, autoc2;
957 // bool link_up = false;
958
959 #if 0
960 /* Call adapter stop to disable tx/rx and clear interrupts */
961 status = hw->mac.ops.stop_adapter(hw);
962 if (status != 0)
963 goto reset_hw_out;
964
965 /* flush pending Tx transactions */
966 ixgbe_clear_tx_pending(hw);
967
968 /* PHY ops must be identified and initialized prior to reset */
969
970 /* Identify PHY and related function pointers */
971 status = hw->phy.ops.init(hw);
972
973 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
974 goto reset_hw_out;
975
976 /* Setup SFP module if there is one present. */
977 if (hw->phy.sfp_setup_needed) {
978 status = hw->mac.ops.setup_sfp(hw);
979 hw->phy.sfp_setup_needed = false;
980 }
981
982 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
983 goto reset_hw_out;
984
985 /* Reset PHY */
986 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
987 hw->phy.ops.reset(hw);
988
989 mac_reset_top:
990 /*
991 * Issue global reset to the MAC. Needs to be SW reset if link is up.
992 * If link reset is used when link is up, it might reset the PHY when
993 * mng is using it. If link is down or the flag to force full link
994 * reset is set, then perform link reset.
995 */
996 ctrl = IXGBE_CTRL_LNK_RST;
997 if (!hw->force_full_reset) {
998 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
999 if (link_up)
1000 ctrl = IXGBE_CTRL_RST;
1001 }
1002
1003 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1004 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1005 IXGBE_WRITE_FLUSH(hw);
1006
1007 /* Poll for reset bit to self-clear indicating reset is complete */
1008 for (i = 0; i < 10; i++) {
1009 udelay(1);
1010 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1011 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1012 break;
1013 }
1014
1015 if (ctrl & IXGBE_CTRL_RST_MASK) {
1016 status = IXGBE_ERR_RESET_FAILED;
1017 hw_dbg(hw, "Reset polling failed to complete.\n");
1018 }
1019
1020 msleep(50);
1021
1022 /*
1023 * Double resets are required for recovery from certain error
1024 * conditions. Between resets, it is necessary to stall to allow time
1025 * for any pending HW events to complete.
1026 */
1027 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1028 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1029 goto mac_reset_top;
1030 }
1031
1032 /*
1033 * Store the original AUTOC/AUTOC2 values if they have not been
1034 * stored off yet. Otherwise restore the stored original
1035 * values since the reset operation sets back to defaults.
1036 */
1037 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1038 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1039 if (hw->mac.orig_link_settings_stored == false) {
1040 hw->mac.orig_autoc = autoc;
1041 hw->mac.orig_autoc2 = autoc2;
1042 hw->mac.orig_link_settings_stored = true;
1043 } else {
1044 if (autoc != hw->mac.orig_autoc)
1045 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
1046 IXGBE_AUTOC_AN_RESTART));
1047
1048 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
1049 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1050 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
1051 autoc2 |= (hw->mac.orig_autoc2 &
1052 IXGBE_AUTOC2_UPPER_MASK);
1053 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1054 }
1055 }
1056 #endif
1057
1058 /* Store the permanent mac address */
1059 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1060
1061 /*
1062 * Store MAC address from RAR0, clear receive address registers, and
1063 * clear the multicast table. Also reset num_rar_entries to 128,
1064 * since we modify this value when programming the SAN MAC address.
1065 */
1066 hw->mac.num_rar_entries = 128;
1067 hw->mac.ops.init_rx_addrs(hw);
1068
1069 /* Store the permanent SAN mac address */
1070 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1071
1072 /* Add the SAN MAC address to the RAR only if it's a valid address */
1073 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
1074 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1075 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1076
1077 /* Save the SAN MAC RAR index */
1078 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
1079
1080 /* Reserve the last RAR for the SAN MAC address */
1081 hw->mac.num_rar_entries--;
1082 }
1083
1084 /* Store the alternative WWNN/WWPN prefix */
1085 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1086 &hw->mac.wwpn_prefix);
1087
1088 //reset_hw_out:
1089 return status;
1090 }
1091
1092 /**
1093 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1094 * @hw: pointer to hardware structure
1095 **/
1096 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1097 {
1098 int i;
1099 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1100 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1101
1102 /*
1103 * Before starting reinitialization process,
1104 * FDIRCMD.CMD must be zero.
1105 */
1106 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1107 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1108 IXGBE_FDIRCMD_CMD_MASK))
1109 break;
1110 udelay(10);
1111 }
1112 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1113 hw_dbg(hw, "Flow Director previous command isn't complete, "
1114 "aborting table re-initialization.\n");
1115 return IXGBE_ERR_FDIR_REINIT_FAILED;
1116 }
1117
1118 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1119 IXGBE_WRITE_FLUSH(hw);
1120 /*
1121 * 82599 adapters flow director init flow cannot be restarted,
1122 * Workaround 82599 silicon errata by performing the following steps
1123 * before re-writing the FDIRCTRL control register with the same value.
1124 * - write 1 to bit 8 of FDIRCMD register &
1125 * - write 0 to bit 8 of FDIRCMD register
1126 */
1127 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1128 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1129 IXGBE_FDIRCMD_CLEARHT));
1130 IXGBE_WRITE_FLUSH(hw);
1131 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1132 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1133 ~IXGBE_FDIRCMD_CLEARHT));
1134 IXGBE_WRITE_FLUSH(hw);
1135 /*
1136 * Clear FDIR Hash register to clear any leftover hashes
1137 * waiting to be programmed.
1138 */
1139 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1140 IXGBE_WRITE_FLUSH(hw);
1141
1142 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1143 IXGBE_WRITE_FLUSH(hw);
1144
1145 /* Poll init-done after we write FDIRCTRL register */
1146 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1147 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1148 IXGBE_FDIRCTRL_INIT_DONE)
1149 break;
1150 udelay(10);
1151 }
1152 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1153 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1154 return IXGBE_ERR_FDIR_REINIT_FAILED;
1155 }
1156
1157 /* Clear FDIR statistics registers (read to clear) */
1158 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1159 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1160 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1161 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1162 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1163
1164 return 0;
1165 }
1166
1167 /**
1168 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1169 * @hw: pointer to hardware structure
1170 * @fdirctrl: value to write to flow director control register
1171 **/
1172 static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1173 {
1174 int i;
1175
1176 /* Prime the keys for hashing */
1177 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1178 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1179
1180 /*
1181 * Poll init-done after we write the register. Estimated times:
1182 * 10G: PBALLOC = 11b, timing is 60us
1183 * 1G: PBALLOC = 11b, timing is 600us
1184 * 100M: PBALLOC = 11b, timing is 6ms
1185 *
1186 * Multiple these timings by 4 if under full Rx load
1187 *
1188 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1189 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1190 * this might not finish in our poll time, but we can live with that
1191 * for now.
1192 */
1193 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1194 IXGBE_WRITE_FLUSH(hw);
1195 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1196 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1197 IXGBE_FDIRCTRL_INIT_DONE)
1198 break;
1199 msleep(1);
1200 }
1201
1202 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1203 hw_dbg(hw, "Flow Director poll time exceeded!\n");
1204 }
1205
1206 /**
1207 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1208 * @hw: pointer to hardware structure
1209 * @fdirctrl: value to write to flow director control register, initially
1210 * contains just the value of the Rx packet buffer allocation
1211 **/
1212 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1213 {
1214 /*
1215 * Continue setup of fdirctrl register bits:
1216 * Move the flexible bytes to use the ethertype - shift 6 words
1217 * Set the maximum length per hash bucket to 0xA filters
1218 * Send interrupt when 64 filters are left
1219 */
1220 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1221 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1222 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1223
1224 /* write hashes and fdirctrl register, poll for completion */
1225 ixgbe_fdir_enable_82599(hw, fdirctrl);
1226
1227 return 0;
1228 }
1229
1230 /**
1231 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1232 * @hw: pointer to hardware structure
1233 * @fdirctrl: value to write to flow director control register, initially
1234 * contains just the value of the Rx packet buffer allocation
1235 **/
1236 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1237 {
1238 /*
1239 * Continue setup of fdirctrl register bits:
1240 * Turn perfect match filtering on
1241 * Report hash in RSS field of Rx wb descriptor
1242 * Initialize the drop queue
1243 * Move the flexible bytes to use the ethertype - shift 6 words
1244 * Set the maximum length per hash bucket to 0xA filters
1245 * Send interrupt when 64 (0x4 * 16) filters are left
1246 */
1247 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
1248 IXGBE_FDIRCTRL_REPORT_STATUS |
1249 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
1250 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1251 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1252 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1253
1254 /* write hashes and fdirctrl register, poll for completion */
1255 ixgbe_fdir_enable_82599(hw, fdirctrl);
1256
1257 return 0;
1258 }
1259
1260 /*
1261 * These defines allow us to quickly generate all of the necessary instructions
1262 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1263 * for values 0 through 15
1264 */
1265 #define IXGBE_ATR_COMMON_HASH_KEY \
1266 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1267 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1268 do { \
1269 u32 n = (_n); \
1270 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1271 common_hash ^= lo_hash_dword >> n; \
1272 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1273 bucket_hash ^= lo_hash_dword >> n; \
1274 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1275 sig_hash ^= lo_hash_dword << (16 - n); \
1276 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1277 common_hash ^= hi_hash_dword >> n; \
1278 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1279 bucket_hash ^= hi_hash_dword >> n; \
1280 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1281 sig_hash ^= hi_hash_dword << (16 - n); \
1282 } while (0);
1283
1284 /**
1285 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1286 * @stream: input bitstream to compute the hash on
1287 *
1288 * This function is almost identical to the function above but contains
1289 * several optomizations such as unwinding all of the loops, letting the
1290 * compiler work out all of the conditional ifs since the keys are static
1291 * defines, and computing two keys at once since the hashed dword stream
1292 * will be the same for both keys.
1293 **/
1294 u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1295 union ixgbe_atr_hash_dword common)
1296 {
1297 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1298 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1299
1300 /* record the flow_vm_vlan bits as they are a key part to the hash */
1301 flow_vm_vlan = IXGBE_NTOHL(input.dword);
1302
1303 /* generate common hash dword */
1304 hi_hash_dword = IXGBE_NTOHL(common.dword);
1305
1306 /* low dword is word swapped version of common */
1307 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1308
1309 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1310 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1311
1312 /* Process bits 0 and 16 */
1313 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1314
1315 /*
1316 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1317 * delay this because bit 0 of the stream should not be processed
1318 * so we do not add the vlan until after bit 0 was processed
1319 */
1320 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1321
1322 /* Process remaining 30 bit of the key */
1323 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1324 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1325 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1326 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1327 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1328 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1329 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1330 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1331 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1332 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1333 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1334 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1335 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1336 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1337 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1338
1339 /* combine common_hash result with signature and bucket hashes */
1340 bucket_hash ^= common_hash;
1341 bucket_hash &= IXGBE_ATR_HASH_MASK;
1342
1343 sig_hash ^= common_hash << 16;
1344 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1345
1346 /* return completed signature hash */
1347 return sig_hash ^ bucket_hash;
1348 }
1349
1350 /**
1351 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1352 * @hw: pointer to hardware structure
1353 * @input: unique input dword
1354 * @common: compressed common input dword
1355 * @queue: queue index to direct traffic to
1356 **/
1357 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1358 union ixgbe_atr_hash_dword input,
1359 union ixgbe_atr_hash_dword common,
1360 u8 queue)
1361 {
1362 u64 fdirhashcmd;
1363 u32 fdircmd;
1364
1365 /*
1366 * Get the flow_type in order to program FDIRCMD properly
1367 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1368 */
1369 switch (input.formatted.flow_type) {
1370 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1371 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1372 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1373 case IXGBE_ATR_FLOW_TYPE_TCPV6:
1374 case IXGBE_ATR_FLOW_TYPE_UDPV6:
1375 case IXGBE_ATR_FLOW_TYPE_SCTPV6:
1376 break;
1377 default:
1378 hw_dbg(hw, " Error on flow type input\n");
1379 return IXGBE_ERR_CONFIG;
1380 }
1381
1382 /* configure FDIRCMD register */
1383 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1384 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1385 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1386 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1387
1388 /*
1389 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1390 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1391 */
1392 fdirhashcmd = (u64)fdircmd << 32;
1393 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
1394 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1395
1396 hw_dbg(hw, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1397
1398 return 0;
1399 }
1400
1401 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
1402 do { \
1403 u32 n = (_n); \
1404 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1405 bucket_hash ^= lo_hash_dword >> n; \
1406 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1407 bucket_hash ^= hi_hash_dword >> n; \
1408 } while (0);
1409
1410 /**
1411 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1412 * @atr_input: input bitstream to compute the hash on
1413 * @input_mask: mask for the input bitstream
1414 *
1415 * This function serves two main purposes. First it applys the input_mask
1416 * to the atr_input resulting in a cleaned up atr_input data stream.
1417 * Secondly it computes the hash and stores it in the bkt_hash field at
1418 * the end of the input byte stream. This way it will be available for
1419 * future use without needing to recompute the hash.
1420 **/
1421 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
1422 union ixgbe_atr_input *input_mask)
1423 {
1424
1425 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1426 u32 bucket_hash = 0;
1427
1428 /* Apply masks to input data */
1429 input->dword_stream[0] &= input_mask->dword_stream[0];
1430 input->dword_stream[1] &= input_mask->dword_stream[1];
1431 input->dword_stream[2] &= input_mask->dword_stream[2];
1432 input->dword_stream[3] &= input_mask->dword_stream[3];
1433 input->dword_stream[4] &= input_mask->dword_stream[4];
1434 input->dword_stream[5] &= input_mask->dword_stream[5];
1435 input->dword_stream[6] &= input_mask->dword_stream[6];
1436 input->dword_stream[7] &= input_mask->dword_stream[7];
1437 input->dword_stream[8] &= input_mask->dword_stream[8];
1438 input->dword_stream[9] &= input_mask->dword_stream[9];
1439 input->dword_stream[10] &= input_mask->dword_stream[10];
1440
1441 /* record the flow_vm_vlan bits as they are a key part to the hash */
1442 flow_vm_vlan = IXGBE_NTOHL(input->dword_stream[0]);
1443
1444 /* generate common hash dword */
1445 hi_hash_dword = IXGBE_NTOHL(input->dword_stream[1] ^
1446 input->dword_stream[2] ^
1447 input->dword_stream[3] ^
1448 input->dword_stream[4] ^
1449 input->dword_stream[5] ^
1450 input->dword_stream[6] ^
1451 input->dword_stream[7] ^
1452 input->dword_stream[8] ^
1453 input->dword_stream[9] ^
1454 input->dword_stream[10]);
1455
1456 /* low dword is word swapped version of common */
1457 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1458
1459 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1460 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1461
1462 /* Process bits 0 and 16 */
1463 IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
1464
1465 /*
1466 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1467 * delay this because bit 0 of the stream should not be processed
1468 * so we do not add the vlan until after bit 0 was processed
1469 */
1470 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1471
1472 /* Process remaining 30 bit of the key */
1473 IXGBE_COMPUTE_BKT_HASH_ITERATION(1);
1474 IXGBE_COMPUTE_BKT_HASH_ITERATION(2);
1475 IXGBE_COMPUTE_BKT_HASH_ITERATION(3);
1476 IXGBE_COMPUTE_BKT_HASH_ITERATION(4);
1477 IXGBE_COMPUTE_BKT_HASH_ITERATION(5);
1478 IXGBE_COMPUTE_BKT_HASH_ITERATION(6);
1479 IXGBE_COMPUTE_BKT_HASH_ITERATION(7);
1480 IXGBE_COMPUTE_BKT_HASH_ITERATION(8);
1481 IXGBE_COMPUTE_BKT_HASH_ITERATION(9);
1482 IXGBE_COMPUTE_BKT_HASH_ITERATION(10);
1483 IXGBE_COMPUTE_BKT_HASH_ITERATION(11);
1484 IXGBE_COMPUTE_BKT_HASH_ITERATION(12);
1485 IXGBE_COMPUTE_BKT_HASH_ITERATION(13);
1486 IXGBE_COMPUTE_BKT_HASH_ITERATION(14);
1487 IXGBE_COMPUTE_BKT_HASH_ITERATION(15);
1488
1489 /*
1490 * Limit hash to 13 bits since max bucket count is 8K.
1491 * Store result at the end of the input stream.
1492 */
1493 input->formatted.bkt_hash = bucket_hash & 0x1FFF;
1494 }
1495
1496 /**
1497 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1498 * @input_mask: mask to be bit swapped
1499 *
1500 * The source and destination port masks for flow director are bit swapped
1501 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1502 * generate a correctly swapped value we need to bit swap the mask and that
1503 * is what is accomplished by this function.
1504 **/
1505 static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
1506 {
1507 u32 mask = IXGBE_NTOHS(input_mask->formatted.dst_port);
1508 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1509 mask |= IXGBE_NTOHS(input_mask->formatted.src_port);
1510 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1511 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1512 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1513 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1514 }
1515
1516 /*
1517 * These two macros are meant to address the fact that we have registers
1518 * that are either all or in part big-endian. As a result on big-endian
1519 * systems we will end up byte swapping the value to little-endian before
1520 * it is byte swapped again and written to the hardware in the original
1521 * big-endian format.
1522 */
1523 #define IXGBE_STORE_AS_BE32(_value) \
1524 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1525 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1526
1527 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1528 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value)))
1529
1530 #define IXGBE_STORE_AS_BE16(_value) \
1531 IXGBE_NTOHS(((u16)(_value) >> 8) | ((u16)(_value) << 8))
1532
1533 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
1534 union ixgbe_atr_input *input_mask)
1535 {
1536 /* mask IPv6 since it is currently not supported */
1537 u32 fdirm = IXGBE_FDIRM_DIPv6;
1538 u32 fdirtcpm;
1539
1540 /*
1541 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1542 * are zero, then assume a full mask for that field. Also assume that
1543 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1544 * cannot be masked out in this implementation.
1545 *
1546 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1547 * point in time.
1548 */
1549
1550 /* verify bucket hash is cleared on hash generation */
1551 if (input_mask->formatted.bkt_hash)
1552 hw_dbg(hw, " bucket hash should always be 0 in mask\n");
1553
1554 /* Program FDIRM and verify partial masks */
1555 switch (input_mask->formatted.vm_pool & 0x7F) {
1556 case 0x0:
1557 fdirm |= IXGBE_FDIRM_POOL;
1558 case 0x7F:
1559 break;
1560 default:
1561 hw_dbg(hw, " Error on vm pool mask\n");
1562 return IXGBE_ERR_CONFIG;
1563 }
1564
1565 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {
1566 case 0x0:
1567 fdirm |= IXGBE_FDIRM_L4P;
1568 if (input_mask->formatted.dst_port ||
1569 input_mask->formatted.src_port) {
1570 hw_dbg(hw, " Error on src/dst port mask\n");
1571 return IXGBE_ERR_CONFIG;
1572 }
1573 case IXGBE_ATR_L4TYPE_MASK:
1574 break;
1575 default:
1576 hw_dbg(hw, " Error on flow type mask\n");
1577 return IXGBE_ERR_CONFIG;
1578 }
1579
1580 switch (IXGBE_NTOHS(input_mask->formatted.vlan_id) & 0xEFFF) {
1581 case 0x0000:
1582 /* mask VLAN ID, fall through to mask VLAN priority */
1583 fdirm |= IXGBE_FDIRM_VLANID;
1584 case 0x0FFF:
1585 /* mask VLAN priority */
1586 fdirm |= IXGBE_FDIRM_VLANP;
1587 break;
1588 case 0xE000:
1589 /* mask VLAN ID only, fall through */
1590 fdirm |= IXGBE_FDIRM_VLANID;
1591 case 0xEFFF:
1592 /* no VLAN fields masked */
1593 break;
1594 default:
1595 hw_dbg(hw, " Error on VLAN mask\n");
1596 return IXGBE_ERR_CONFIG;
1597 }
1598
1599 switch (input_mask->formatted.flex_bytes & 0xFFFF) {
1600 case 0x0000:
1601 /* Mask Flex Bytes, fall through */
1602 fdirm |= IXGBE_FDIRM_FLEX;
1603 case 0xFFFF:
1604 break;
1605 default:
1606 hw_dbg(hw, " Error on flexible byte mask\n");
1607 return IXGBE_ERR_CONFIG;
1608 }
1609
1610 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1611 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1612
1613 /* store the TCP/UDP port masks, bit reversed from port layout */
1614 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
1615
1616 /* write both the same so that UDP and TCP use the same mask */
1617 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1618 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1619
1620 /* store source and destination IP masks (big-enian) */
1621 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1622 ~input_mask->formatted.src_ip[0]);
1623 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1624 ~input_mask->formatted.dst_ip[0]);
1625
1626 return 0;
1627 }
1628
1629 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
1630 union ixgbe_atr_input *input,
1631 u16 soft_id, u8 queue)
1632 {
1633 u32 fdirport, fdirvlan, fdirhash, fdircmd;
1634
1635 /* currently IPv6 is not supported, must be programmed with 0 */
1636 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
1637 input->formatted.src_ip[0]);
1638 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
1639 input->formatted.src_ip[1]);
1640 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
1641 input->formatted.src_ip[2]);
1642
1643 /* record the source address (big-endian) */
1644 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
1645
1646 /* record the first 32 bits of the destination address (big-endian) */
1647 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
1648
1649 /* record source and destination port (little-endian)*/
1650 fdirport = IXGBE_NTOHS(input->formatted.dst_port);
1651 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1652 fdirport |= IXGBE_NTOHS(input->formatted.src_port);
1653 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1654
1655 /* record vlan (little-endian) and flex_bytes(big-endian) */
1656 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
1657 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1658 fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
1659 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1660
1661 /* configure FDIRHASH register */
1662 fdirhash = input->formatted.bkt_hash;
1663 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1664 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1665
1666 /*
1667 * flush all previous writes to make certain registers are
1668 * programmed prior to issuing the command
1669 */
1670 IXGBE_WRITE_FLUSH(hw);
1671
1672 /* configure FDIRCMD register */
1673 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1674 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1675 if (queue == IXGBE_FDIR_DROP_QUEUE)
1676 fdircmd |= IXGBE_FDIRCMD_DROP;
1677 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1678 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1679 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
1680
1681 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1682
1683 return 0;
1684 }
1685
1686 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
1687 union ixgbe_atr_input *input,
1688 u16 soft_id)
1689 {
1690 u32 fdirhash;
1691 u32 fdircmd = 0;
1692 u32 retry_count;
1693 s32 err = 0;
1694
1695 /* configure FDIRHASH register */
1696 fdirhash = input->formatted.bkt_hash;
1697 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1698 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1699
1700 /* flush hash to HW */
1701 IXGBE_WRITE_FLUSH(hw);
1702
1703 /* Query if filter is present */
1704 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
1705
1706 for (retry_count = 10; retry_count; retry_count--) {
1707 /* allow 10us for query to process */
1708 udelay(10);
1709 /* verify query completed successfully */
1710 fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
1711 if (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK))
1712 break;
1713 }
1714
1715 if (!retry_count)
1716 err = IXGBE_ERR_FDIR_REINIT_FAILED;
1717
1718 /* if filter exists in hardware then remove it */
1719 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
1720 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1721 IXGBE_WRITE_FLUSH(hw);
1722 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1723 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
1724 }
1725
1726 return err;
1727 }
1728
1729 /**
1730 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1731 * @hw: pointer to hardware structure
1732 * @input: input bitstream
1733 * @input_mask: mask for the input bitstream
1734 * @soft_id: software index for the filters
1735 * @queue: queue index to direct traffic to
1736 *
1737 * Note that the caller to this function must lock before calling, since the
1738 * hardware writes must be protected from one another.
1739 **/
1740 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
1741 union ixgbe_atr_input *input,
1742 union ixgbe_atr_input *input_mask,
1743 u16 soft_id, u8 queue)
1744 {
1745 s32 err = IXGBE_ERR_CONFIG;
1746
1747 /*
1748 * Check flow_type formatting, and bail out before we touch the hardware
1749 * if there's a configuration issue
1750 */
1751 switch (input->formatted.flow_type) {
1752 case IXGBE_ATR_FLOW_TYPE_IPV4:
1753 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK;
1754 if (input->formatted.dst_port || input->formatted.src_port) {
1755 hw_dbg(hw, " Error on src/dst port\n");
1756 return IXGBE_ERR_CONFIG;
1757 }
1758 break;
1759 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1760 if (input->formatted.dst_port || input->formatted.src_port) {
1761 hw_dbg(hw, " Error on src/dst port\n");
1762 return IXGBE_ERR_CONFIG;
1763 }
1764 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1765 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1766 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
1767 IXGBE_ATR_L4TYPE_MASK;
1768 break;
1769 default:
1770 hw_dbg(hw, " Error on flow type input\n");
1771 return err;
1772 }
1773
1774 /* program input mask into the HW */
1775 err = ixgbe_fdir_set_input_mask_82599(hw, input_mask);
1776 if (err)
1777 return err;
1778
1779 /* apply mask and compute/store hash */
1780 ixgbe_atr_compute_perfect_hash_82599(input, input_mask);
1781
1782 /* program filters to filter memory */
1783 return ixgbe_fdir_write_perfect_filter_82599(hw, input,
1784 soft_id, queue);
1785 }
1786
1787 /**
1788 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1789 * @hw: pointer to hardware structure
1790 * @reg: analog register to read
1791 * @val: read value
1792 *
1793 * Performs read operation to Omer analog register specified.
1794 **/
1795 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1796 {
1797 u32 core_ctl;
1798
1799 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1800 (reg << 8));
1801 IXGBE_WRITE_FLUSH(hw);
1802 udelay(10);
1803 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1804 *val = (u8)core_ctl;
1805
1806 return 0;
1807 }
1808
1809 /**
1810 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1811 * @hw: pointer to hardware structure
1812 * @reg: atlas register to write
1813 * @val: value to write
1814 *
1815 * Performs write operation to Omer analog register specified.
1816 **/
1817 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1818 {
1819 u32 core_ctl;
1820
1821 core_ctl = (reg << 8) | val;
1822 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1823 IXGBE_WRITE_FLUSH(hw);
1824 udelay(10);
1825
1826 return 0;
1827 }
1828
1829 /**
1830 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1831 * @hw: pointer to hardware structure
1832 *
1833 * Starts the hardware using the generic start_hw function
1834 * and the generation start_hw function.
1835 * Then performs revision-specific operations, if any.
1836 **/
1837 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1838 {
1839 s32 ret_val = 0;
1840
1841 ret_val = ixgbe_start_hw_generic(hw);
1842 if (ret_val != 0)
1843 goto out;
1844
1845 ret_val = ixgbe_start_hw_gen2(hw);
1846 if (ret_val != 0)
1847 goto out;
1848
1849 /* We need to run link autotry after the driver loads */
1850 hw->mac.autotry_restart = true;
1851
1852 if (ret_val == 0)
1853 ret_val = ixgbe_verify_fw_version_82599(hw);
1854 out:
1855 return ret_val;
1856 }
1857
1858 /**
1859 * ixgbe_identify_phy_82599 - Get physical layer module
1860 * @hw: pointer to hardware structure
1861 *
1862 * Determines the physical layer module found on the current adapter.
1863 * If PHY already detected, maintains current PHY type in hw struct,
1864 * otherwise executes the PHY detection routine.
1865 **/
1866 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1867 {
1868 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1869
1870 /* Detect PHY if not unknown - returns success if already detected. */
1871 status = ixgbe_identify_phy_generic(hw);
1872 if (status != 0) {
1873 /* 82599 10GBASE-T requires an external PHY */
1874 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
1875 goto out;
1876 else
1877 status = ixgbe_identify_module_generic(hw);
1878 }
1879
1880 /* Set PHY type none if no PHY detected */
1881 if (hw->phy.type == ixgbe_phy_unknown) {
1882 hw->phy.type = ixgbe_phy_none;
1883 status = 0;
1884 }
1885
1886 /* Return error if SFP module has been detected but is not supported */
1887 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
1888 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1889
1890 out:
1891 return status;
1892 }
1893
1894 /**
1895 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1896 * @hw: pointer to hardware structure
1897 *
1898 * Determines physical layer capabilities of the current configuration.
1899 **/
1900 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
1901 {
1902 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1903 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1904 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1905 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
1906 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1907 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1908 u16 ext_ability = 0;
1909 u8 comp_codes_10g = 0;
1910 u8 comp_codes_1g = 0;
1911
1912 hw->phy.ops.identify(hw);
1913
1914 switch (hw->phy.type) {
1915 case ixgbe_phy_tn:
1916 case ixgbe_phy_cu_unknown:
1917 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
1918 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
1919 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
1920 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1921 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
1922 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1923 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
1924 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1925 goto out;
1926 default:
1927 break;
1928 }
1929
1930 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1931 case IXGBE_AUTOC_LMS_1G_AN:
1932 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1933 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
1934 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
1935 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1936 goto out;
1937 } else
1938 /* SFI mode so read SFP module */
1939 goto sfp_check;
1940 break;
1941 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1942 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
1943 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1944 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
1945 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1946 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
1947 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
1948 goto out;
1949 break;
1950 case IXGBE_AUTOC_LMS_10G_SERIAL:
1951 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
1952 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1953 goto out;
1954 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
1955 goto sfp_check;
1956 break;
1957 case IXGBE_AUTOC_LMS_KX4_KX_KR:
1958 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
1959 if (autoc & IXGBE_AUTOC_KX_SUPP)
1960 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1961 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1962 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1963 if (autoc & IXGBE_AUTOC_KR_SUPP)
1964 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1965 goto out;
1966 break;
1967 default:
1968 goto out;
1969 break;
1970 }
1971
1972 sfp_check:
1973 /* SFP check must be done last since DA modules are sometimes used to
1974 * test KR mode - we need to id KR mode correctly before SFP module.
1975 * Call identify_sfp because the pluggable module may have changed */
1976 hw->phy.ops.identify_sfp(hw);
1977 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1978 goto out;
1979
1980 switch (hw->phy.type) {
1981 case ixgbe_phy_sfp_passive_tyco:
1982 case ixgbe_phy_sfp_passive_unknown:
1983 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1984 break;
1985 case ixgbe_phy_sfp_ftl_active:
1986 case ixgbe_phy_sfp_active_unknown:
1987 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1988 break;
1989 case ixgbe_phy_sfp_avago:
1990 case ixgbe_phy_sfp_ftl:
1991 case ixgbe_phy_sfp_intel:
1992 case ixgbe_phy_sfp_unknown:
1993 hw->phy.ops.read_i2c_eeprom(hw,
1994 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1995 hw->phy.ops.read_i2c_eeprom(hw,
1996 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1997 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1998 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1999 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
2000 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
2001 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
2002 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
2003 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
2004 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
2005 break;
2006 default:
2007 break;
2008 }
2009
2010 out:
2011 return physical_layer;
2012 }
2013
2014 /**
2015 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2016 * @hw: pointer to hardware structure
2017 * @regval: register value to write to RXCTRL
2018 *
2019 * Enables the Rx DMA unit for 82599
2020 **/
2021 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
2022 {
2023
2024 /*
2025 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2026 * If traffic is incoming before we enable the Rx unit, it could hang
2027 * the Rx DMA unit. Therefore, make sure the security engine is
2028 * completely disabled prior to enabling the Rx unit.
2029 */
2030
2031 hw->mac.ops.disable_sec_rx_path(hw);
2032
2033 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2034
2035 hw->mac.ops.enable_sec_rx_path(hw);
2036
2037 return 0;
2038 }
2039
2040 /**
2041 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2042 * @hw: pointer to hardware structure
2043 *
2044 * Verifies that installed the firmware version is 0.6 or higher
2045 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2046 *
2047 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2048 * if the FW version is not supported.
2049 **/
2050 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2051 {
2052 s32 status = IXGBE_ERR_EEPROM_VERSION;
2053 u16 fw_offset, fw_ptp_cfg_offset;
2054 u16 fw_version = 0;
2055
2056 /* firmware check is only necessary for SFI devices */
2057 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2058 status = 0;
2059 goto fw_version_out;
2060 }
2061
2062 /* get the offset to the Firmware Module block */
2063 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2064
2065 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2066 goto fw_version_out;
2067
2068 /* get the offset to the Pass Through Patch Configuration block */
2069 hw->eeprom.ops.read(hw, (fw_offset +
2070 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2071 &fw_ptp_cfg_offset);
2072
2073 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2074 goto fw_version_out;
2075
2076 /* get the firmware version */
2077 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2078 IXGBE_FW_PATCH_VERSION_4), &fw_version);
2079
2080 if (fw_version > 0x5)
2081 status = 0;
2082
2083 fw_version_out:
2084 return status;
2085 }
2086
2087 /**
2088 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2089 * @hw: pointer to hardware structure
2090 *
2091 * Returns true if the LESM FW module is present and enabled. Otherwise
2092 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
2093 **/
2094 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
2095 {
2096 bool lesm_enabled = false;
2097 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2098 s32 status;
2099
2100 /* get the offset to the Firmware Module block */
2101 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2102
2103 if ((status != 0) ||
2104 (fw_offset == 0) || (fw_offset == 0xFFFF))
2105 goto out;
2106
2107 /* get the offset to the LESM Parameters block */
2108 status = hw->eeprom.ops.read(hw, (fw_offset +
2109 IXGBE_FW_LESM_PARAMETERS_PTR),
2110 &fw_lesm_param_offset);
2111
2112 if ((status != 0) ||
2113 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
2114 goto out;
2115
2116 /* get the lesm state word */
2117 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2118 IXGBE_FW_LESM_STATE_1),
2119 &fw_lesm_state);
2120
2121 if ((status == 0) &&
2122 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
2123 lesm_enabled = true;
2124
2125 out:
2126 return lesm_enabled;
2127 }
2128
2129 /**
2130 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2131 * fastest available method
2132 *
2133 * @hw: pointer to hardware structure
2134 * @offset: offset of word in EEPROM to read
2135 * @words: number of words
2136 * @data: word(s) read from the EEPROM
2137 *
2138 * Retrieves 16 bit word(s) read from EEPROM
2139 **/
2140 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
2141 u16 words, u16 *data)
2142 {
2143 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2144 s32 ret_val = IXGBE_ERR_CONFIG;
2145
2146 /*
2147 * If EEPROM is detected and can be addressed using 14 bits,
2148 * use EERD otherwise use bit bang
2149 */
2150 if ((eeprom->type == ixgbe_eeprom_spi) &&
2151 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
2152 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
2153 data);
2154 else
2155 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
2156 words,
2157 data);
2158
2159 return ret_val;
2160 }
2161
2162 /**
2163 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2164 * fastest available method
2165 *
2166 * @hw: pointer to hardware structure
2167 * @offset: offset of word in the EEPROM to read
2168 * @data: word read from the EEPROM
2169 *
2170 * Reads a 16 bit word from the EEPROM
2171 **/
2172 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2173 u16 offset, u16 *data)
2174 {
2175 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2176 s32 ret_val = IXGBE_ERR_CONFIG;
2177
2178 /*
2179 * If EEPROM is detected and can be addressed using 14 bits,
2180 * use EERD otherwise use bit bang
2181 */
2182 if ((eeprom->type == ixgbe_eeprom_spi) &&
2183 (offset <= IXGBE_EERD_MAX_ADDR))
2184 ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2185 else
2186 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2187
2188 return ret_val;
2189 }
2190
2191 /**
2192 * ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C
2193 * @hw: pointer to hardware structure
2194 * @byte_offset: byte offset to read
2195 * @data: value read
2196 *
2197 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2198 * a specified device address.
2199 **/
2200 static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
2201 u8 dev_addr, u8 *data)
2202 {
2203 u32 esdp;
2204 s32 status;
2205 s32 timeout = 200;
2206
2207 if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
2208 /* Acquire I2C bus ownership. */
2209 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2210 esdp |= IXGBE_ESDP_SDP0;
2211 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2212 IXGBE_WRITE_FLUSH(hw);
2213
2214 while (timeout) {
2215 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2216 if (esdp & IXGBE_ESDP_SDP1)
2217 break;
2218
2219 msleep(5);
2220 timeout--;
2221 }
2222
2223 if (!timeout) {
2224 hw_dbg(hw, "Driver can't access resource,"
2225 " acquiring I2C bus timeout.\n");
2226 status = IXGBE_ERR_I2C;
2227 goto release_i2c_access;
2228 }
2229 }
2230
2231 status = ixgbe_read_i2c_byte_generic(hw, byte_offset, dev_addr, data);
2232
2233 release_i2c_access:
2234
2235 if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
2236 /* Release I2C bus ownership. */
2237 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2238 esdp &= ~IXGBE_ESDP_SDP0;
2239 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2240 IXGBE_WRITE_FLUSH(hw);
2241 }
2242
2243 return status;
2244 }
2245
2246 /**
2247 * ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C
2248 * @hw: pointer to hardware structure
2249 * @byte_offset: byte offset to write
2250 * @data: value to write
2251 *
2252 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2253 * a specified device address.
2254 **/
2255 static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
2256 u8 dev_addr, u8 data)
2257 {
2258 u32 esdp;
2259 s32 status;
2260 s32 timeout = 200;
2261
2262 if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
2263 /* Acquire I2C bus ownership. */
2264 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2265 esdp |= IXGBE_ESDP_SDP0;
2266 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2267 IXGBE_WRITE_FLUSH(hw);
2268
2269 while (timeout) {
2270 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2271 if (esdp & IXGBE_ESDP_SDP1)
2272 break;
2273
2274 msleep(5);
2275 timeout--;
2276 }
2277
2278 if (!timeout) {
2279 hw_dbg(hw, "Driver can't access resource,"
2280 " acquiring I2C bus timeout.\n");
2281 status = IXGBE_ERR_I2C;
2282 goto release_i2c_access;
2283 }
2284 }
2285
2286 status = ixgbe_write_i2c_byte_generic(hw, byte_offset, dev_addr, data);
2287
2288 release_i2c_access:
2289
2290 if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
2291 /* Release I2C bus ownership. */
2292 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2293 esdp &= ~IXGBE_ESDP_SDP0;
2294 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2295 IXGBE_WRITE_FLUSH(hw);
2296 }
2297
2298 return status;
2299 }
Ceph