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[ceph.git] / ceph / src / spdk / dpdk / drivers / net / sfc / base / efx_impl.h
1 /* SPDX-License-Identifier: BSD-3-Clause
2 *
3 * Copyright (c) 2007-2018 Solarflare Communications Inc.
4 * All rights reserved.
5 */
6
7 #ifndef _SYS_EFX_IMPL_H
8 #define _SYS_EFX_IMPL_H
9
10 #include "efx.h"
11 #include "efx_regs.h"
12 #include "efx_regs_ef10.h"
13 #if EFSYS_OPT_MCDI
14 #include "efx_mcdi.h"
15 #endif /* EFSYS_OPT_MCDI */
16
17 /* FIXME: Add definition for driver generated software events */
18 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
19 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
20 #endif
21
22
23 #if EFSYS_OPT_SIENA
24 #include "siena_impl.h"
25 #endif /* EFSYS_OPT_SIENA */
26
27 #if EFSYS_OPT_HUNTINGTON
28 #include "hunt_impl.h"
29 #endif /* EFSYS_OPT_HUNTINGTON */
30
31 #if EFSYS_OPT_MEDFORD
32 #include "medford_impl.h"
33 #endif /* EFSYS_OPT_MEDFORD */
34
35 #if EFSYS_OPT_MEDFORD2
36 #include "medford2_impl.h"
37 #endif /* EFSYS_OPT_MEDFORD2 */
38
39 #if EFX_OPTS_EF10()
40 #include "ef10_impl.h"
41 #endif /* EFX_OPTS_EF10() */
42
43 #ifdef __cplusplus
44 extern "C" {
45 #endif
46
47 #define EFX_MOD_MCDI 0x00000001
48 #define EFX_MOD_PROBE 0x00000002
49 #define EFX_MOD_NVRAM 0x00000004
50 #define EFX_MOD_VPD 0x00000008
51 #define EFX_MOD_NIC 0x00000010
52 #define EFX_MOD_INTR 0x00000020
53 #define EFX_MOD_EV 0x00000040
54 #define EFX_MOD_RX 0x00000080
55 #define EFX_MOD_TX 0x00000100
56 #define EFX_MOD_PORT 0x00000200
57 #define EFX_MOD_MON 0x00000400
58 #define EFX_MOD_FILTER 0x00001000
59 #define EFX_MOD_LIC 0x00002000
60 #define EFX_MOD_TUNNEL 0x00004000
61
62 #define EFX_RESET_PHY 0x00000001
63 #define EFX_RESET_RXQ_ERR 0x00000002
64 #define EFX_RESET_TXQ_ERR 0x00000004
65 #define EFX_RESET_HW_UNAVAIL 0x00000008
66
67 typedef enum efx_mac_type_e {
68 EFX_MAC_INVALID = 0,
69 EFX_MAC_SIENA,
70 EFX_MAC_HUNTINGTON,
71 EFX_MAC_MEDFORD,
72 EFX_MAC_MEDFORD2,
73 EFX_MAC_NTYPES
74 } efx_mac_type_t;
75
76 typedef struct efx_ev_ops_s {
77 efx_rc_t (*eevo_init)(efx_nic_t *);
78 void (*eevo_fini)(efx_nic_t *);
79 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int,
80 efsys_mem_t *, size_t, uint32_t,
81 uint32_t, uint32_t, efx_evq_t *);
82 void (*eevo_qdestroy)(efx_evq_t *);
83 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int);
84 void (*eevo_qpost)(efx_evq_t *, uint16_t);
85 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int);
86 #if EFSYS_OPT_QSTATS
87 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
88 #endif
89 } efx_ev_ops_t;
90
91 typedef struct efx_tx_ops_s {
92 efx_rc_t (*etxo_init)(efx_nic_t *);
93 void (*etxo_fini)(efx_nic_t *);
94 efx_rc_t (*etxo_qcreate)(efx_nic_t *,
95 unsigned int, unsigned int,
96 efsys_mem_t *, size_t,
97 uint32_t, uint16_t,
98 efx_evq_t *, efx_txq_t *,
99 unsigned int *);
100 void (*etxo_qdestroy)(efx_txq_t *);
101 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
102 unsigned int, unsigned int,
103 unsigned int *);
104 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
105 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int);
106 efx_rc_t (*etxo_qflush)(efx_txq_t *);
107 void (*etxo_qenable)(efx_txq_t *);
108 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *);
109 void (*etxo_qpio_disable)(efx_txq_t *);
110 efx_rc_t (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
111 size_t);
112 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
113 unsigned int *);
114 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
115 unsigned int, unsigned int,
116 unsigned int *);
117 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
118 size_t, boolean_t,
119 efx_desc_t *);
120 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
121 uint32_t, uint8_t,
122 efx_desc_t *);
123 void (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
124 uint16_t, uint32_t, uint16_t,
125 efx_desc_t *, int);
126 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
127 efx_desc_t *);
128 void (*etxo_qdesc_checksum_create)(efx_txq_t *, uint16_t,
129 efx_desc_t *);
130 #if EFSYS_OPT_QSTATS
131 void (*etxo_qstats_update)(efx_txq_t *,
132 efsys_stat_t *);
133 #endif
134 } efx_tx_ops_t;
135
136 typedef union efx_rxq_type_data_u {
137 struct {
138 size_t ed_buf_size;
139 } ertd_default;
140 #if EFSYS_OPT_RX_PACKED_STREAM
141 struct {
142 uint32_t eps_buf_size;
143 } ertd_packed_stream;
144 #endif
145 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
146 struct {
147 uint32_t eessb_bufs_per_desc;
148 uint32_t eessb_max_dma_len;
149 uint32_t eessb_buf_stride;
150 uint32_t eessb_hol_block_timeout;
151 } ertd_es_super_buffer;
152 #endif
153 } efx_rxq_type_data_t;
154
155 typedef struct efx_rx_ops_s {
156 efx_rc_t (*erxo_init)(efx_nic_t *);
157 void (*erxo_fini)(efx_nic_t *);
158 #if EFSYS_OPT_RX_SCATTER
159 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
160 #endif
161 #if EFSYS_OPT_RX_SCALE
162 efx_rc_t (*erxo_scale_context_alloc)(efx_nic_t *,
163 efx_rx_scale_context_type_t,
164 uint32_t, uint32_t *);
165 efx_rc_t (*erxo_scale_context_free)(efx_nic_t *, uint32_t);
166 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, uint32_t,
167 efx_rx_hash_alg_t,
168 efx_rx_hash_type_t, boolean_t);
169 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint32_t,
170 uint8_t *, size_t);
171 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t,
172 unsigned int *, size_t);
173 uint32_t (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
174 uint8_t *);
175 #endif /* EFSYS_OPT_RX_SCALE */
176 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
177 uint16_t *);
178 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
179 unsigned int, unsigned int,
180 unsigned int);
181 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
182 #if EFSYS_OPT_RX_PACKED_STREAM
183 void (*erxo_qpush_ps_credits)(efx_rxq_t *);
184 uint8_t * (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *,
185 uint32_t, uint32_t,
186 uint16_t *, uint32_t *, uint32_t *);
187 #endif
188 efx_rc_t (*erxo_qflush)(efx_rxq_t *);
189 void (*erxo_qenable)(efx_rxq_t *);
190 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
191 unsigned int, efx_rxq_type_t,
192 const efx_rxq_type_data_t *,
193 efsys_mem_t *, size_t, uint32_t,
194 unsigned int,
195 efx_evq_t *, efx_rxq_t *);
196 void (*erxo_qdestroy)(efx_rxq_t *);
197 } efx_rx_ops_t;
198
199 typedef struct efx_mac_ops_s {
200 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
201 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *);
202 efx_rc_t (*emo_addr_set)(efx_nic_t *);
203 efx_rc_t (*emo_pdu_set)(efx_nic_t *);
204 efx_rc_t (*emo_pdu_get)(efx_nic_t *, size_t *);
205 efx_rc_t (*emo_reconfigure)(efx_nic_t *);
206 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *);
207 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *,
208 efx_rxq_t *, boolean_t);
209 void (*emo_filter_default_rxq_clear)(efx_nic_t *);
210 #if EFSYS_OPT_LOOPBACK
211 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
212 efx_loopback_type_t);
213 #endif /* EFSYS_OPT_LOOPBACK */
214 #if EFSYS_OPT_MAC_STATS
215 efx_rc_t (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
216 efx_rc_t (*emo_stats_clear)(efx_nic_t *);
217 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
218 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
219 uint16_t, boolean_t);
220 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
221 efsys_stat_t *, uint32_t *);
222 #endif /* EFSYS_OPT_MAC_STATS */
223 } efx_mac_ops_t;
224
225 typedef struct efx_phy_ops_s {
226 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */
227 efx_rc_t (*epo_reset)(efx_nic_t *);
228 efx_rc_t (*epo_reconfigure)(efx_nic_t *);
229 efx_rc_t (*epo_verify)(efx_nic_t *);
230 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *);
231 efx_rc_t (*epo_link_state_get)(efx_nic_t *, efx_phy_link_state_t *);
232 #if EFSYS_OPT_PHY_STATS
233 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
234 uint32_t *);
235 #endif /* EFSYS_OPT_PHY_STATS */
236 #if EFSYS_OPT_BIST
237 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *);
238 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
239 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
240 efx_bist_result_t *, uint32_t *,
241 unsigned long *, size_t);
242 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
243 #endif /* EFSYS_OPT_BIST */
244 } efx_phy_ops_t;
245
246 #if EFSYS_OPT_FILTER
247 typedef struct efx_filter_ops_s {
248 efx_rc_t (*efo_init)(efx_nic_t *);
249 void (*efo_fini)(efx_nic_t *);
250 efx_rc_t (*efo_restore)(efx_nic_t *);
251 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
252 boolean_t may_replace);
253 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
254 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *,
255 size_t, size_t *);
256 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
257 boolean_t, boolean_t, boolean_t,
258 uint8_t const *, uint32_t);
259 } efx_filter_ops_t;
260
261 extern __checkReturn efx_rc_t
262 efx_filter_reconfigure(
263 __in efx_nic_t *enp,
264 __in_ecount(6) uint8_t const *mac_addr,
265 __in boolean_t all_unicst,
266 __in boolean_t mulcst,
267 __in boolean_t all_mulcst,
268 __in boolean_t brdcst,
269 __in_ecount(6*count) uint8_t const *addrs,
270 __in uint32_t count);
271
272 #endif /* EFSYS_OPT_FILTER */
273
274 #if EFSYS_OPT_TUNNEL
275 typedef struct efx_tunnel_ops_s {
276 boolean_t (*eto_udp_encap_supported)(efx_nic_t *);
277 efx_rc_t (*eto_reconfigure)(efx_nic_t *);
278 } efx_tunnel_ops_t;
279 #endif /* EFSYS_OPT_TUNNEL */
280
281 typedef struct efx_port_s {
282 efx_mac_type_t ep_mac_type;
283 uint32_t ep_phy_type;
284 uint8_t ep_port;
285 uint32_t ep_mac_pdu;
286 uint8_t ep_mac_addr[6];
287 efx_link_mode_t ep_link_mode;
288 boolean_t ep_all_unicst;
289 boolean_t ep_mulcst;
290 boolean_t ep_all_mulcst;
291 boolean_t ep_brdcst;
292 unsigned int ep_fcntl;
293 boolean_t ep_fcntl_autoneg;
294 efx_oword_t ep_multicst_hash[2];
295 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
296 EFX_MAC_MULTICAST_LIST_MAX];
297 uint32_t ep_mulcst_addr_count;
298 #if EFSYS_OPT_LOOPBACK
299 efx_loopback_type_t ep_loopback_type;
300 efx_link_mode_t ep_loopback_link_mode;
301 #endif /* EFSYS_OPT_LOOPBACK */
302 #if EFSYS_OPT_PHY_FLAGS
303 uint32_t ep_phy_flags;
304 #endif /* EFSYS_OPT_PHY_FLAGS */
305 #if EFSYS_OPT_PHY_LED_CONTROL
306 efx_phy_led_mode_t ep_phy_led_mode;
307 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
308 efx_phy_media_type_t ep_fixed_port_type;
309 efx_phy_media_type_t ep_module_type;
310 uint32_t ep_adv_cap_mask;
311 uint32_t ep_lp_cap_mask;
312 uint32_t ep_default_adv_cap_mask;
313 uint32_t ep_phy_cap_mask;
314 boolean_t ep_mac_drain;
315 #if EFSYS_OPT_BIST
316 efx_bist_type_t ep_current_bist;
317 #endif
318 const efx_mac_ops_t *ep_emop;
319 const efx_phy_ops_t *ep_epop;
320 } efx_port_t;
321
322 typedef struct efx_mon_ops_s {
323 #if EFSYS_OPT_MON_STATS
324 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
325 efx_mon_stat_value_t *);
326 efx_rc_t (*emo_limits_update)(efx_nic_t *,
327 efx_mon_stat_limits_t *);
328 #endif /* EFSYS_OPT_MON_STATS */
329 } efx_mon_ops_t;
330
331 typedef struct efx_mon_s {
332 efx_mon_type_t em_type;
333 const efx_mon_ops_t *em_emop;
334 } efx_mon_t;
335
336 typedef struct efx_intr_ops_s {
337 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
338 void (*eio_enable)(efx_nic_t *);
339 void (*eio_disable)(efx_nic_t *);
340 void (*eio_disable_unlocked)(efx_nic_t *);
341 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int);
342 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
343 void (*eio_status_message)(efx_nic_t *, unsigned int,
344 boolean_t *);
345 void (*eio_fatal)(efx_nic_t *);
346 void (*eio_fini)(efx_nic_t *);
347 } efx_intr_ops_t;
348
349 typedef struct efx_intr_s {
350 const efx_intr_ops_t *ei_eiop;
351 efsys_mem_t *ei_esmp;
352 efx_intr_type_t ei_type;
353 unsigned int ei_level;
354 } efx_intr_t;
355
356 typedef struct efx_nic_ops_s {
357 efx_rc_t (*eno_probe)(efx_nic_t *);
358 efx_rc_t (*eno_board_cfg)(efx_nic_t *);
359 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
360 efx_rc_t (*eno_reset)(efx_nic_t *);
361 efx_rc_t (*eno_init)(efx_nic_t *);
362 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
363 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
364 uint32_t *, size_t *);
365 boolean_t (*eno_hw_unavailable)(efx_nic_t *);
366 void (*eno_set_hw_unavailable)(efx_nic_t *);
367 #if EFSYS_OPT_DIAG
368 efx_rc_t (*eno_register_test)(efx_nic_t *);
369 #endif /* EFSYS_OPT_DIAG */
370 void (*eno_fini)(efx_nic_t *);
371 void (*eno_unprobe)(efx_nic_t *);
372 } efx_nic_ops_t;
373
374 #ifndef EFX_TXQ_LIMIT_TARGET
375 #define EFX_TXQ_LIMIT_TARGET 259
376 #endif
377 #ifndef EFX_RXQ_LIMIT_TARGET
378 #define EFX_RXQ_LIMIT_TARGET 512
379 #endif
380
381
382 #if EFSYS_OPT_FILTER
383
384 #if EFSYS_OPT_SIENA
385
386 typedef struct siena_filter_spec_s {
387 uint8_t sfs_type;
388 uint32_t sfs_flags;
389 uint32_t sfs_dmaq_id;
390 uint32_t sfs_dword[3];
391 } siena_filter_spec_t;
392
393 typedef enum siena_filter_type_e {
394 EFX_SIENA_FILTER_RX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
395 EFX_SIENA_FILTER_RX_TCP_WILD, /* TCP/IPv4 {dIP,dTCP, -, -} */
396 EFX_SIENA_FILTER_RX_UDP_FULL, /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
397 EFX_SIENA_FILTER_RX_UDP_WILD, /* UDP/IPv4 {dIP,dUDP, -, -} */
398 EFX_SIENA_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */
399 EFX_SIENA_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */
400
401 EFX_SIENA_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
402 EFX_SIENA_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */
403 EFX_SIENA_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
404 EFX_SIENA_FILTER_TX_UDP_WILD, /* UDP/IPv4 { -, -,sIP,sUDP} */
405 EFX_SIENA_FILTER_TX_MAC_FULL, /* Ethernet {sMAC,VLAN} */
406 EFX_SIENA_FILTER_TX_MAC_WILD, /* Ethernet {sMAC, -} */
407
408 EFX_SIENA_FILTER_NTYPES
409 } siena_filter_type_t;
410
411 typedef enum siena_filter_tbl_id_e {
412 EFX_SIENA_FILTER_TBL_RX_IP = 0,
413 EFX_SIENA_FILTER_TBL_RX_MAC,
414 EFX_SIENA_FILTER_TBL_TX_IP,
415 EFX_SIENA_FILTER_TBL_TX_MAC,
416 EFX_SIENA_FILTER_NTBLS
417 } siena_filter_tbl_id_t;
418
419 typedef struct siena_filter_tbl_s {
420 int sft_size; /* number of entries */
421 int sft_used; /* active count */
422 uint32_t *sft_bitmap; /* active bitmap */
423 siena_filter_spec_t *sft_spec; /* array of saved specs */
424 } siena_filter_tbl_t;
425
426 typedef struct siena_filter_s {
427 siena_filter_tbl_t sf_tbl[EFX_SIENA_FILTER_NTBLS];
428 unsigned int sf_depth[EFX_SIENA_FILTER_NTYPES];
429 } siena_filter_t;
430
431 #endif /* EFSYS_OPT_SIENA */
432
433 typedef struct efx_filter_s {
434 #if EFSYS_OPT_SIENA
435 siena_filter_t *ef_siena_filter;
436 #endif /* EFSYS_OPT_SIENA */
437 #if EFX_OPTS_EF10()
438 ef10_filter_table_t *ef_ef10_filter_table;
439 #endif /* EFX_OPTS_EF10() */
440 } efx_filter_t;
441
442 #if EFSYS_OPT_SIENA
443
444 extern void
445 siena_filter_tbl_clear(
446 __in efx_nic_t *enp,
447 __in siena_filter_tbl_id_t tbl);
448
449 #endif /* EFSYS_OPT_SIENA */
450
451 #endif /* EFSYS_OPT_FILTER */
452
453 #if EFSYS_OPT_MCDI
454
455 #define EFX_TUNNEL_MAXNENTRIES (16)
456
457 #if EFSYS_OPT_TUNNEL
458
459 typedef struct efx_tunnel_udp_entry_s {
460 uint16_t etue_port; /* host/cpu-endian */
461 uint16_t etue_protocol;
462 } efx_tunnel_udp_entry_t;
463
464 typedef struct efx_tunnel_cfg_s {
465 efx_tunnel_udp_entry_t etc_udp_entries[EFX_TUNNEL_MAXNENTRIES];
466 unsigned int etc_udp_entries_num;
467 } efx_tunnel_cfg_t;
468
469 #endif /* EFSYS_OPT_TUNNEL */
470
471 typedef struct efx_mcdi_ops_s {
472 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
473 void (*emco_send_request)(efx_nic_t *, void *, size_t,
474 void *, size_t);
475 efx_rc_t (*emco_poll_reboot)(efx_nic_t *);
476 boolean_t (*emco_poll_response)(efx_nic_t *);
477 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
478 void (*emco_fini)(efx_nic_t *);
479 efx_rc_t (*emco_feature_supported)(efx_nic_t *,
480 efx_mcdi_feature_id_t, boolean_t *);
481 void (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
482 uint32_t *);
483 } efx_mcdi_ops_t;
484
485 typedef struct efx_mcdi_s {
486 const efx_mcdi_ops_t *em_emcop;
487 const efx_mcdi_transport_t *em_emtp;
488 efx_mcdi_iface_t em_emip;
489 } efx_mcdi_t;
490
491 #endif /* EFSYS_OPT_MCDI */
492
493 #if EFSYS_OPT_NVRAM
494
495 /* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */
496 #define EFX_NVRAM_PARTN_INVALID (0xffffffffu)
497
498 typedef struct efx_nvram_ops_s {
499 #if EFSYS_OPT_DIAG
500 efx_rc_t (*envo_test)(efx_nic_t *);
501 #endif /* EFSYS_OPT_DIAG */
502 efx_rc_t (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
503 uint32_t *);
504 efx_rc_t (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);
505 efx_rc_t (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
506 efx_rc_t (*envo_partn_read)(efx_nic_t *, uint32_t,
507 unsigned int, caddr_t, size_t);
508 efx_rc_t (*envo_partn_read_backup)(efx_nic_t *, uint32_t,
509 unsigned int, caddr_t, size_t);
510 efx_rc_t (*envo_partn_erase)(efx_nic_t *, uint32_t,
511 unsigned int, size_t);
512 efx_rc_t (*envo_partn_write)(efx_nic_t *, uint32_t,
513 unsigned int, caddr_t, size_t);
514 efx_rc_t (*envo_partn_rw_finish)(efx_nic_t *, uint32_t,
515 uint32_t *);
516 efx_rc_t (*envo_partn_get_version)(efx_nic_t *, uint32_t,
517 uint32_t *, uint16_t *);
518 efx_rc_t (*envo_partn_set_version)(efx_nic_t *, uint32_t,
519 uint16_t *);
520 efx_rc_t (*envo_buffer_validate)(uint32_t,
521 caddr_t, size_t);
522 } efx_nvram_ops_t;
523 #endif /* EFSYS_OPT_NVRAM */
524
525 #if EFSYS_OPT_VPD
526 typedef struct efx_vpd_ops_s {
527 efx_rc_t (*evpdo_init)(efx_nic_t *);
528 efx_rc_t (*evpdo_size)(efx_nic_t *, size_t *);
529 efx_rc_t (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
530 efx_rc_t (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
531 efx_rc_t (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
532 efx_rc_t (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
533 efx_vpd_value_t *);
534 efx_rc_t (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
535 efx_vpd_value_t *);
536 efx_rc_t (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
537 efx_vpd_value_t *, unsigned int *);
538 efx_rc_t (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
539 void (*evpdo_fini)(efx_nic_t *);
540 } efx_vpd_ops_t;
541 #endif /* EFSYS_OPT_VPD */
542
543 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
544
545 __checkReturn efx_rc_t
546 efx_mcdi_nvram_partitions(
547 __in efx_nic_t *enp,
548 __out_bcount(size) caddr_t data,
549 __in size_t size,
550 __out unsigned int *npartnp);
551
552 __checkReturn efx_rc_t
553 efx_mcdi_nvram_metadata(
554 __in efx_nic_t *enp,
555 __in uint32_t partn,
556 __out uint32_t *subtypep,
557 __out_ecount(4) uint16_t version[4],
558 __out_bcount_opt(size) char *descp,
559 __in size_t size);
560
561 __checkReturn efx_rc_t
562 efx_mcdi_nvram_info(
563 __in efx_nic_t *enp,
564 __in uint32_t partn,
565 __out_opt size_t *sizep,
566 __out_opt uint32_t *addressp,
567 __out_opt uint32_t *erase_sizep,
568 __out_opt uint32_t *write_sizep);
569
570 __checkReturn efx_rc_t
571 efx_mcdi_nvram_update_start(
572 __in efx_nic_t *enp,
573 __in uint32_t partn);
574
575 __checkReturn efx_rc_t
576 efx_mcdi_nvram_read(
577 __in efx_nic_t *enp,
578 __in uint32_t partn,
579 __in uint32_t offset,
580 __out_bcount(size) caddr_t data,
581 __in size_t size,
582 __in uint32_t mode);
583
584 __checkReturn efx_rc_t
585 efx_mcdi_nvram_erase(
586 __in efx_nic_t *enp,
587 __in uint32_t partn,
588 __in uint32_t offset,
589 __in size_t size);
590
591 __checkReturn efx_rc_t
592 efx_mcdi_nvram_write(
593 __in efx_nic_t *enp,
594 __in uint32_t partn,
595 __in uint32_t offset,
596 __in_bcount(size) caddr_t data,
597 __in size_t size);
598
599 __checkReturn efx_rc_t
600 efx_mcdi_nvram_update_finish(
601 __in efx_nic_t *enp,
602 __in uint32_t partn,
603 __in boolean_t reboot,
604 __out_opt uint32_t *verify_resultp);
605
606 #if EFSYS_OPT_DIAG
607
608 __checkReturn efx_rc_t
609 efx_mcdi_nvram_test(
610 __in efx_nic_t *enp,
611 __in uint32_t partn);
612
613 #endif /* EFSYS_OPT_DIAG */
614
615 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
616
617 #if EFSYS_OPT_LICENSING
618
619 typedef struct efx_lic_ops_s {
620 efx_rc_t (*elo_update_licenses)(efx_nic_t *);
621 efx_rc_t (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
622 efx_rc_t (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
623 efx_rc_t (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
624 size_t *, uint8_t *);
625 efx_rc_t (*elo_find_start)
626 (efx_nic_t *, caddr_t, size_t, uint32_t *);
627 efx_rc_t (*elo_find_end)(efx_nic_t *, caddr_t, size_t,
628 uint32_t, uint32_t *);
629 boolean_t (*elo_find_key)(efx_nic_t *, caddr_t, size_t,
630 uint32_t, uint32_t *, uint32_t *);
631 boolean_t (*elo_validate_key)(efx_nic_t *,
632 caddr_t, uint32_t);
633 efx_rc_t (*elo_read_key)(efx_nic_t *,
634 caddr_t, size_t, uint32_t, uint32_t,
635 caddr_t, size_t, uint32_t *);
636 efx_rc_t (*elo_write_key)(efx_nic_t *,
637 caddr_t, size_t, uint32_t,
638 caddr_t, uint32_t, uint32_t *);
639 efx_rc_t (*elo_delete_key)(efx_nic_t *,
640 caddr_t, size_t, uint32_t,
641 uint32_t, uint32_t, uint32_t *);
642 efx_rc_t (*elo_create_partition)(efx_nic_t *,
643 caddr_t, size_t);
644 efx_rc_t (*elo_finish_partition)(efx_nic_t *,
645 caddr_t, size_t);
646 } efx_lic_ops_t;
647
648 #endif
649
650 typedef struct efx_drv_cfg_s {
651 uint32_t edc_min_vi_count;
652 uint32_t edc_max_vi_count;
653
654 uint32_t edc_max_piobuf_count;
655 uint32_t edc_pio_alloc_size;
656 } efx_drv_cfg_t;
657
658 struct efx_nic_s {
659 uint32_t en_magic;
660 efx_family_t en_family;
661 uint32_t en_features;
662 efsys_identifier_t *en_esip;
663 efsys_lock_t *en_eslp;
664 efsys_bar_t *en_esbp;
665 unsigned int en_mod_flags;
666 unsigned int en_reset_flags;
667 efx_nic_cfg_t en_nic_cfg;
668 efx_drv_cfg_t en_drv_cfg;
669 efx_port_t en_port;
670 efx_mon_t en_mon;
671 efx_intr_t en_intr;
672 uint32_t en_ev_qcount;
673 uint32_t en_rx_qcount;
674 uint32_t en_tx_qcount;
675 const efx_nic_ops_t *en_enop;
676 const efx_ev_ops_t *en_eevop;
677 const efx_tx_ops_t *en_etxop;
678 const efx_rx_ops_t *en_erxop;
679 efx_fw_variant_t efv;
680 #if EFSYS_OPT_FILTER
681 efx_filter_t en_filter;
682 const efx_filter_ops_t *en_efop;
683 #endif /* EFSYS_OPT_FILTER */
684 #if EFSYS_OPT_TUNNEL
685 efx_tunnel_cfg_t en_tunnel_cfg;
686 const efx_tunnel_ops_t *en_etop;
687 #endif /* EFSYS_OPT_TUNNEL */
688 #if EFSYS_OPT_MCDI
689 efx_mcdi_t en_mcdi;
690 #endif /* EFSYS_OPT_MCDI */
691 #if EFSYS_OPT_NVRAM
692 uint32_t en_nvram_partn_locked;
693 const efx_nvram_ops_t *en_envop;
694 #endif /* EFSYS_OPT_NVRAM */
695 #if EFSYS_OPT_VPD
696 const efx_vpd_ops_t *en_evpdop;
697 #endif /* EFSYS_OPT_VPD */
698 #if EFSYS_OPT_RX_SCALE
699 efx_rx_hash_support_t en_hash_support;
700 efx_rx_scale_context_type_t en_rss_context_type;
701 uint32_t en_rss_context;
702 #endif /* EFSYS_OPT_RX_SCALE */
703 uint32_t en_vport_id;
704 #if EFSYS_OPT_LICENSING
705 const efx_lic_ops_t *en_elop;
706 boolean_t en_licensing_supported;
707 #endif
708 union {
709 #if EFSYS_OPT_SIENA
710 struct {
711 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
712 unsigned int enu_partn_mask;
713 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
714 #if EFSYS_OPT_VPD
715 caddr_t enu_svpd;
716 size_t enu_svpd_length;
717 #endif /* EFSYS_OPT_VPD */
718 int enu_unused;
719 } siena;
720 #endif /* EFSYS_OPT_SIENA */
721 int enu_unused;
722 } en_u;
723 #if EFX_OPTS_EF10()
724 union en_arch {
725 struct {
726 int ena_vi_base;
727 int ena_vi_count;
728 int ena_vi_shift;
729 #if EFSYS_OPT_VPD
730 caddr_t ena_svpd;
731 size_t ena_svpd_length;
732 #endif /* EFSYS_OPT_VPD */
733 efx_piobuf_handle_t ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
734 uint32_t ena_piobuf_count;
735 uint32_t ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
736 uint32_t ena_pio_write_vi_base;
737 /* Memory BAR mapping regions */
738 uint32_t ena_uc_mem_map_offset;
739 size_t ena_uc_mem_map_size;
740 uint32_t ena_wc_mem_map_offset;
741 size_t ena_wc_mem_map_size;
742 } ef10;
743 } en_arch;
744 #endif /* EFX_OPTS_EF10() */
745 };
746
747 #define EFX_FAMILY_IS_EF10(_enp) \
748 ((_enp)->en_family == EFX_FAMILY_MEDFORD2 || \
749 (_enp)->en_family == EFX_FAMILY_MEDFORD || \
750 (_enp)->en_family == EFX_FAMILY_HUNTINGTON)
751
752
753 #define EFX_NIC_MAGIC 0x02121996
754
755 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
756 const efx_ev_callbacks_t *, void *);
757
758 typedef struct efx_evq_rxq_state_s {
759 unsigned int eers_rx_read_ptr;
760 unsigned int eers_rx_mask;
761 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
762 unsigned int eers_rx_stream_npackets;
763 boolean_t eers_rx_packed_stream;
764 #endif
765 #if EFSYS_OPT_RX_PACKED_STREAM
766 unsigned int eers_rx_packed_stream_credits;
767 #endif
768 } efx_evq_rxq_state_t;
769
770 struct efx_evq_s {
771 uint32_t ee_magic;
772 uint32_t ee_flags;
773 efx_nic_t *ee_enp;
774 unsigned int ee_index;
775 unsigned int ee_mask;
776 efsys_mem_t *ee_esmp;
777 #if EFSYS_OPT_QSTATS
778 uint32_t ee_stat[EV_NQSTATS];
779 #endif /* EFSYS_OPT_QSTATS */
780
781 efx_ev_handler_t ee_rx;
782 efx_ev_handler_t ee_tx;
783 efx_ev_handler_t ee_driver;
784 efx_ev_handler_t ee_global;
785 efx_ev_handler_t ee_drv_gen;
786 #if EFSYS_OPT_MCDI
787 efx_ev_handler_t ee_mcdi;
788 #endif /* EFSYS_OPT_MCDI */
789
790 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS];
791 };
792
793 #define EFX_EVQ_MAGIC 0x08081997
794
795 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */
796
797 #if EFSYS_OPT_QSTATS
798 #define EFX_EV_QSTAT_INCR(_eep, _stat) \
799 do { \
800 (_eep)->ee_stat[_stat]++; \
801 _NOTE(CONSTANTCONDITION) \
802 } while (B_FALSE)
803 #else
804 #define EFX_EV_QSTAT_INCR(_eep, _stat)
805 #endif
806
807 struct efx_rxq_s {
808 uint32_t er_magic;
809 efx_nic_t *er_enp;
810 efx_evq_t *er_eep;
811 unsigned int er_index;
812 unsigned int er_label;
813 unsigned int er_mask;
814 size_t er_buf_size;
815 efsys_mem_t *er_esmp;
816 efx_evq_rxq_state_t *er_ev_qstate;
817 };
818
819 #define EFX_RXQ_MAGIC 0x15022005
820
821 struct efx_txq_s {
822 uint32_t et_magic;
823 efx_nic_t *et_enp;
824 unsigned int et_index;
825 unsigned int et_mask;
826 efsys_mem_t *et_esmp;
827 #if EFSYS_OPT_HUNTINGTON
828 uint32_t et_pio_bufnum;
829 uint32_t et_pio_blknum;
830 uint32_t et_pio_write_offset;
831 uint32_t et_pio_offset;
832 size_t et_pio_size;
833 #endif
834 #if EFSYS_OPT_QSTATS
835 uint32_t et_stat[TX_NQSTATS];
836 #endif /* EFSYS_OPT_QSTATS */
837 };
838
839 #define EFX_TXQ_MAGIC 0x05092005
840
841 #define EFX_MAC_ADDR_COPY(_dst, _src) \
842 do { \
843 (_dst)[0] = (_src)[0]; \
844 (_dst)[1] = (_src)[1]; \
845 (_dst)[2] = (_src)[2]; \
846 (_dst)[3] = (_src)[3]; \
847 (_dst)[4] = (_src)[4]; \
848 (_dst)[5] = (_src)[5]; \
849 _NOTE(CONSTANTCONDITION) \
850 } while (B_FALSE)
851
852 #define EFX_MAC_BROADCAST_ADDR_SET(_dst) \
853 do { \
854 uint16_t *_d = (uint16_t *)(_dst); \
855 _d[0] = 0xffff; \
856 _d[1] = 0xffff; \
857 _d[2] = 0xffff; \
858 _NOTE(CONSTANTCONDITION) \
859 } while (B_FALSE)
860
861 #if EFSYS_OPT_CHECK_REG
862 #define EFX_CHECK_REG(_enp, _reg) \
863 do { \
864 const char *name = #_reg; \
865 char min = name[4]; \
866 char max = name[5]; \
867 char rev; \
868 \
869 switch ((_enp)->en_family) { \
870 case EFX_FAMILY_SIENA: \
871 rev = 'C'; \
872 break; \
873 \
874 case EFX_FAMILY_HUNTINGTON: \
875 rev = 'D'; \
876 break; \
877 \
878 case EFX_FAMILY_MEDFORD: \
879 rev = 'E'; \
880 break; \
881 \
882 case EFX_FAMILY_MEDFORD2: \
883 rev = 'F'; \
884 break; \
885 \
886 default: \
887 rev = '?'; \
888 break; \
889 } \
890 \
891 EFSYS_ASSERT3S(rev, >=, min); \
892 EFSYS_ASSERT3S(rev, <=, max); \
893 \
894 _NOTE(CONSTANTCONDITION) \
895 } while (B_FALSE)
896 #else
897 #define EFX_CHECK_REG(_enp, _reg) do { \
898 _NOTE(CONSTANTCONDITION) \
899 } while (B_FALSE)
900 #endif
901
902 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \
903 do { \
904 EFX_CHECK_REG((_enp), (_reg)); \
905 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \
906 (_edp), (_lock)); \
907 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \
908 uint32_t, _reg ## _OFST, \
909 uint32_t, (_edp)->ed_u32[0]); \
910 _NOTE(CONSTANTCONDITION) \
911 } while (B_FALSE)
912
913 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \
914 do { \
915 EFX_CHECK_REG((_enp), (_reg)); \
916 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \
917 uint32_t, _reg ## _OFST, \
918 uint32_t, (_edp)->ed_u32[0]); \
919 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \
920 (_edp), (_lock)); \
921 _NOTE(CONSTANTCONDITION) \
922 } while (B_FALSE)
923
924 #define EFX_BAR_READQ(_enp, _reg, _eqp) \
925 do { \
926 EFX_CHECK_REG((_enp), (_reg)); \
927 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \
928 (_eqp)); \
929 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \
930 uint32_t, _reg ## _OFST, \
931 uint32_t, (_eqp)->eq_u32[1], \
932 uint32_t, (_eqp)->eq_u32[0]); \
933 _NOTE(CONSTANTCONDITION) \
934 } while (B_FALSE)
935
936 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \
937 do { \
938 EFX_CHECK_REG((_enp), (_reg)); \
939 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \
940 uint32_t, _reg ## _OFST, \
941 uint32_t, (_eqp)->eq_u32[1], \
942 uint32_t, (_eqp)->eq_u32[0]); \
943 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \
944 (_eqp)); \
945 _NOTE(CONSTANTCONDITION) \
946 } while (B_FALSE)
947
948 #define EFX_BAR_READO(_enp, _reg, _eop) \
949 do { \
950 EFX_CHECK_REG((_enp), (_reg)); \
951 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \
952 (_eop), B_TRUE); \
953 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \
954 uint32_t, _reg ## _OFST, \
955 uint32_t, (_eop)->eo_u32[3], \
956 uint32_t, (_eop)->eo_u32[2], \
957 uint32_t, (_eop)->eo_u32[1], \
958 uint32_t, (_eop)->eo_u32[0]); \
959 _NOTE(CONSTANTCONDITION) \
960 } while (B_FALSE)
961
962 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \
963 do { \
964 EFX_CHECK_REG((_enp), (_reg)); \
965 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \
966 uint32_t, _reg ## _OFST, \
967 uint32_t, (_eop)->eo_u32[3], \
968 uint32_t, (_eop)->eo_u32[2], \
969 uint32_t, (_eop)->eo_u32[1], \
970 uint32_t, (_eop)->eo_u32[0]); \
971 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \
972 (_eop), B_TRUE); \
973 _NOTE(CONSTANTCONDITION) \
974 } while (B_FALSE)
975
976 /*
977 * Accessors for memory BAR non-VI tables.
978 *
979 * Code used on EF10 *must* use EFX_BAR_VI_*() macros for per-VI registers,
980 * to ensure the correct runtime VI window size is used on Medford2.
981 *
982 * Siena-only code may continue using EFX_BAR_TBL_*() macros for VI registers.
983 */
984
985 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \
986 do { \
987 EFX_CHECK_REG((_enp), (_reg)); \
988 EFSYS_BAR_READD((_enp)->en_esbp, \
989 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
990 (_edp), (_lock)); \
991 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \
992 uint32_t, (_index), \
993 uint32_t, _reg ## _OFST, \
994 uint32_t, (_edp)->ed_u32[0]); \
995 _NOTE(CONSTANTCONDITION) \
996 } while (B_FALSE)
997
998 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \
999 do { \
1000 EFX_CHECK_REG((_enp), (_reg)); \
1001 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
1002 uint32_t, (_index), \
1003 uint32_t, _reg ## _OFST, \
1004 uint32_t, (_edp)->ed_u32[0]); \
1005 EFSYS_BAR_WRITED((_enp)->en_esbp, \
1006 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1007 (_edp), (_lock)); \
1008 _NOTE(CONSTANTCONDITION) \
1009 } while (B_FALSE)
1010
1011 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \
1012 do { \
1013 EFX_CHECK_REG((_enp), (_reg)); \
1014 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
1015 uint32_t, (_index), \
1016 uint32_t, _reg ## _OFST, \
1017 uint32_t, (_edp)->ed_u32[0]); \
1018 EFSYS_BAR_WRITED((_enp)->en_esbp, \
1019 (_reg ## _OFST + \
1020 (3 * sizeof (efx_dword_t)) + \
1021 ((_index) * _reg ## _STEP)), \
1022 (_edp), (_lock)); \
1023 _NOTE(CONSTANTCONDITION) \
1024 } while (B_FALSE)
1025
1026 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \
1027 do { \
1028 EFX_CHECK_REG((_enp), (_reg)); \
1029 EFSYS_BAR_READQ((_enp)->en_esbp, \
1030 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1031 (_eqp)); \
1032 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \
1033 uint32_t, (_index), \
1034 uint32_t, _reg ## _OFST, \
1035 uint32_t, (_eqp)->eq_u32[1], \
1036 uint32_t, (_eqp)->eq_u32[0]); \
1037 _NOTE(CONSTANTCONDITION) \
1038 } while (B_FALSE)
1039
1040 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \
1041 do { \
1042 EFX_CHECK_REG((_enp), (_reg)); \
1043 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \
1044 uint32_t, (_index), \
1045 uint32_t, _reg ## _OFST, \
1046 uint32_t, (_eqp)->eq_u32[1], \
1047 uint32_t, (_eqp)->eq_u32[0]); \
1048 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \
1049 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1050 (_eqp)); \
1051 _NOTE(CONSTANTCONDITION) \
1052 } while (B_FALSE)
1053
1054 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \
1055 do { \
1056 EFX_CHECK_REG((_enp), (_reg)); \
1057 EFSYS_BAR_READO((_enp)->en_esbp, \
1058 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1059 (_eop), (_lock)); \
1060 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \
1061 uint32_t, (_index), \
1062 uint32_t, _reg ## _OFST, \
1063 uint32_t, (_eop)->eo_u32[3], \
1064 uint32_t, (_eop)->eo_u32[2], \
1065 uint32_t, (_eop)->eo_u32[1], \
1066 uint32_t, (_eop)->eo_u32[0]); \
1067 _NOTE(CONSTANTCONDITION) \
1068 } while (B_FALSE)
1069
1070 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \
1071 do { \
1072 EFX_CHECK_REG((_enp), (_reg)); \
1073 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \
1074 uint32_t, (_index), \
1075 uint32_t, _reg ## _OFST, \
1076 uint32_t, (_eop)->eo_u32[3], \
1077 uint32_t, (_eop)->eo_u32[2], \
1078 uint32_t, (_eop)->eo_u32[1], \
1079 uint32_t, (_eop)->eo_u32[0]); \
1080 EFSYS_BAR_WRITEO((_enp)->en_esbp, \
1081 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1082 (_eop), (_lock)); \
1083 _NOTE(CONSTANTCONDITION) \
1084 } while (B_FALSE)
1085
1086 /*
1087 * Accessors for memory BAR per-VI registers.
1088 *
1089 * The VI window size is 8KB for Medford and all earlier controllers.
1090 * For Medford2, the VI window size can be 8KB, 16KB or 64KB.
1091 */
1092
1093 #define EFX_BAR_VI_READD(_enp, _reg, _index, _edp, _lock) \
1094 do { \
1095 EFX_CHECK_REG((_enp), (_reg)); \
1096 EFSYS_BAR_READD((_enp)->en_esbp, \
1097 ((_reg ## _OFST) + \
1098 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1099 (_edp), (_lock)); \
1100 EFSYS_PROBE4(efx_bar_vi_readd, const char *, #_reg, \
1101 uint32_t, (_index), \
1102 uint32_t, _reg ## _OFST, \
1103 uint32_t, (_edp)->ed_u32[0]); \
1104 _NOTE(CONSTANTCONDITION) \
1105 } while (B_FALSE)
1106
1107 #define EFX_BAR_VI_WRITED(_enp, _reg, _index, _edp, _lock) \
1108 do { \
1109 EFX_CHECK_REG((_enp), (_reg)); \
1110 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg, \
1111 uint32_t, (_index), \
1112 uint32_t, _reg ## _OFST, \
1113 uint32_t, (_edp)->ed_u32[0]); \
1114 EFSYS_BAR_WRITED((_enp)->en_esbp, \
1115 ((_reg ## _OFST) + \
1116 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1117 (_edp), (_lock)); \
1118 _NOTE(CONSTANTCONDITION) \
1119 } while (B_FALSE)
1120
1121 #define EFX_BAR_VI_WRITED2(_enp, _reg, _index, _edp, _lock) \
1122 do { \
1123 EFX_CHECK_REG((_enp), (_reg)); \
1124 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg, \
1125 uint32_t, (_index), \
1126 uint32_t, _reg ## _OFST, \
1127 uint32_t, (_edp)->ed_u32[0]); \
1128 EFSYS_BAR_WRITED((_enp)->en_esbp, \
1129 ((_reg ## _OFST) + \
1130 (2 * sizeof (efx_dword_t)) + \
1131 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1132 (_edp), (_lock)); \
1133 _NOTE(CONSTANTCONDITION) \
1134 } while (B_FALSE)
1135
1136 /*
1137 * Allow drivers to perform optimised 128-bit VI doorbell writes.
1138 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1139 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1140 * the need for locking in the host, and are the only ones known to be safe to
1141 * use 128-bites write with.
1142 */
1143 #define EFX_BAR_VI_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \
1144 do { \
1145 EFX_CHECK_REG((_enp), (_reg)); \
1146 EFSYS_PROBE7(efx_bar_vi_doorbell_writeo, \
1147 const char *, #_reg, \
1148 uint32_t, (_index), \
1149 uint32_t, _reg ## _OFST, \
1150 uint32_t, (_eop)->eo_u32[3], \
1151 uint32_t, (_eop)->eo_u32[2], \
1152 uint32_t, (_eop)->eo_u32[1], \
1153 uint32_t, (_eop)->eo_u32[0]); \
1154 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \
1155 (_reg ## _OFST + \
1156 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1157 (_eop)); \
1158 _NOTE(CONSTANTCONDITION) \
1159 } while (B_FALSE)
1160
1161 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \
1162 do { \
1163 unsigned int _new = (_wptr); \
1164 unsigned int _old = (_owptr); \
1165 \
1166 if ((_new) >= (_old)) \
1167 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1168 (_old) * sizeof (efx_desc_t), \
1169 ((_new) - (_old)) * sizeof (efx_desc_t)); \
1170 else \
1171 /* \
1172 * It is cheaper to sync entire map than sync \
1173 * two parts especially when offset/size are \
1174 * ignored and entire map is synced in any case.\
1175 */ \
1176 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1177 0, \
1178 (_entries) * sizeof (efx_desc_t)); \
1179 _NOTE(CONSTANTCONDITION) \
1180 } while (B_FALSE)
1181
1182 extern __checkReturn efx_rc_t
1183 efx_mac_select(
1184 __in efx_nic_t *enp);
1185
1186 extern void
1187 efx_mac_multicast_hash_compute(
1188 __in_ecount(6*count) uint8_t const *addrs,
1189 __in int count,
1190 __out efx_oword_t *hash_low,
1191 __out efx_oword_t *hash_high);
1192
1193 extern __checkReturn efx_rc_t
1194 efx_phy_probe(
1195 __in efx_nic_t *enp);
1196
1197 extern void
1198 efx_phy_unprobe(
1199 __in efx_nic_t *enp);
1200
1201 #if EFSYS_OPT_VPD
1202
1203 /* VPD utility functions */
1204
1205 extern __checkReturn efx_rc_t
1206 efx_vpd_hunk_length(
1207 __in_bcount(size) caddr_t data,
1208 __in size_t size,
1209 __out size_t *lengthp);
1210
1211 extern __checkReturn efx_rc_t
1212 efx_vpd_hunk_verify(
1213 __in_bcount(size) caddr_t data,
1214 __in size_t size,
1215 __out_opt boolean_t *cksummedp);
1216
1217 extern __checkReturn efx_rc_t
1218 efx_vpd_hunk_reinit(
1219 __in_bcount(size) caddr_t data,
1220 __in size_t size,
1221 __in boolean_t wantpid);
1222
1223 extern __checkReturn efx_rc_t
1224 efx_vpd_hunk_get(
1225 __in_bcount(size) caddr_t data,
1226 __in size_t size,
1227 __in efx_vpd_tag_t tag,
1228 __in efx_vpd_keyword_t keyword,
1229 __out unsigned int *payloadp,
1230 __out uint8_t *paylenp);
1231
1232 extern __checkReturn efx_rc_t
1233 efx_vpd_hunk_next(
1234 __in_bcount(size) caddr_t data,
1235 __in size_t size,
1236 __out efx_vpd_tag_t *tagp,
1237 __out efx_vpd_keyword_t *keyword,
1238 __out_opt unsigned int *payloadp,
1239 __out_opt uint8_t *paylenp,
1240 __inout unsigned int *contp);
1241
1242 extern __checkReturn efx_rc_t
1243 efx_vpd_hunk_set(
1244 __in_bcount(size) caddr_t data,
1245 __in size_t size,
1246 __in efx_vpd_value_t *evvp);
1247
1248 #endif /* EFSYS_OPT_VPD */
1249
1250 #if EFSYS_OPT_MCDI
1251
1252 extern __checkReturn efx_rc_t
1253 efx_mcdi_set_workaround(
1254 __in efx_nic_t *enp,
1255 __in uint32_t type,
1256 __in boolean_t enabled,
1257 __out_opt uint32_t *flagsp);
1258
1259 extern __checkReturn efx_rc_t
1260 efx_mcdi_get_workarounds(
1261 __in efx_nic_t *enp,
1262 __out_opt uint32_t *implementedp,
1263 __out_opt uint32_t *enabledp);
1264
1265 #endif /* EFSYS_OPT_MCDI */
1266
1267 #if EFSYS_OPT_MAC_STATS
1268
1269 /*
1270 * Closed range of stats (i.e. the first and the last are included).
1271 * The last must be greater or equal (if the range is one item only) to
1272 * the first.
1273 */
1274 struct efx_mac_stats_range {
1275 efx_mac_stat_t first;
1276 efx_mac_stat_t last;
1277 };
1278
1279 extern efx_rc_t
1280 efx_mac_stats_mask_add_ranges(
1281 __inout_bcount(mask_size) uint32_t *maskp,
1282 __in size_t mask_size,
1283 __in_ecount(rng_count) const struct efx_mac_stats_range *rngp,
1284 __in unsigned int rng_count);
1285
1286 #endif /* EFSYS_OPT_MAC_STATS */
1287
1288 #ifdef __cplusplus
1289 }
1290 #endif
1291
1292 #endif /* _SYS_EFX_IMPL_H */
Ceph