ceph/src/spdk/dpdk/kernel/linux/kni/ethtool/ixgbe/ixgbe_type.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*******************************************************************************
   3
   4   Intel 10 Gigabit PCI Express Linux driver
   5   Copyright(c) 1999 - 2012 Intel Corporation.
   6
   7   Contact Information:
   8   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
   9   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  10
  11 *******************************************************************************/
  12
  13 #ifndef _IXGBE_TYPE_H_
  14 #define _IXGBE_TYPE_H_
  15
  16 #include "ixgbe_osdep.h"
  17
  18
  19 /* Vendor ID */
  20 #define IXGBE_INTEL_VENDOR_ID                   0x8086
  21
  22 /* Device IDs */
  23 #define IXGBE_DEV_ID_82598                      0x10B6
  24 #define IXGBE_DEV_ID_82598_BX                   0x1508
  25 #define IXGBE_DEV_ID_82598AF_DUAL_PORT          0x10C6
  26 #define IXGBE_DEV_ID_82598AF_SINGLE_PORT        0x10C7
  27 #define IXGBE_DEV_ID_82598AT                    0x10C8
  28 #define IXGBE_DEV_ID_82598AT2                   0x150B
  29 #define IXGBE_DEV_ID_82598EB_SFP_LOM            0x10DB
  30 #define IXGBE_DEV_ID_82598EB_CX4                0x10DD
  31 #define IXGBE_DEV_ID_82598_CX4_DUAL_PORT        0x10EC
  32 #define IXGBE_DEV_ID_82598_DA_DUAL_PORT         0x10F1
  33 #define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM      0x10E1
  34 #define IXGBE_DEV_ID_82598EB_XF_LR              0x10F4
  35 #define IXGBE_DEV_ID_82599_KX4                  0x10F7
  36 #define IXGBE_DEV_ID_82599_KX4_MEZZ             0x1514
  37 #define IXGBE_DEV_ID_82599_KR                   0x1517
  38 #define IXGBE_DEV_ID_82599_COMBO_BACKPLANE      0x10F8
  39 #define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ       0x000C
  40 #define IXGBE_DEV_ID_82599_CX4                  0x10F9
  41 #define IXGBE_DEV_ID_82599_SFP                  0x10FB
  42 #define IXGBE_SUBDEV_ID_82599_SFP               0x11A9
  43 #define IXGBE_SUBDEV_ID_82599_560FLR            0x17D0
  44 #define IXGBE_DEV_ID_82599_BACKPLANE_FCOE       0x152A
  45 #define IXGBE_DEV_ID_82599_SFP_FCOE             0x1529
  46 #define IXGBE_DEV_ID_82599_SFP_EM               0x1507
  47 #define IXGBE_DEV_ID_82599_SFP_SF2              0x154D
  48 #define IXGBE_DEV_ID_82599_QSFP_SF_QP           0x1558
  49 #define IXGBE_DEV_ID_82599EN_SFP                0x1557
  50 #define IXGBE_DEV_ID_82599_XAUI_LOM             0x10FC
  51 #define IXGBE_DEV_ID_82599_T3_LOM               0x151C
  52 #define IXGBE_DEV_ID_82599_LS                   0x154F
  53 #define IXGBE_DEV_ID_X540T                      0x1528
  54
  55 /* General Registers */
  56 #define IXGBE_CTRL              0x00000
  57 #define IXGBE_STATUS            0x00008
  58 #define IXGBE_CTRL_EXT          0x00018
  59 #define IXGBE_ESDP              0x00020
  60 #define IXGBE_EODSDP            0x00028
  61 #define IXGBE_I2CCTL            0x00028
  62 #define IXGBE_PHY_GPIO          0x00028
  63 #define IXGBE_MAC_GPIO          0x00030
  64 #define IXGBE_PHYINT_STATUS0    0x00100
  65 #define IXGBE_PHYINT_STATUS1    0x00104
  66 #define IXGBE_PHYINT_STATUS2    0x00108
  67 #define IXGBE_LEDCTL            0x00200
  68 #define IXGBE_FRTIMER           0x00048
  69 #define IXGBE_TCPTIMER          0x0004C
  70 #define IXGBE_CORESPARE         0x00600
  71 #define IXGBE_EXVET             0x05078
  72
  73 /* NVM Registers */
  74 #define IXGBE_EEC       0x10010
  75 #define IXGBE_EERD      0x10014
  76 #define IXGBE_EEWR      0x10018
  77 #define IXGBE_FLA       0x1001C
  78 #define IXGBE_EEMNGCTL  0x10110
  79 #define IXGBE_EEMNGDATA 0x10114
  80 #define IXGBE_FLMNGCTL  0x10118
  81 #define IXGBE_FLMNGDATA 0x1011C
  82 #define IXGBE_FLMNGCNT  0x10120
  83 #define IXGBE_FLOP      0x1013C
  84 #define IXGBE_GRC       0x10200
  85 #define IXGBE_SRAMREL   0x10210
  86 #define IXGBE_PHYDBG    0x10218
  87
  88 /* General Receive Control */
  89 #define IXGBE_GRC_MNG   0x00000001 /* Manageability Enable */
  90 #define IXGBE_GRC_APME  0x00000002 /* APM enabled in EEPROM */
  91
  92 #define IXGBE_VPDDIAG0  0x10204
  93 #define IXGBE_VPDDIAG1  0x10208
  94
  95 /* I2CCTL Bit Masks */
  96 #define IXGBE_I2C_CLK_IN        0x00000001
  97 #define IXGBE_I2C_CLK_OUT       0x00000002
  98 #define IXGBE_I2C_DATA_IN       0x00000004
  99 #define IXGBE_I2C_DATA_OUT      0x00000008
 100 #define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT      500
 101
 102 #define IXGBE_I2C_THERMAL_SENSOR_ADDR   0xF8
 103 #define IXGBE_EMC_INTERNAL_DATA         0x00
 104 #define IXGBE_EMC_INTERNAL_THERM_LIMIT  0x20
 105 #define IXGBE_EMC_DIODE1_DATA           0x01
 106 #define IXGBE_EMC_DIODE1_THERM_LIMIT    0x19
 107 #define IXGBE_EMC_DIODE2_DATA           0x23
 108 #define IXGBE_EMC_DIODE2_THERM_LIMIT    0x1A
 109
 110 #define IXGBE_MAX_SENSORS               3
 111
 112 struct ixgbe_thermal_diode_data {
 113         u8 location;
 114         u8 temp;
 115         u8 caution_thresh;
 116         u8 max_op_thresh;
 117 };
 118
 119 struct ixgbe_thermal_sensor_data {
 120         struct ixgbe_thermal_diode_data sensor[IXGBE_MAX_SENSORS];
 121 };
 122
 123 /* Interrupt Registers */
 124 #define IXGBE_EICR              0x00800
 125 #define IXGBE_EICS              0x00808
 126 #define IXGBE_EIMS              0x00880
 127 #define IXGBE_EIMC              0x00888
 128 #define IXGBE_EIAC              0x00810
 129 #define IXGBE_EIAM              0x00890
 130 #define IXGBE_EICS_EX(_i)       (0x00A90 + (_i) * 4)
 131 #define IXGBE_EIMS_EX(_i)       (0x00AA0 + (_i) * 4)
 132 #define IXGBE_EIMC_EX(_i)       (0x00AB0 + (_i) * 4)
 133 #define IXGBE_EIAM_EX(_i)       (0x00AD0 + (_i) * 4)
 134 /* 82599 EITR is only 12 bits, with the lower 3 always zero */
 135 /*
 136  * 82598 EITR is 16 bits but set the limits based on the max
 137  * supported by all ixgbe hardware
 138  */
 139 #define IXGBE_MAX_INT_RATE      488281
 140 #define IXGBE_MIN_INT_RATE      956
 141 #define IXGBE_MAX_EITR          0x00000FF8
 142 #define IXGBE_MIN_EITR          8
 143 #define IXGBE_EITR(_i)          (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \
 144                                  (0x012300 + (((_i) - 24) * 4)))
 145 #define IXGBE_EITR_ITR_INT_MASK 0x00000FF8
 146 #define IXGBE_EITR_LLI_MOD      0x00008000
 147 #define IXGBE_EITR_CNT_WDIS     0x80000000
 148 #define IXGBE_IVAR(_i)          (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */
 149 #define IXGBE_IVAR_MISC         0x00A00 /* misc MSI-X interrupt causes */
 150 #define IXGBE_EITRSEL           0x00894
 151 #define IXGBE_MSIXT             0x00000 /* MSI-X Table. 0x0000 - 0x01C */
 152 #define IXGBE_MSIXPBA           0x02000 /* MSI-X Pending bit array */
 153 #define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4)))
 154 #define IXGBE_GPIE              0x00898
 155
 156 /* Flow Control Registers */
 157 #define IXGBE_FCADBUL           0x03210
 158 #define IXGBE_FCADBUH           0x03214
 159 #define IXGBE_FCAMACL           0x04328
 160 #define IXGBE_FCAMACH           0x0432C
 161 #define IXGBE_FCRTH_82599(_i)   (0x03260 + ((_i) * 4)) /* 8 of these (0-7) */
 162 #define IXGBE_FCRTL_82599(_i)   (0x03220 + ((_i) * 4)) /* 8 of these (0-7) */
 163 #define IXGBE_PFCTOP            0x03008
 164 #define IXGBE_FCTTV(_i)         (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */
 165 #define IXGBE_FCRTL(_i)         (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */
 166 #define IXGBE_FCRTH(_i)         (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */
 167 #define IXGBE_FCRTV             0x032A0
 168 #define IXGBE_FCCFG             0x03D00
 169 #define IXGBE_TFCS              0x0CE00
 170
 171 /* Receive DMA Registers */
 172 #define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \
 173                          (0x0D000 + (((_i) - 64) * 0x40)))
 174 #define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \
 175                          (0x0D004 + (((_i) - 64) * 0x40)))
 176 #define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \
 177                          (0x0D008 + (((_i) - 64) * 0x40)))
 178 #define IXGBE_RDH(_i)   (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \
 179                          (0x0D010 + (((_i) - 64) * 0x40)))
 180 #define IXGBE_RDT(_i)   (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \
 181                          (0x0D018 + (((_i) - 64) * 0x40)))
 182 #define IXGBE_RXDCTL(_i)        (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \
 183                                  (0x0D028 + (((_i) - 64) * 0x40)))
 184 #define IXGBE_RSCCTL(_i)        (((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \
 185                                  (0x0D02C + (((_i) - 64) * 0x40)))
 186 #define IXGBE_RSCDBU    0x03028
 187 #define IXGBE_RDDCC     0x02F20
 188 #define IXGBE_RXMEMWRAP 0x03190
 189 #define IXGBE_STARCTRL  0x03024
 190 /*
 191  * Split and Replication Receive Control Registers
 192  * 00-15 : 0x02100 + n*4
 193  * 16-64 : 0x01014 + n*0x40
 194  * 64-127: 0x0D014 + (n-64)*0x40
 195  */
 196 #define IXGBE_SRRCTL(_i)        (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \
 197                                  (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \
 198                                  (0x0D014 + (((_i) - 64) * 0x40))))
 199 /*
 200  * Rx DCA Control Register:
 201  * 00-15 : 0x02200 + n*4
 202  * 16-64 : 0x0100C + n*0x40
 203  * 64-127: 0x0D00C + (n-64)*0x40
 204  */
 205 #define IXGBE_DCA_RXCTRL(_i)    (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \
 206                                  (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \
 207                                  (0x0D00C + (((_i) - 64) * 0x40))))
 208 #define IXGBE_RDRXCTL           0x02F00
 209 #define IXGBE_RDRXCTL_RSC_PUSH  0x80
 210 /* 8 of these 0x03C00 - 0x03C1C */
 211 #define IXGBE_RXPBSIZE(_i)      (0x03C00 + ((_i) * 4))
 212 #define IXGBE_RXCTRL            0x03000
 213 #define IXGBE_DROPEN            0x03D04
 214 #define IXGBE_RXPBSIZE_SHIFT    10
 215
 216 /* Receive Registers */
 217 #define IXGBE_RXCSUM            0x05000
 218 #define IXGBE_RFCTL             0x05008
 219 #define IXGBE_DRECCCTL          0x02F08
 220 #define IXGBE_DRECCCTL_DISABLE  0
 221 #define IXGBE_DRECCCTL2         0x02F8C
 222
 223 /* Multicast Table Array - 128 entries */
 224 #define IXGBE_MTA(_i)           (0x05200 + ((_i) * 4))
 225 #define IXGBE_RAL(_i)           (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
 226                                  (0x0A200 + ((_i) * 8)))
 227 #define IXGBE_RAH(_i)           (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
 228                                  (0x0A204 + ((_i) * 8)))
 229 #define IXGBE_MPSAR_LO(_i)      (0x0A600 + ((_i) * 8))
 230 #define IXGBE_MPSAR_HI(_i)      (0x0A604 + ((_i) * 8))
 231 /* Packet split receive type */
 232 #define IXGBE_PSRTYPE(_i)       (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \
 233                                  (0x0EA00 + ((_i) * 4)))
 234 /* array of 4096 1-bit vlan filters */
 235 #define IXGBE_VFTA(_i)          (0x0A000 + ((_i) * 4))
 236 /*array of 4096 4-bit vlan vmdq indices */
 237 #define IXGBE_VFTAVIND(_j, _i)  (0x0A200 + ((_j) * 0x200) + ((_i) * 4))
 238 #define IXGBE_FCTRL             0x05080
 239 #define IXGBE_VLNCTRL           0x05088
 240 #define IXGBE_MCSTCTRL          0x05090
 241 #define IXGBE_MRQC              0x05818
 242 #define IXGBE_SAQF(_i)  (0x0E000 + ((_i) * 4)) /* Source Address Queue Filter */
 243 #define IXGBE_DAQF(_i)  (0x0E200 + ((_i) * 4)) /* Dest. Address Queue Filter */
 244 #define IXGBE_SDPQF(_i) (0x0E400 + ((_i) * 4)) /* Src Dest. Addr Queue Filter */
 245 #define IXGBE_FTQF(_i)  (0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */
 246 #define IXGBE_ETQF(_i)  (0x05128 + ((_i) * 4)) /* EType Queue Filter */
 247 #define IXGBE_ETQS(_i)  (0x0EC00 + ((_i) * 4)) /* EType Queue Select */
 248 #define IXGBE_SYNQF     0x0EC30 /* SYN Packet Queue Filter */
 249 #define IXGBE_RQTC      0x0EC70
 250 #define IXGBE_MTQC      0x08120
 251 #define IXGBE_VLVF(_i)  (0x0F100 + ((_i) * 4))  /* 64 of these (0-63) */
 252 #define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4))  /* 128 of these (0-127) */
 253 #define IXGBE_VMVIR(_i) (0x08000 + ((_i) * 4))  /* 64 of these (0-63) */
 254 #define IXGBE_VT_CTL            0x051B0
 255 #define IXGBE_PFMAILBOX(_i)     (0x04B00 + (4 * (_i))) /* 64 total */
 256 /* 64 Mailboxes, 16 DW each */
 257 #define IXGBE_PFMBMEM(_i)       (0x13000 + (64 * (_i)))
 258 #define IXGBE_PFMBICR(_i)       (0x00710 + (4 * (_i))) /* 4 total */
 259 #define IXGBE_PFMBIMR(_i)       (0x00720 + (4 * (_i))) /* 4 total */
 260 #define IXGBE_VFRE(_i)          (0x051E0 + ((_i) * 4))
 261 #define IXGBE_VFTE(_i)          (0x08110 + ((_i) * 4))
 262 #define IXGBE_VMECM(_i)         (0x08790 + ((_i) * 4))
 263 #define IXGBE_QDE               0x2F04
 264 #define IXGBE_VMTXSW(_i)        (0x05180 + ((_i) * 4)) /* 2 total */
 265 #define IXGBE_VMOLR(_i)         (0x0F000 + ((_i) * 4)) /* 64 total */
 266 #define IXGBE_UTA(_i)           (0x0F400 + ((_i) * 4))
 267 #define IXGBE_MRCTL(_i)         (0x0F600 + ((_i) * 4))
 268 #define IXGBE_VMRVLAN(_i)       (0x0F610 + ((_i) * 4))
 269 #define IXGBE_VMRVM(_i)         (0x0F630 + ((_i) * 4))
 270 #define IXGBE_L34T_IMIR(_i)     (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/
 271 #define IXGBE_RXFECCERR0        0x051B8
 272 #define IXGBE_LLITHRESH         0x0EC90
 273 #define IXGBE_IMIR(_i)          (0x05A80 + ((_i) * 4))  /* 8 of these (0-7) */
 274 #define IXGBE_IMIREXT(_i)       (0x05AA0 + ((_i) * 4))  /* 8 of these (0-7) */
 275 #define IXGBE_IMIRVP            0x05AC0
 276 #define IXGBE_VMD_CTL           0x0581C
 277 #define IXGBE_RETA(_i)          (0x05C00 + ((_i) * 4))  /* 32 of these (0-31) */
 278 #define IXGBE_RSSRK(_i)         (0x05C80 + ((_i) * 4))  /* 10 of these (0-9) */
 279
 280 /* Flow Director registers */
 281 #define IXGBE_FDIRCTRL  0x0EE00
 282 #define IXGBE_FDIRHKEY  0x0EE68
 283 #define IXGBE_FDIRSKEY  0x0EE6C
 284 #define IXGBE_FDIRDIP4M 0x0EE3C
 285 #define IXGBE_FDIRSIP4M 0x0EE40
 286 #define IXGBE_FDIRTCPM  0x0EE44
 287 #define IXGBE_FDIRUDPM  0x0EE48
 288 #define IXGBE_FDIRIP6M  0x0EE74
 289 #define IXGBE_FDIRM     0x0EE70
 290
 291 /* Flow Director Stats registers */
 292 #define IXGBE_FDIRFREE  0x0EE38
 293 #define IXGBE_FDIRLEN   0x0EE4C
 294 #define IXGBE_FDIRUSTAT 0x0EE50
 295 #define IXGBE_FDIRFSTAT 0x0EE54
 296 #define IXGBE_FDIRMATCH 0x0EE58
 297 #define IXGBE_FDIRMISS  0x0EE5C
 298
 299 /* Flow Director Programming registers */
 300 #define IXGBE_FDIRSIPv6(_i) (0x0EE0C + ((_i) * 4)) /* 3 of these (0-2) */
 301 #define IXGBE_FDIRIPSA  0x0EE18
 302 #define IXGBE_FDIRIPDA  0x0EE1C
 303 #define IXGBE_FDIRPORT  0x0EE20
 304 #define IXGBE_FDIRVLAN  0x0EE24
 305 #define IXGBE_FDIRHASH  0x0EE28
 306 #define IXGBE_FDIRCMD   0x0EE2C
 307
 308 /* Transmit DMA registers */
 309 #define IXGBE_TDBAL(_i)         (0x06000 + ((_i) * 0x40)) /* 32 of them (0-31)*/
 310 #define IXGBE_TDBAH(_i)         (0x06004 + ((_i) * 0x40))
 311 #define IXGBE_TDLEN(_i)         (0x06008 + ((_i) * 0x40))
 312 #define IXGBE_TDH(_i)           (0x06010 + ((_i) * 0x40))
 313 #define IXGBE_TDT(_i)           (0x06018 + ((_i) * 0x40))
 314 #define IXGBE_TXDCTL(_i)        (0x06028 + ((_i) * 0x40))
 315 #define IXGBE_TDWBAL(_i)        (0x06038 + ((_i) * 0x40))
 316 #define IXGBE_TDWBAH(_i)        (0x0603C + ((_i) * 0x40))
 317 #define IXGBE_DTXCTL            0x07E00
 318
 319 #define IXGBE_DMATXCTL          0x04A80
 320 #define IXGBE_PFVFSPOOF(_i)     (0x08200 + ((_i) * 4)) /* 8 of these 0 - 7 */
 321 #define IXGBE_PFDTXGSWC         0x08220
 322 #define IXGBE_DTXMXSZRQ         0x08100
 323 #define IXGBE_DTXTCPFLGL        0x04A88
 324 #define IXGBE_DTXTCPFLGH        0x04A8C
 325 #define IXGBE_LBDRPEN           0x0CA00
 326 #define IXGBE_TXPBTHRESH(_i)    (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */
 327
 328 #define IXGBE_DMATXCTL_TE       0x1 /* Transmit Enable */
 329 #define IXGBE_DMATXCTL_NS       0x2 /* No Snoop LSO hdr buffer */
 330 #define IXGBE_DMATXCTL_GDV      0x8 /* Global Double VLAN */
 331 #define IXGBE_DMATXCTL_VT_SHIFT 16  /* VLAN EtherType */
 332
 333 #define IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */
 334
 335 /* Anti-spoofing defines */
 336 #define IXGBE_SPOOF_MACAS_MASK          0xFF
 337 #define IXGBE_SPOOF_VLANAS_MASK         0xFF00
 338 #define IXGBE_SPOOF_VLANAS_SHIFT        8
 339 #define IXGBE_PFVFSPOOF_REG_COUNT       8
 340 /* 16 of these (0-15) */
 341 #define IXGBE_DCA_TXCTRL(_i)            (0x07200 + ((_i) * 4))
 342 /* Tx DCA Control register : 128 of these (0-127) */
 343 #define IXGBE_DCA_TXCTRL_82599(_i)      (0x0600C + ((_i) * 0x40))
 344 #define IXGBE_TIPG                      0x0CB00
 345 #define IXGBE_TXPBSIZE(_i)              (0x0CC00 + ((_i) * 4)) /* 8 of these */
 346 #define IXGBE_MNGTXMAP                  0x0CD10
 347 #define IXGBE_TIPG_FIBER_DEFAULT        3
 348 #define IXGBE_TXPBSIZE_SHIFT            10
 349
 350 /* Wake up registers */
 351 #define IXGBE_WUC       0x05800
 352 #define IXGBE_WUFC      0x05808
 353 #define IXGBE_WUS       0x05810
 354 #define IXGBE_IPAV      0x05838
 355 #define IXGBE_IP4AT     0x05840 /* IPv4 table 0x5840-0x5858 */
 356 #define IXGBE_IP6AT     0x05880 /* IPv6 table 0x5880-0x588F */
 357
 358 #define IXGBE_WUPL      0x05900
 359 #define IXGBE_WUPM      0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */
 360 #define IXGBE_FHFT(_n)  (0x09000 + (_n * 0x100)) /* Flex host filter table */
 361 /* Ext Flexible Host Filter Table */
 362 #define IXGBE_FHFT_EXT(_n)      (0x09800 + (_n * 0x100))
 363
 364 #define IXGBE_FLEXIBLE_FILTER_COUNT_MAX         4
 365 #define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX     2
 366
 367 /* Each Flexible Filter is at most 128 (0x80) bytes in length */
 368 #define IXGBE_FLEXIBLE_FILTER_SIZE_MAX          128
 369 #define IXGBE_FHFT_LENGTH_OFFSET                0xFC  /* Length byte in FHFT */
 370 #define IXGBE_FHFT_LENGTH_MASK                  0x0FF /* Length in lower byte */
 371
 372 /* Definitions for power management and wakeup registers */
 373 /* Wake Up Control */
 374 #define IXGBE_WUC_PME_EN        0x00000002 /* PME Enable */
 375 #define IXGBE_WUC_PME_STATUS    0x00000004 /* PME Status */
 376 #define IXGBE_WUC_WKEN          0x00000010 /* Enable PE_WAKE_N pin assertion  */
 377
 378 /* Wake Up Filter Control */
 379 #define IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
 380 #define IXGBE_WUFC_MAG  0x00000002 /* Magic Packet Wakeup Enable */
 381 #define IXGBE_WUFC_EX   0x00000004 /* Directed Exact Wakeup Enable */
 382 #define IXGBE_WUFC_MC   0x00000008 /* Directed Multicast Wakeup Enable */
 383 #define IXGBE_WUFC_BC   0x00000010 /* Broadcast Wakeup Enable */
 384 #define IXGBE_WUFC_ARP  0x00000020 /* ARP Request Packet Wakeup Enable */
 385 #define IXGBE_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
 386 #define IXGBE_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
 387 #define IXGBE_WUFC_MNG  0x00000100 /* Directed Mgmt Packet Wakeup Enable */
 388
 389 #define IXGBE_WUFC_IGNORE_TCO   0x00008000 /* Ignore WakeOn TCO packets */
 390 #define IXGBE_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
 391 #define IXGBE_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
 392 #define IXGBE_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
 393 #define IXGBE_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
 394 #define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */
 395 #define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */
 396 #define IXGBE_WUFC_FLX_FILTERS  0x000F0000 /* Mask for 4 flex filters */
 397 /* Mask for Ext. flex filters */
 398 #define IXGBE_WUFC_EXT_FLX_FILTERS      0x00300000
 399 #define IXGBE_WUFC_ALL_FILTERS  0x003F00FF /* Mask for all wakeup filters */
 400 #define IXGBE_WUFC_FLX_OFFSET   16 /* Offset to the Flexible Filters bits */
 401
 402 /* Wake Up Status */
 403 #define IXGBE_WUS_LNKC          IXGBE_WUFC_LNKC
 404 #define IXGBE_WUS_MAG           IXGBE_WUFC_MAG
 405 #define IXGBE_WUS_EX            IXGBE_WUFC_EX
 406 #define IXGBE_WUS_MC            IXGBE_WUFC_MC
 407 #define IXGBE_WUS_BC            IXGBE_WUFC_BC
 408 #define IXGBE_WUS_ARP           IXGBE_WUFC_ARP
 409 #define IXGBE_WUS_IPV4          IXGBE_WUFC_IPV4
 410 #define IXGBE_WUS_IPV6          IXGBE_WUFC_IPV6
 411 #define IXGBE_WUS_MNG           IXGBE_WUFC_MNG
 412 #define IXGBE_WUS_FLX0          IXGBE_WUFC_FLX0
 413 #define IXGBE_WUS_FLX1          IXGBE_WUFC_FLX1
 414 #define IXGBE_WUS_FLX2          IXGBE_WUFC_FLX2
 415 #define IXGBE_WUS_FLX3          IXGBE_WUFC_FLX3
 416 #define IXGBE_WUS_FLX4          IXGBE_WUFC_FLX4
 417 #define IXGBE_WUS_FLX5          IXGBE_WUFC_FLX5
 418 #define IXGBE_WUS_FLX_FILTERS   IXGBE_WUFC_FLX_FILTERS
 419
 420 /* Wake Up Packet Length */
 421 #define IXGBE_WUPL_LENGTH_MASK  0xFFFF
 422
 423 /* DCB registers */
 424 #define IXGBE_DCB_MAX_TRAFFIC_CLASS     8
 425 #define IXGBE_RMCS              0x03D00
 426 #define IXGBE_DPMCS             0x07F40
 427 #define IXGBE_PDPMCS            0x0CD00
 428 #define IXGBE_RUPPBMR           0x050A0
 429 #define IXGBE_RT2CR(_i)         (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */
 430 #define IXGBE_RT2SR(_i)         (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */
 431 #define IXGBE_TDTQ2TCCR(_i)     (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */
 432 #define IXGBE_TDTQ2TCSR(_i)     (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */
 433 #define IXGBE_TDPT2TCCR(_i)     (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
 434 #define IXGBE_TDPT2TCSR(_i)     (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
 435
 436
 437 /* Security Control Registers */
 438 #define IXGBE_SECTXCTRL         0x08800
 439 #define IXGBE_SECTXSTAT         0x08804
 440 #define IXGBE_SECTXBUFFAF       0x08808
 441 #define IXGBE_SECTXMINIFG       0x08810
 442 #define IXGBE_SECRXCTRL         0x08D00
 443 #define IXGBE_SECRXSTAT         0x08D04
 444
 445 /* Security Bit Fields and Masks */
 446 #define IXGBE_SECTXCTRL_SECTX_DIS       0x00000001
 447 #define IXGBE_SECTXCTRL_TX_DIS          0x00000002
 448 #define IXGBE_SECTXCTRL_STORE_FORWARD   0x00000004
 449
 450 #define IXGBE_SECTXSTAT_SECTX_RDY       0x00000001
 451 #define IXGBE_SECTXSTAT_ECC_TXERR       0x00000002
 452
 453 #define IXGBE_SECRXCTRL_SECRX_DIS       0x00000001
 454 #define IXGBE_SECRXCTRL_RX_DIS          0x00000002
 455
 456 #define IXGBE_SECRXSTAT_SECRX_RDY       0x00000001
 457 #define IXGBE_SECRXSTAT_ECC_RXERR       0x00000002
 458
 459 /* LinkSec (MacSec) Registers */
 460 #define IXGBE_LSECTXCAP         0x08A00
 461 #define IXGBE_LSECRXCAP         0x08F00
 462 #define IXGBE_LSECTXCTRL        0x08A04
 463 #define IXGBE_LSECTXSCL         0x08A08 /* SCI Low */
 464 #define IXGBE_LSECTXSCH         0x08A0C /* SCI High */
 465 #define IXGBE_LSECTXSA          0x08A10
 466 #define IXGBE_LSECTXPN0         0x08A14
 467 #define IXGBE_LSECTXPN1         0x08A18
 468 #define IXGBE_LSECTXKEY0(_n)    (0x08A1C + (4 * (_n))) /* 4 of these (0-3) */
 469 #define IXGBE_LSECTXKEY1(_n)    (0x08A2C + (4 * (_n))) /* 4 of these (0-3) */
 470 #define IXGBE_LSECRXCTRL        0x08F04
 471 #define IXGBE_LSECRXSCL         0x08F08
 472 #define IXGBE_LSECRXSCH         0x08F0C
 473 #define IXGBE_LSECRXSA(_i)      (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */
 474 #define IXGBE_LSECRXPN(_i)      (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */
 475 #define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m))))
 476 #define IXGBE_LSECTXUT          0x08A3C /* OutPktsUntagged */
 477 #define IXGBE_LSECTXPKTE        0x08A40 /* OutPktsEncrypted */
 478 #define IXGBE_LSECTXPKTP        0x08A44 /* OutPktsProtected */
 479 #define IXGBE_LSECTXOCTE        0x08A48 /* OutOctetsEncrypted */
 480 #define IXGBE_LSECTXOCTP        0x08A4C /* OutOctetsProtected */
 481 #define IXGBE_LSECRXUT          0x08F40 /* InPktsUntagged/InPktsNoTag */
 482 #define IXGBE_LSECRXOCTD        0x08F44 /* InOctetsDecrypted */
 483 #define IXGBE_LSECRXOCTV        0x08F48 /* InOctetsValidated */
 484 #define IXGBE_LSECRXBAD         0x08F4C /* InPktsBadTag */
 485 #define IXGBE_LSECRXNOSCI       0x08F50 /* InPktsNoSci */
 486 #define IXGBE_LSECRXUNSCI       0x08F54 /* InPktsUnknownSci */
 487 #define IXGBE_LSECRXUNCH        0x08F58 /* InPktsUnchecked */
 488 #define IXGBE_LSECRXDELAY       0x08F5C /* InPktsDelayed */
 489 #define IXGBE_LSECRXLATE        0x08F60 /* InPktsLate */
 490 #define IXGBE_LSECRXOK(_n)      (0x08F64 + (0x04 * (_n))) /* InPktsOk */
 491 #define IXGBE_LSECRXINV(_n)     (0x08F6C + (0x04 * (_n))) /* InPktsInvalid */
 492 #define IXGBE_LSECRXNV(_n)      (0x08F74 + (0x04 * (_n))) /* InPktsNotValid */
 493 #define IXGBE_LSECRXUNSA        0x08F7C /* InPktsUnusedSa */
 494 #define IXGBE_LSECRXNUSA        0x08F80 /* InPktsNotUsingSa */
 495
 496 /* LinkSec (MacSec) Bit Fields and Masks */
 497 #define IXGBE_LSECTXCAP_SUM_MASK        0x00FF0000
 498 #define IXGBE_LSECTXCAP_SUM_SHIFT       16
 499 #define IXGBE_LSECRXCAP_SUM_MASK        0x00FF0000
 500 #define IXGBE_LSECRXCAP_SUM_SHIFT       16
 501
 502 #define IXGBE_LSECTXCTRL_EN_MASK        0x00000003
 503 #define IXGBE_LSECTXCTRL_DISABLE        0x0
 504 #define IXGBE_LSECTXCTRL_AUTH           0x1
 505 #define IXGBE_LSECTXCTRL_AUTH_ENCRYPT   0x2
 506 #define IXGBE_LSECTXCTRL_AISCI          0x00000020
 507 #define IXGBE_LSECTXCTRL_PNTHRSH_MASK   0xFFFFFF00
 508 #define IXGBE_LSECTXCTRL_RSV_MASK       0x000000D8
 509
 510 #define IXGBE_LSECRXCTRL_EN_MASK        0x0000000C
 511 #define IXGBE_LSECRXCTRL_EN_SHIFT       2
 512 #define IXGBE_LSECRXCTRL_DISABLE        0x0
 513 #define IXGBE_LSECRXCTRL_CHECK          0x1
 514 #define IXGBE_LSECRXCTRL_STRICT         0x2
 515 #define IXGBE_LSECRXCTRL_DROP           0x3
 516 #define IXGBE_LSECRXCTRL_PLSH           0x00000040
 517 #define IXGBE_LSECRXCTRL_RP             0x00000080
 518 #define IXGBE_LSECRXCTRL_RSV_MASK       0xFFFFFF33
 519
 520 /* IpSec Registers */
 521 #define IXGBE_IPSTXIDX          0x08900
 522 #define IXGBE_IPSTXSALT         0x08904
 523 #define IXGBE_IPSTXKEY(_i)      (0x08908 + (4 * (_i))) /* 4 of these (0-3) */
 524 #define IXGBE_IPSRXIDX          0x08E00
 525 #define IXGBE_IPSRXIPADDR(_i)   (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */
 526 #define IXGBE_IPSRXSPI          0x08E14
 527 #define IXGBE_IPSRXIPIDX        0x08E18
 528 #define IXGBE_IPSRXKEY(_i)      (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */
 529 #define IXGBE_IPSRXSALT         0x08E2C
 530 #define IXGBE_IPSRXMOD          0x08E30
 531
 532 #define IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE    0x4
 533
 534 /* DCB registers */
 535 #define IXGBE_RTRPCS            0x02430
 536 #define IXGBE_RTTDCS            0x04900
 537 #define IXGBE_RTTDCS_ARBDIS     0x00000040 /* DCB arbiter disable */
 538 #define IXGBE_RTTPCS            0x0CD00
 539 #define IXGBE_RTRUP2TC          0x03020
 540 #define IXGBE_RTTUP2TC          0x0C800
 541 #define IXGBE_RTRPT4C(_i)       (0x02140 + ((_i) * 4)) /* 8 of these (0-7) */
 542 #define IXGBE_TXLLQ(_i)         (0x082E0 + ((_i) * 4)) /* 4 of these (0-3) */
 543 #define IXGBE_RTRPT4S(_i)       (0x02160 + ((_i) * 4)) /* 8 of these (0-7) */
 544 #define IXGBE_RTTDT2C(_i)       (0x04910 + ((_i) * 4)) /* 8 of these (0-7) */
 545 #define IXGBE_RTTDT2S(_i)       (0x04930 + ((_i) * 4)) /* 8 of these (0-7) */
 546 #define IXGBE_RTTPT2C(_i)       (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
 547 #define IXGBE_RTTPT2S(_i)       (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
 548 #define IXGBE_RTTDQSEL          0x04904
 549 #define IXGBE_RTTDT1C           0x04908
 550 #define IXGBE_RTTDT1S           0x0490C
 551 #define IXGBE_RTTDTECC          0x04990
 552 #define IXGBE_RTTDTECC_NO_BCN   0x00000100
 553
 554 #define IXGBE_RTTBCNRC                  0x04984
 555 #define IXGBE_RTTBCNRC_RS_ENA           0x80000000
 556 #define IXGBE_RTTBCNRC_RF_DEC_MASK      0x00003FFF
 557 #define IXGBE_RTTBCNRC_RF_INT_SHIFT     14
 558 #define IXGBE_RTTBCNRC_RF_INT_MASK \
 559         (IXGBE_RTTBCNRC_RF_DEC_MASK << IXGBE_RTTBCNRC_RF_INT_SHIFT)
 560 #define IXGBE_RTTBCNRM  0x04980
 561
 562 /* FCoE DMA Context Registers */
 563 #define IXGBE_FCPTRL            0x02410 /* FC User Desc. PTR Low */
 564 #define IXGBE_FCPTRH            0x02414 /* FC USer Desc. PTR High */
 565 #define IXGBE_FCBUFF            0x02418 /* FC Buffer Control */
 566 #define IXGBE_FCDMARW           0x02420 /* FC Receive DMA RW */
 567 #define IXGBE_FCINVST0          0x03FC0 /* FC Invalid DMA Context Status Reg 0*/
 568 #define IXGBE_FCINVST(_i)       (IXGBE_FCINVST0 + ((_i) * 4))
 569 #define IXGBE_FCBUFF_VALID      (1 << 0)   /* DMA Context Valid */
 570 #define IXGBE_FCBUFF_BUFFSIZE   (3 << 3)   /* User Buffer Size */
 571 #define IXGBE_FCBUFF_WRCONTX    (1 << 7)   /* 0: Initiator, 1: Target */
 572 #define IXGBE_FCBUFF_BUFFCNT    0x0000ff00 /* Number of User Buffers */
 573 #define IXGBE_FCBUFF_OFFSET     0xffff0000 /* User Buffer Offset */
 574 #define IXGBE_FCBUFF_BUFFSIZE_SHIFT     3
 575 #define IXGBE_FCBUFF_BUFFCNT_SHIFT      8
 576 #define IXGBE_FCBUFF_OFFSET_SHIFT       16
 577 #define IXGBE_FCDMARW_WE                (1 << 14)   /* Write enable */
 578 #define IXGBE_FCDMARW_RE                (1 << 15)   /* Read enable */
 579 #define IXGBE_FCDMARW_FCOESEL           0x000001ff  /* FC X_ID: 11 bits */
 580 #define IXGBE_FCDMARW_LASTSIZE          0xffff0000  /* Last User Buffer Size */
 581 #define IXGBE_FCDMARW_LASTSIZE_SHIFT    16
 582 /* FCoE SOF/EOF */
 583 #define IXGBE_TEOFF             0x04A94 /* Tx FC EOF */
 584 #define IXGBE_TSOFF             0x04A98 /* Tx FC SOF */
 585 #define IXGBE_REOFF             0x05158 /* Rx FC EOF */
 586 #define IXGBE_RSOFF             0x051F8 /* Rx FC SOF */
 587 /* FCoE Filter Context Registers */
 588 #define IXGBE_FCFLT             0x05108 /* FC FLT Context */
 589 #define IXGBE_FCFLTRW           0x05110 /* FC Filter RW Control */
 590 #define IXGBE_FCPARAM           0x051d8 /* FC Offset Parameter */
 591 #define IXGBE_FCFLT_VALID       (1 << 0)   /* Filter Context Valid */
 592 #define IXGBE_FCFLT_FIRST       (1 << 1)   /* Filter First */
 593 #define IXGBE_FCFLT_SEQID       0x00ff0000 /* Sequence ID */
 594 #define IXGBE_FCFLT_SEQCNT      0xff000000 /* Sequence Count */
 595 #define IXGBE_FCFLTRW_RVALDT    (1 << 13)  /* Fast Re-Validation */
 596 #define IXGBE_FCFLTRW_WE        (1 << 14)  /* Write Enable */
 597 #define IXGBE_FCFLTRW_RE        (1 << 15)  /* Read Enable */
 598 /* FCoE Receive Control */
 599 #define IXGBE_FCRXCTRL          0x05100 /* FC Receive Control */
 600 #define IXGBE_FCRXCTRL_FCOELLI  (1 << 0)   /* Low latency interrupt */
 601 #define IXGBE_FCRXCTRL_SAVBAD   (1 << 1)   /* Save Bad Frames */
 602 #define IXGBE_FCRXCTRL_FRSTRDH  (1 << 2)   /* EN 1st Read Header */
 603 #define IXGBE_FCRXCTRL_LASTSEQH (1 << 3)   /* EN Last Header in Seq */
 604 #define IXGBE_FCRXCTRL_ALLH     (1 << 4)   /* EN All Headers */
 605 #define IXGBE_FCRXCTRL_FRSTSEQH (1 << 5)   /* EN 1st Seq. Header */
 606 #define IXGBE_FCRXCTRL_ICRC     (1 << 6)   /* Ignore Bad FC CRC */
 607 #define IXGBE_FCRXCTRL_FCCRCBO  (1 << 7)   /* FC CRC Byte Ordering */
 608 #define IXGBE_FCRXCTRL_FCOEVER  0x00000f00 /* FCoE Version: 4 bits */
 609 #define IXGBE_FCRXCTRL_FCOEVER_SHIFT    8
 610 /* FCoE Redirection */
 611 #define IXGBE_FCRECTL           0x0ED00 /* FC Redirection Control */
 612 #define IXGBE_FCRETA0           0x0ED10 /* FC Redirection Table 0 */
 613 #define IXGBE_FCRETA(_i)        (IXGBE_FCRETA0 + ((_i) * 4)) /* FCoE Redir */
 614 #define IXGBE_FCRECTL_ENA       0x1 /* FCoE Redir Table Enable */
 615 #define IXGBE_FCRETASEL_ENA     0x2 /* FCoE FCRETASEL bit */
 616 #define IXGBE_FCRETA_SIZE       8 /* Max entries in FCRETA */
 617 #define IXGBE_FCRETA_ENTRY_MASK 0x0000007f /* 7 bits for the queue index */
 618
 619 /* Stats registers */
 620 #define IXGBE_CRCERRS   0x04000
 621 #define IXGBE_ILLERRC   0x04004
 622 #define IXGBE_ERRBC     0x04008
 623 #define IXGBE_MSPDC     0x04010
 624 #define IXGBE_MPC(_i)   (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/
 625 #define IXGBE_MLFC      0x04034
 626 #define IXGBE_MRFC      0x04038
 627 #define IXGBE_RLEC      0x04040
 628 #define IXGBE_LXONTXC   0x03F60
 629 #define IXGBE_LXONRXC   0x0CF60
 630 #define IXGBE_LXOFFTXC  0x03F68
 631 #define IXGBE_LXOFFRXC  0x0CF68
 632 #define IXGBE_LXONRXCNT         0x041A4
 633 #define IXGBE_LXOFFRXCNT        0x041A8
 634 #define IXGBE_PXONRXCNT(_i)     (0x04140 + ((_i) * 4)) /* 8 of these */
 635 #define IXGBE_PXOFFRXCNT(_i)    (0x04160 + ((_i) * 4)) /* 8 of these */
 636 #define IXGBE_PXON2OFFCNT(_i)   (0x03240 + ((_i) * 4)) /* 8 of these */
 637 #define IXGBE_PXONTXC(_i)       (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/
 638 #define IXGBE_PXONRXC(_i)       (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/
 639 #define IXGBE_PXOFFTXC(_i)      (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/
 640 #define IXGBE_PXOFFRXC(_i)      (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/
 641 #define IXGBE_PRC64             0x0405C
 642 #define IXGBE_PRC127            0x04060
 643 #define IXGBE_PRC255            0x04064
 644 #define IXGBE_PRC511            0x04068
 645 #define IXGBE_PRC1023           0x0406C
 646 #define IXGBE_PRC1522           0x04070
 647 #define IXGBE_GPRC              0x04074
 648 #define IXGBE_BPRC              0x04078
 649 #define IXGBE_MPRC              0x0407C
 650 #define IXGBE_GPTC              0x04080
 651 #define IXGBE_GORCL             0x04088
 652 #define IXGBE_GORCH             0x0408C
 653 #define IXGBE_GOTCL             0x04090
 654 #define IXGBE_GOTCH             0x04094
 655 #define IXGBE_RNBC(_i)          (0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/
 656 #define IXGBE_RUC               0x040A4
 657 #define IXGBE_RFC               0x040A8
 658 #define IXGBE_ROC               0x040AC
 659 #define IXGBE_RJC               0x040B0
 660 #define IXGBE_MNGPRC            0x040B4
 661 #define IXGBE_MNGPDC            0x040B8
 662 #define IXGBE_MNGPTC            0x0CF90
 663 #define IXGBE_TORL              0x040C0
 664 #define IXGBE_TORH              0x040C4
 665 #define IXGBE_TPR               0x040D0
 666 #define IXGBE_TPT               0x040D4
 667 #define IXGBE_PTC64             0x040D8
 668 #define IXGBE_PTC127            0x040DC
 669 #define IXGBE_PTC255            0x040E0
 670 #define IXGBE_PTC511            0x040E4
 671 #define IXGBE_PTC1023           0x040E8
 672 #define IXGBE_PTC1522           0x040EC
 673 #define IXGBE_MPTC              0x040F0
 674 #define IXGBE_BPTC              0x040F4
 675 #define IXGBE_XEC               0x04120
 676 #define IXGBE_SSVPC             0x08780
 677
 678 #define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4))
 679 #define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \
 680                          (0x08600 + ((_i) * 4)))
 681 #define IXGBE_TQSM(_i)  (0x08600 + ((_i) * 4))
 682
 683 #define IXGBE_QPRC(_i)  (0x01030 + ((_i) * 0x40)) /* 16 of these */
 684 #define IXGBE_QPTC(_i)  (0x06030 + ((_i) * 0x40)) /* 16 of these */
 685 #define IXGBE_QBRC(_i)  (0x01034 + ((_i) * 0x40)) /* 16 of these */
 686 #define IXGBE_QBTC(_i)  (0x06034 + ((_i) * 0x40)) /* 16 of these */
 687 #define IXGBE_QBRC_L(_i)        (0x01034 + ((_i) * 0x40)) /* 16 of these */
 688 #define IXGBE_QBRC_H(_i)        (0x01038 + ((_i) * 0x40)) /* 16 of these */
 689 #define IXGBE_QPRDC(_i)         (0x01430 + ((_i) * 0x40)) /* 16 of these */
 690 #define IXGBE_QBTC_L(_i)        (0x08700 + ((_i) * 0x8)) /* 16 of these */
 691 #define IXGBE_QBTC_H(_i)        (0x08704 + ((_i) * 0x8)) /* 16 of these */
 692 #define IXGBE_FCCRC             0x05118 /* Num of Good Eth CRC w/ Bad FC CRC */
 693 #define IXGBE_FCOERPDC          0x0241C /* FCoE Rx Packets Dropped Count */
 694 #define IXGBE_FCLAST            0x02424 /* FCoE Last Error Count */
 695 #define IXGBE_FCOEPRC           0x02428 /* Number of FCoE Packets Received */
 696 #define IXGBE_FCOEDWRC          0x0242C /* Number of FCoE DWords Received */
 697 #define IXGBE_FCOEPTC           0x08784 /* Number of FCoE Packets Transmitted */
 698 #define IXGBE_FCOEDWTC          0x08788 /* Number of FCoE DWords Transmitted */
 699 #define IXGBE_FCCRC_CNT_MASK    0x0000FFFF /* CRC_CNT: bit 0 - 15 */
 700 #define IXGBE_FCLAST_CNT_MASK   0x0000FFFF /* Last_CNT: bit 0 - 15 */
 701 #define IXGBE_O2BGPTC           0x041C4
 702 #define IXGBE_O2BSPC            0x087B0
 703 #define IXGBE_B2OSPC            0x041C0
 704 #define IXGBE_B2OGPRC           0x02F90
 705 #define IXGBE_BUPRC             0x04180
 706 #define IXGBE_BMPRC             0x04184
 707 #define IXGBE_BBPRC             0x04188
 708 #define IXGBE_BUPTC             0x0418C
 709 #define IXGBE_BMPTC             0x04190
 710 #define IXGBE_BBPTC             0x04194
 711 #define IXGBE_BCRCERRS          0x04198
 712 #define IXGBE_BXONRXC           0x0419C
 713 #define IXGBE_BXOFFRXC          0x041E0
 714 #define IXGBE_BXONTXC           0x041E4
 715 #define IXGBE_BXOFFTXC          0x041E8
 716 #define IXGBE_PCRC8ECL          0x0E810
 717 #define IXGBE_PCRC8ECH          0x0E811
 718 #define IXGBE_PCRC8ECH_MASK     0x1F
 719 #define IXGBE_LDPCECL           0x0E820
 720 #define IXGBE_LDPCECH           0x0E821
 721
 722 /* Management */
 723 #define IXGBE_MAVTV(_i)         (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */
 724 #define IXGBE_MFUTP(_i)         (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */
 725 #define IXGBE_MANC              0x05820
 726 #define IXGBE_MFVAL             0x05824
 727 #define IXGBE_MANC2H            0x05860
 728 #define IXGBE_MDEF(_i)          (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */
 729 #define IXGBE_MIPAF             0x058B0
 730 #define IXGBE_MMAL(_i)          (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */
 731 #define IXGBE_MMAH(_i)          (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */
 732 #define IXGBE_FTFT              0x09400 /* 0x9400-0x97FC */
 733 #define IXGBE_METF(_i)          (0x05190 + ((_i) * 4)) /* 4 of these (0-3) */
 734 #define IXGBE_MDEF_EXT(_i)      (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */
 735 #define IXGBE_LSWFW             0x15014
 736 #define IXGBE_BMCIP(_i)         (0x05050 + ((_i) * 4)) /* 0x5050-0x505C */
 737 #define IXGBE_BMCIPVAL          0x05060
 738 #define IXGBE_BMCIP_IPADDR_TYPE 0x00000001
 739 #define IXGBE_BMCIP_IPADDR_VALID        0x00000002
 740
 741 /* Management Bit Fields and Masks */
 742 #define IXGBE_MANC_EN_BMC2OS    0x10000000 /* Ena BMC2OS and OS2BMC traffic */
 743 #define IXGBE_MANC_EN_BMC2OS_SHIFT      28
 744
 745 /* Firmware Semaphore Register */
 746 #define IXGBE_FWSM_MODE_MASK    0xE
 747
 748 /* ARC Subsystem registers */
 749 #define IXGBE_HICR              0x15F00
 750 #define IXGBE_FWSTS             0x15F0C
 751 #define IXGBE_HSMC0R            0x15F04
 752 #define IXGBE_HSMC1R            0x15F08
 753 #define IXGBE_SWSR              0x15F10
 754 #define IXGBE_HFDR              0x15FE8
 755 #define IXGBE_FLEX_MNG          0x15800 /* 0x15800 - 0x15EFC */
 756
 757 #define IXGBE_HICR_EN           0x01  /* Enable bit - RO */
 758 /* Driver sets this bit when done to put command in RAM */
 759 #define IXGBE_HICR_C            0x02
 760 #define IXGBE_HICR_SV           0x04  /* Status Validity */
 761 #define IXGBE_HICR_FW_RESET_ENABLE      0x40
 762 #define IXGBE_HICR_FW_RESET     0x80
 763
 764 /* PCI-E registers */
 765 #define IXGBE_GCR               0x11000
 766 #define IXGBE_GTV               0x11004
 767 #define IXGBE_FUNCTAG           0x11008
 768 #define IXGBE_GLT               0x1100C
 769 #define IXGBE_PCIEPIPEADR       0x11004
 770 #define IXGBE_PCIEPIPEDAT       0x11008
 771 #define IXGBE_GSCL_1            0x11010
 772 #define IXGBE_GSCL_2            0x11014
 773 #define IXGBE_GSCL_3            0x11018
 774 #define IXGBE_GSCL_4            0x1101C
 775 #define IXGBE_GSCN_0            0x11020
 776 #define IXGBE_GSCN_1            0x11024
 777 #define IXGBE_GSCN_2            0x11028
 778 #define IXGBE_GSCN_3            0x1102C
 779 #define IXGBE_FACTPS            0x10150
 780 #define IXGBE_PCIEANACTL        0x11040
 781 #define IXGBE_SWSM              0x10140
 782 #define IXGBE_FWSM              0x10148
 783 #define IXGBE_GSSR              0x10160
 784 #define IXGBE_MREVID            0x11064
 785 #define IXGBE_DCA_ID            0x11070
 786 #define IXGBE_DCA_CTRL          0x11074
 787 #define IXGBE_SWFW_SYNC         IXGBE_GSSR
 788
 789 /* PCI-E registers 82599-Specific */
 790 #define IXGBE_GCR_EXT           0x11050
 791 #define IXGBE_GSCL_5_82599      0x11030
 792 #define IXGBE_GSCL_6_82599      0x11034
 793 #define IXGBE_GSCL_7_82599      0x11038
 794 #define IXGBE_GSCL_8_82599      0x1103C
 795 #define IXGBE_PHYADR_82599      0x11040
 796 #define IXGBE_PHYDAT_82599      0x11044
 797 #define IXGBE_PHYCTL_82599      0x11048
 798 #define IXGBE_PBACLR_82599      0x11068
 799 #define IXGBE_CIAA_82599        0x11088
 800 #define IXGBE_CIAD_82599        0x1108C
 801 #define IXGBE_PICAUSE           0x110B0
 802 #define IXGBE_PIENA             0x110B8
 803 #define IXGBE_CDQ_MBR_82599     0x110B4
 804 #define IXGBE_PCIESPARE         0x110BC
 805 #define IXGBE_MISC_REG_82599    0x110F0
 806 #define IXGBE_ECC_CTRL_0_82599  0x11100
 807 #define IXGBE_ECC_CTRL_1_82599  0x11104
 808 #define IXGBE_ECC_STATUS_82599  0x110E0
 809 #define IXGBE_BAR_CTRL_82599    0x110F4
 810
 811 /* PCI Express Control */
 812 #define IXGBE_GCR_CMPL_TMOUT_MASK       0x0000F000
 813 #define IXGBE_GCR_CMPL_TMOUT_10ms       0x00001000
 814 #define IXGBE_GCR_CMPL_TMOUT_RESEND     0x00010000
 815 #define IXGBE_GCR_CAP_VER2              0x00040000
 816
 817 #define IXGBE_GCR_EXT_MSIX_EN           0x80000000
 818 #define IXGBE_GCR_EXT_BUFFERS_CLEAR     0x40000000
 819 #define IXGBE_GCR_EXT_VT_MODE_16        0x00000001
 820 #define IXGBE_GCR_EXT_VT_MODE_32        0x00000002
 821 #define IXGBE_GCR_EXT_VT_MODE_64        0x00000003
 822 #define IXGBE_GCR_EXT_SRIOV             (IXGBE_GCR_EXT_MSIX_EN | \
 823                                          IXGBE_GCR_EXT_VT_MODE_64)
 824 /* Time Sync Registers */
 825 #define IXGBE_TSYNCRXCTL        0x05188 /* Rx Time Sync Control register - RW */
 826 #define IXGBE_TSYNCTXCTL        0x08C00 /* Tx Time Sync Control register - RW */
 827 #define IXGBE_RXSTMPL   0x051E8 /* Rx timestamp Low - RO */
 828 #define IXGBE_RXSTMPH   0x051A4 /* Rx timestamp High - RO */
 829 #define IXGBE_RXSATRL   0x051A0 /* Rx timestamp attribute low - RO */
 830 #define IXGBE_RXSATRH   0x051A8 /* Rx timestamp attribute high - RO */
 831 #define IXGBE_RXMTRL    0x05120 /* RX message type register low - RW */
 832 #define IXGBE_TXSTMPL   0x08C04 /* Tx timestamp value Low - RO */
 833 #define IXGBE_TXSTMPH   0x08C08 /* Tx timestamp value High - RO */
 834 #define IXGBE_SYSTIML   0x08C0C /* System time register Low - RO */
 835 #define IXGBE_SYSTIMH   0x08C10 /* System time register High - RO */
 836 #define IXGBE_TIMINCA   0x08C14 /* Increment attributes register - RW */
 837 #define IXGBE_TIMADJL   0x08C18 /* Time Adjustment Offset register Low - RW */
 838 #define IXGBE_TIMADJH   0x08C1C /* Time Adjustment Offset register High - RW */
 839 #define IXGBE_TSAUXC    0x08C20 /* TimeSync Auxiliary Control register - RW */
 840 #define IXGBE_TRGTTIML0 0x08C24 /* Target Time Register 0 Low - RW */
 841 #define IXGBE_TRGTTIMH0 0x08C28 /* Target Time Register 0 High - RW */
 842 #define IXGBE_TRGTTIML1 0x08C2C /* Target Time Register 1 Low - RW */
 843 #define IXGBE_TRGTTIMH1 0x08C30 /* Target Time Register 1 High - RW */
 844 #define IXGBE_FREQOUT0  0x08C34 /* Frequency Out 0 Control register - RW */
 845 #define IXGBE_FREQOUT1  0x08C38 /* Frequency Out 1 Control register - RW */
 846 #define IXGBE_AUXSTMPL0 0x08C3C /* Auxiliary Time Stamp 0 register Low - RO */
 847 #define IXGBE_AUXSTMPH0 0x08C40 /* Auxiliary Time Stamp 0 register High - RO */
 848 #define IXGBE_AUXSTMPL1 0x08C44 /* Auxiliary Time Stamp 1 register Low - RO */
 849 #define IXGBE_AUXSTMPH1 0x08C48 /* Auxiliary Time Stamp 1 register High - RO */
 850
 851 /* Diagnostic Registers */
 852 #define IXGBE_RDSTATCTL         0x02C20
 853 #define IXGBE_RDSTAT(_i)        (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */
 854 #define IXGBE_RDHMPN            0x02F08
 855 #define IXGBE_RIC_DW(_i)        (0x02F10 + ((_i) * 4))
 856 #define IXGBE_RDPROBE           0x02F20
 857 #define IXGBE_RDMAM             0x02F30
 858 #define IXGBE_RDMAD             0x02F34
 859 #define IXGBE_TDSTATCTL         0x07C20
 860 #define IXGBE_TDSTAT(_i)        (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */
 861 #define IXGBE_TDHMPN            0x07F08
 862 #define IXGBE_TDHMPN2           0x082FC
 863 #define IXGBE_TXDESCIC          0x082CC
 864 #define IXGBE_TIC_DW(_i)        (0x07F10 + ((_i) * 4))
 865 #define IXGBE_TIC_DW2(_i)       (0x082B0 + ((_i) * 4))
 866 #define IXGBE_TDPROBE           0x07F20
 867 #define IXGBE_TXBUFCTRL         0x0C600
 868 #define IXGBE_TXBUFDATA0        0x0C610
 869 #define IXGBE_TXBUFDATA1        0x0C614
 870 #define IXGBE_TXBUFDATA2        0x0C618
 871 #define IXGBE_TXBUFDATA3        0x0C61C
 872 #define IXGBE_RXBUFCTRL         0x03600
 873 #define IXGBE_RXBUFDATA0        0x03610
 874 #define IXGBE_RXBUFDATA1        0x03614
 875 #define IXGBE_RXBUFDATA2        0x03618
 876 #define IXGBE_RXBUFDATA3        0x0361C
 877 #define IXGBE_PCIE_DIAG(_i)     (0x11090 + ((_i) * 4)) /* 8 of these */
 878 #define IXGBE_RFVAL             0x050A4
 879 #define IXGBE_MDFTC1            0x042B8
 880 #define IXGBE_MDFTC2            0x042C0
 881 #define IXGBE_MDFTFIFO1         0x042C4
 882 #define IXGBE_MDFTFIFO2         0x042C8
 883 #define IXGBE_MDFTS             0x042CC
 884 #define IXGBE_RXDATAWRPTR(_i)   (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/
 885 #define IXGBE_RXDESCWRPTR(_i)   (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/
 886 #define IXGBE_RXDATARDPTR(_i)   (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/
 887 #define IXGBE_RXDESCRDPTR(_i)   (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/
 888 #define IXGBE_TXDATAWRPTR(_i)   (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/
 889 #define IXGBE_TXDESCWRPTR(_i)   (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/
 890 #define IXGBE_TXDATARDPTR(_i)   (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/
 891 #define IXGBE_TXDESCRDPTR(_i)   (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/
 892 #define IXGBE_PCIEECCCTL        0x1106C
 893 #define IXGBE_RXWRPTR(_i)       (0x03100 + ((_i) * 4)) /* 8 of these 3100-310C*/
 894 #define IXGBE_RXUSED(_i)        (0x03120 + ((_i) * 4)) /* 8 of these 3120-312C*/
 895 #define IXGBE_RXRDPTR(_i)       (0x03140 + ((_i) * 4)) /* 8 of these 3140-314C*/
 896 #define IXGBE_RXRDWRPTR(_i)     (0x03160 + ((_i) * 4)) /* 8 of these 3160-310C*/
 897 #define IXGBE_TXWRPTR(_i)       (0x0C100 + ((_i) * 4)) /* 8 of these C100-C10C*/
 898 #define IXGBE_TXUSED(_i)        (0x0C120 + ((_i) * 4)) /* 8 of these C120-C12C*/
 899 #define IXGBE_TXRDPTR(_i)       (0x0C140 + ((_i) * 4)) /* 8 of these C140-C14C*/
 900 #define IXGBE_TXRDWRPTR(_i)     (0x0C160 + ((_i) * 4)) /* 8 of these C160-C10C*/
 901 #define IXGBE_PCIEECCCTL0       0x11100
 902 #define IXGBE_PCIEECCCTL1       0x11104
 903 #define IXGBE_RXDBUECC          0x03F70
 904 #define IXGBE_TXDBUECC          0x0CF70
 905 #define IXGBE_RXDBUEST          0x03F74
 906 #define IXGBE_TXDBUEST          0x0CF74
 907 #define IXGBE_PBTXECC           0x0C300
 908 #define IXGBE_PBRXECC           0x03300
 909 #define IXGBE_GHECCR            0x110B0
 910
 911 /* MAC Registers */
 912 #define IXGBE_PCS1GCFIG         0x04200
 913 #define IXGBE_PCS1GLCTL         0x04208
 914 #define IXGBE_PCS1GLSTA         0x0420C
 915 #define IXGBE_PCS1GDBG0         0x04210
 916 #define IXGBE_PCS1GDBG1         0x04214
 917 #define IXGBE_PCS1GANA          0x04218
 918 #define IXGBE_PCS1GANLP         0x0421C
 919 #define IXGBE_PCS1GANNP         0x04220
 920 #define IXGBE_PCS1GANLPNP       0x04224
 921 #define IXGBE_HLREG0            0x04240
 922 #define IXGBE_HLREG1            0x04244
 923 #define IXGBE_PAP               0x04248
 924 #define IXGBE_MACA              0x0424C
 925 #define IXGBE_APAE              0x04250
 926 #define IXGBE_ARD               0x04254
 927 #define IXGBE_AIS               0x04258
 928 #define IXGBE_MSCA              0x0425C
 929 #define IXGBE_MSRWD             0x04260
 930 #define IXGBE_MLADD             0x04264
 931 #define IXGBE_MHADD             0x04268
 932 #define IXGBE_MAXFRS            0x04268
 933 #define IXGBE_TREG              0x0426C
 934 #define IXGBE_PCSS1             0x04288
 935 #define IXGBE_PCSS2             0x0428C
 936 #define IXGBE_XPCSS             0x04290
 937 #define IXGBE_MFLCN             0x04294
 938 #define IXGBE_SERDESC           0x04298
 939 #define IXGBE_MACS              0x0429C
 940 #define IXGBE_AUTOC             0x042A0
 941 #define IXGBE_LINKS             0x042A4
 942 #define IXGBE_LINKS2            0x04324
 943 #define IXGBE_AUTOC2            0x042A8
 944 #define IXGBE_AUTOC3            0x042AC
 945 #define IXGBE_ANLP1             0x042B0
 946 #define IXGBE_ANLP2             0x042B4
 947 #define IXGBE_MACC              0x04330
 948 #define IXGBE_ATLASCTL          0x04800
 949 #define IXGBE_MMNGC             0x042D0
 950 #define IXGBE_ANLPNP1           0x042D4
 951 #define IXGBE_ANLPNP2           0x042D8
 952 #define IXGBE_KRPCSFC           0x042E0
 953 #define IXGBE_KRPCSS            0x042E4
 954 #define IXGBE_FECS1             0x042E8
 955 #define IXGBE_FECS2             0x042EC
 956 #define IXGBE_SMADARCTL         0x14F10
 957 #define IXGBE_MPVC              0x04318
 958 #define IXGBE_SGMIIC            0x04314
 959
 960 /* Statistics Registers */
 961 #define IXGBE_RXNFGPC           0x041B0
 962 #define IXGBE_RXNFGBCL          0x041B4
 963 #define IXGBE_RXNFGBCH          0x041B8
 964 #define IXGBE_RXDGPC            0x02F50
 965 #define IXGBE_RXDGBCL           0x02F54
 966 #define IXGBE_RXDGBCH           0x02F58
 967 #define IXGBE_RXDDGPC           0x02F5C
 968 #define IXGBE_RXDDGBCL          0x02F60
 969 #define IXGBE_RXDDGBCH          0x02F64
 970 #define IXGBE_RXLPBKGPC         0x02F68
 971 #define IXGBE_RXLPBKGBCL        0x02F6C
 972 #define IXGBE_RXLPBKGBCH        0x02F70
 973 #define IXGBE_RXDLPBKGPC        0x02F74
 974 #define IXGBE_RXDLPBKGBCL       0x02F78
 975 #define IXGBE_RXDLPBKGBCH       0x02F7C
 976 #define IXGBE_TXDGPC            0x087A0
 977 #define IXGBE_TXDGBCL           0x087A4
 978 #define IXGBE_TXDGBCH           0x087A8
 979
 980 #define IXGBE_RXDSTATCTRL       0x02F40
 981
 982 /* Copper Pond 2 link timeout */
 983 #define IXGBE_VALIDATE_LINK_READY_TIMEOUT 50
 984
 985 /* Omer CORECTL */
 986 #define IXGBE_CORECTL                   0x014F00
 987 /* BARCTRL */
 988 #define IXGBE_BARCTRL                   0x110F4
 989 #define IXGBE_BARCTRL_FLSIZE            0x0700
 990 #define IXGBE_BARCTRL_FLSIZE_SHIFT      8
 991 #define IXGBE_BARCTRL_CSRSIZE           0x2000
 992
 993 /* RSCCTL Bit Masks */
 994 #define IXGBE_RSCCTL_RSCEN      0x01
 995 #define IXGBE_RSCCTL_MAXDESC_1  0x00
 996 #define IXGBE_RSCCTL_MAXDESC_4  0x04
 997 #define IXGBE_RSCCTL_MAXDESC_8  0x08
 998 #define IXGBE_RSCCTL_MAXDESC_16 0x0C
 999
1000 /* RSCDBU Bit Masks */
1001 #define IXGBE_RSCDBU_RSCSMALDIS_MASK    0x0000007F
1002 #define IXGBE_RSCDBU_RSCACKDIS          0x00000080
1003
1004 /* RDRXCTL Bit Masks */
1005 #define IXGBE_RDRXCTL_RDMTS_1_2         0x00000000 /* Rx Desc Min THLD Size */
1006 #define IXGBE_RDRXCTL_CRCSTRIP          0x00000002 /* CRC Strip */
1007 #define IXGBE_RDRXCTL_MVMEN             0x00000020
1008 #define IXGBE_RDRXCTL_DMAIDONE          0x00000008 /* DMA init cycle done */
1009 #define IXGBE_RDRXCTL_AGGDIS            0x00010000 /* Aggregation disable */
1010 #define IXGBE_RDRXCTL_RSCFRSTSIZE       0x003E0000 /* RSC First packet size */
1011 #define IXGBE_RDRXCTL_RSCLLIDIS         0x00800000 /* Disabl RSC compl on LLI */
1012 #define IXGBE_RDRXCTL_RSCACKC           0x02000000 /* must set 1 when RSC ena */
1013 #define IXGBE_RDRXCTL_FCOE_WRFIX        0x04000000 /* must set 1 when RSC ena */
1014
1015 /* RQTC Bit Masks and Shifts */
1016 #define IXGBE_RQTC_SHIFT_TC(_i) ((_i) * 4)
1017 #define IXGBE_RQTC_TC0_MASK     (0x7 << 0)
1018 #define IXGBE_RQTC_TC1_MASK     (0x7 << 4)
1019 #define IXGBE_RQTC_TC2_MASK     (0x7 << 8)
1020 #define IXGBE_RQTC_TC3_MASK     (0x7 << 12)
1021 #define IXGBE_RQTC_TC4_MASK     (0x7 << 16)
1022 #define IXGBE_RQTC_TC5_MASK     (0x7 << 20)
1023 #define IXGBE_RQTC_TC6_MASK     (0x7 << 24)
1024 #define IXGBE_RQTC_TC7_MASK     (0x7 << 28)
1025
1026 /* PSRTYPE.RQPL Bit masks and shift */
1027 #define IXGBE_PSRTYPE_RQPL_MASK         0x7
1028 #define IXGBE_PSRTYPE_RQPL_SHIFT        29
1029
1030 /* CTRL Bit Masks */
1031 #define IXGBE_CTRL_GIO_DIS      0x00000004 /* Global IO Master Disable bit */
1032 #define IXGBE_CTRL_LNK_RST      0x00000008 /* Link Reset. Resets everything. */
1033 #define IXGBE_CTRL_RST          0x04000000 /* Reset (SW) */
1034 #define IXGBE_CTRL_RST_MASK     (IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST)
1035
1036 /* FACTPS */
1037 #define IXGBE_FACTPS_LFS        0x40000000 /* LAN Function Select */
1038
1039 /* MHADD Bit Masks */
1040 #define IXGBE_MHADD_MFS_MASK    0xFFFF0000
1041 #define IXGBE_MHADD_MFS_SHIFT   16
1042
1043 /* Extended Device Control */
1044 #define IXGBE_CTRL_EXT_PFRSTD   0x00004000 /* Physical Function Reset Done */
1045 #define IXGBE_CTRL_EXT_NS_DIS   0x00010000 /* No Snoop disable */
1046 #define IXGBE_CTRL_EXT_RO_DIS   0x00020000 /* Relaxed Ordering disable */
1047 #define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
1048
1049 /* Direct Cache Access (DCA) definitions */
1050 #define IXGBE_DCA_CTRL_DCA_ENABLE       0x00000000 /* DCA Enable */
1051 #define IXGBE_DCA_CTRL_DCA_DISABLE      0x00000001 /* DCA Disable */
1052
1053 #define IXGBE_DCA_CTRL_DCA_MODE_CB1     0x00 /* DCA Mode CB1 */
1054 #define IXGBE_DCA_CTRL_DCA_MODE_CB2     0x02 /* DCA Mode CB2 */
1055
1056 #define IXGBE_DCA_RXCTRL_CPUID_MASK     0x0000001F /* Rx CPUID Mask */
1057 #define IXGBE_DCA_RXCTRL_CPUID_MASK_82599       0xFF000000 /* Rx CPUID Mask */
1058 #define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599      24 /* Rx CPUID Shift */
1059 #define IXGBE_DCA_RXCTRL_DESC_DCA_EN    (1 << 5) /* Rx Desc enable */
1060 #define IXGBE_DCA_RXCTRL_HEAD_DCA_EN    (1 << 6) /* Rx Desc header ena */
1061 #define IXGBE_DCA_RXCTRL_DATA_DCA_EN    (1 << 7) /* Rx Desc payload ena */
1062 #define IXGBE_DCA_RXCTRL_DESC_RRO_EN    (1 << 9) /* Rx rd Desc Relax Order */
1063 #define IXGBE_DCA_RXCTRL_DATA_WRO_EN    (1 << 13) /* Rx wr data Relax Order */
1064 #define IXGBE_DCA_RXCTRL_HEAD_WRO_EN    (1 << 15) /* Rx wr header RO */
1065
1066 #define IXGBE_DCA_TXCTRL_CPUID_MASK     0x0000001F /* Tx CPUID Mask */
1067 #define IXGBE_DCA_TXCTRL_CPUID_MASK_82599       0xFF000000 /* Tx CPUID Mask */
1068 #define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599      24 /* Tx CPUID Shift */
1069 #define IXGBE_DCA_TXCTRL_DESC_DCA_EN    (1 << 5) /* DCA Tx Desc enable */
1070 #define IXGBE_DCA_TXCTRL_DESC_RRO_EN    (1 << 9) /* Tx rd Desc Relax Order */
1071 #define IXGBE_DCA_TXCTRL_DESC_WRO_EN    (1 << 11) /* Tx Desc writeback RO bit */
1072 #define IXGBE_DCA_TXCTRL_DATA_RRO_EN    (1 << 13) /* Tx rd data Relax Order */
1073 #define IXGBE_DCA_MAX_QUEUES_82598      16 /* DCA regs only on 16 queues */
1074
1075 /* MSCA Bit Masks */
1076 #define IXGBE_MSCA_NP_ADDR_MASK         0x0000FFFF /* MDI Addr (new prot) */
1077 #define IXGBE_MSCA_NP_ADDR_SHIFT        0
1078 #define IXGBE_MSCA_DEV_TYPE_MASK        0x001F0000 /* Dev Type (new prot) */
1079 #define IXGBE_MSCA_DEV_TYPE_SHIFT       16 /* Register Address (old prot */
1080 #define IXGBE_MSCA_PHY_ADDR_MASK        0x03E00000 /* PHY Address mask */
1081 #define IXGBE_MSCA_PHY_ADDR_SHIFT       21 /* PHY Address shift*/
1082 #define IXGBE_MSCA_OP_CODE_MASK         0x0C000000 /* OP CODE mask */
1083 #define IXGBE_MSCA_OP_CODE_SHIFT        26 /* OP CODE shift */
1084 #define IXGBE_MSCA_ADDR_CYCLE           0x00000000 /* OP CODE 00 (addr cycle) */
1085 #define IXGBE_MSCA_WRITE                0x04000000 /* OP CODE 01 (wr) */
1086 #define IXGBE_MSCA_READ                 0x0C000000 /* OP CODE 11 (rd) */
1087 #define IXGBE_MSCA_READ_AUTOINC         0x08000000 /* OP CODE 10 (rd auto inc)*/
1088 #define IXGBE_MSCA_ST_CODE_MASK         0x30000000 /* ST Code mask */
1089 #define IXGBE_MSCA_ST_CODE_SHIFT        28 /* ST Code shift */
1090 #define IXGBE_MSCA_NEW_PROTOCOL         0x00000000 /* ST CODE 00 (new prot) */
1091 #define IXGBE_MSCA_OLD_PROTOCOL         0x10000000 /* ST CODE 01 (old prot) */
1092 #define IXGBE_MSCA_MDI_COMMAND          0x40000000 /* Initiate MDI command */
1093 #define IXGBE_MSCA_MDI_IN_PROG_EN       0x80000000 /* MDI in progress ena */
1094
1095 /* MSRWD bit masks */
1096 #define IXGBE_MSRWD_WRITE_DATA_MASK     0x0000FFFF
1097 #define IXGBE_MSRWD_WRITE_DATA_SHIFT    0
1098 #define IXGBE_MSRWD_READ_DATA_MASK      0xFFFF0000
1099 #define IXGBE_MSRWD_READ_DATA_SHIFT     16
1100
1101 /* Atlas registers */
1102 #define IXGBE_ATLAS_PDN_LPBK            0x24
1103 #define IXGBE_ATLAS_PDN_10G             0xB
1104 #define IXGBE_ATLAS_PDN_1G              0xC
1105 #define IXGBE_ATLAS_PDN_AN              0xD
1106
1107 /* Atlas bit masks */
1108 #define IXGBE_ATLASCTL_WRITE_CMD        0x00010000
1109 #define IXGBE_ATLAS_PDN_TX_REG_EN       0x10
1110 #define IXGBE_ATLAS_PDN_TX_10G_QL_ALL   0xF0
1111 #define IXGBE_ATLAS_PDN_TX_1G_QL_ALL    0xF0
1112 #define IXGBE_ATLAS_PDN_TX_AN_QL_ALL    0xF0
1113
1114 /* Omer bit masks */
1115 #define IXGBE_CORECTL_WRITE_CMD         0x00010000
1116
1117 /* Device Type definitions for new protocol MDIO commands */
1118 #define IXGBE_MDIO_PMA_PMD_DEV_TYPE             0x1
1119 #define IXGBE_MDIO_PCS_DEV_TYPE                 0x3
1120 #define IXGBE_MDIO_PHY_XS_DEV_TYPE              0x4
1121 #define IXGBE_MDIO_AUTO_NEG_DEV_TYPE            0x7
1122 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE   0x1E   /* Device 30 */
1123 #define IXGBE_TWINAX_DEV                        1
1124
1125 #define IXGBE_MDIO_COMMAND_TIMEOUT      100 /* PHY Timeout for 1 GB mode */
1126
1127 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL            0x0 /* VS1 Ctrl Reg */
1128 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS             0x1 /* VS1 Status Reg */
1129 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS        0x0008 /* 1 = Link Up */
1130 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS       0x0010 /* 0-10G, 1-1G */
1131 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED          0x0018
1132 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED           0x0010
1133
1134 #define IXGBE_MDIO_AUTO_NEG_CONTROL     0x0 /* AUTO_NEG Control Reg */
1135 #define IXGBE_MDIO_AUTO_NEG_STATUS      0x1 /* AUTO_NEG Status Reg */
1136 #define IXGBE_MDIO_AUTO_NEG_ADVT        0x10 /* AUTO_NEG Advt Reg */
1137 #define IXGBE_MDIO_AUTO_NEG_LP          0x13 /* AUTO_NEG LP Status Reg */
1138 #define IXGBE_MDIO_PHY_XS_CONTROL       0x0 /* PHY_XS Control Reg */
1139 #define IXGBE_MDIO_PHY_XS_RESET         0x8000 /* PHY_XS Reset */
1140 #define IXGBE_MDIO_PHY_ID_HIGH          0x2 /* PHY ID High Reg*/
1141 #define IXGBE_MDIO_PHY_ID_LOW           0x3 /* PHY ID Low Reg*/
1142 #define IXGBE_MDIO_PHY_SPEED_ABILITY    0x4 /* Speed Ability Reg */
1143 #define IXGBE_MDIO_PHY_SPEED_10G        0x0001 /* 10G capable */
1144 #define IXGBE_MDIO_PHY_SPEED_1G         0x0010 /* 1G capable */
1145 #define IXGBE_MDIO_PHY_SPEED_100M       0x0020 /* 100M capable */
1146 #define IXGBE_MDIO_PHY_EXT_ABILITY      0xB /* Ext Ability Reg */
1147 #define IXGBE_MDIO_PHY_10GBASET_ABILITY         0x0004 /* 10GBaseT capable */
1148 #define IXGBE_MDIO_PHY_1000BASET_ABILITY        0x0020 /* 1000BaseT capable */
1149 #define IXGBE_MDIO_PHY_100BASETX_ABILITY        0x0080 /* 100BaseTX capable */
1150 #define IXGBE_MDIO_PHY_SET_LOW_POWER_MODE       0x0800 /* Set low power mode */
1151
1152 #define IXGBE_MDIO_PMA_PMD_CONTROL_ADDR 0x0000 /* PMA/PMD Control Reg */
1153 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */
1154 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */
1155 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */
1156
1157 /* MII clause 22/28 definitions */
1158 #define IXGBE_MDIO_PHY_LOW_POWER_MODE   0x0800
1159
1160 #define IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG    0x20   /* 10G Control Reg */
1161 #define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */
1162 #define IXGBE_MII_AUTONEG_XNP_TX_REG            0x17   /* 1G XNP Transmit */
1163 #define IXGBE_MII_AUTONEG_ADVERTISE_REG         0x10   /* 100M Advertisement */
1164 #define IXGBE_MII_10GBASE_T_ADVERTISE           0x1000 /* full duplex, bit:12*/
1165 #define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX     0x4000 /* full duplex, bit:14*/
1166 #define IXGBE_MII_1GBASE_T_ADVERTISE            0x8000 /* full duplex, bit:15*/
1167 #define IXGBE_MII_100BASE_T_ADVERTISE           0x0100 /* full duplex, bit:8 */
1168 #define IXGBE_MII_100BASE_T_ADVERTISE_HALF      0x0080 /* half duplex, bit:7 */
1169 #define IXGBE_MII_RESTART                       0x200
1170 #define IXGBE_MII_AUTONEG_COMPLETE              0x20
1171 #define IXGBE_MII_AUTONEG_LINK_UP               0x04
1172 #define IXGBE_MII_AUTONEG_REG                   0x0
1173
1174 #define IXGBE_PHY_REVISION_MASK         0xFFFFFFF0
1175 #define IXGBE_MAX_PHY_ADDR              32
1176
1177 /* PHY IDs*/
1178 #define TN1010_PHY_ID   0x00A19410
1179 #define TNX_FW_REV      0xB
1180 #define X540_PHY_ID     0x01540200
1181 #define AQ_FW_REV       0x20
1182 #define QT2022_PHY_ID   0x0043A400
1183 #define ATH_PHY_ID      0x03429050
1184
1185 /* PHY Types */
1186 #define IXGBE_M88E1145_E_PHY_ID 0x01410CD0
1187
1188 /* Special PHY Init Routine */
1189 #define IXGBE_PHY_INIT_OFFSET_NL        0x002B
1190 #define IXGBE_PHY_INIT_END_NL           0xFFFF
1191 #define IXGBE_CONTROL_MASK_NL           0xF000
1192 #define IXGBE_DATA_MASK_NL              0x0FFF
1193 #define IXGBE_CONTROL_SHIFT_NL          12
1194 #define IXGBE_DELAY_NL                  0
1195 #define IXGBE_DATA_NL                   1
1196 #define IXGBE_CONTROL_NL                0x000F
1197 #define IXGBE_CONTROL_EOL_NL            0x0FFF
1198 #define IXGBE_CONTROL_SOL_NL            0x0000
1199
1200 /* General purpose Interrupt Enable */
1201 #define IXGBE_SDP0_GPIEN        0x00000001 /* SDP0 */
1202 #define IXGBE_SDP1_GPIEN        0x00000002 /* SDP1 */
1203 #define IXGBE_SDP2_GPIEN        0x00000004 /* SDP2 */
1204 #define IXGBE_GPIE_MSIX_MODE    0x00000010 /* MSI-X mode */
1205 #define IXGBE_GPIE_OCD          0x00000020 /* Other Clear Disable */
1206 #define IXGBE_GPIE_EIMEN        0x00000040 /* Immediate Interrupt Enable */
1207 #define IXGBE_GPIE_EIAME        0x40000000
1208 #define IXGBE_GPIE_PBA_SUPPORT  0x80000000
1209 #define IXGBE_GPIE_RSC_DELAY_SHIFT      11
1210 #define IXGBE_GPIE_VTMODE_MASK  0x0000C000 /* VT Mode Mask */
1211 #define IXGBE_GPIE_VTMODE_16    0x00004000 /* 16 VFs 8 queues per VF */
1212 #define IXGBE_GPIE_VTMODE_32    0x00008000 /* 32 VFs 4 queues per VF */
1213 #define IXGBE_GPIE_VTMODE_64    0x0000C000 /* 64 VFs 2 queues per VF */
1214
1215 /* Packet Buffer Initialization */
1216 #define IXGBE_MAX_PACKET_BUFFERS        8
1217
1218 #define IXGBE_TXPBSIZE_20KB     0x00005000 /* 20KB Packet Buffer */
1219 #define IXGBE_TXPBSIZE_40KB     0x0000A000 /* 40KB Packet Buffer */
1220 #define IXGBE_RXPBSIZE_48KB     0x0000C000 /* 48KB Packet Buffer */
1221 #define IXGBE_RXPBSIZE_64KB     0x00010000 /* 64KB Packet Buffer */
1222 #define IXGBE_RXPBSIZE_80KB     0x00014000 /* 80KB Packet Buffer */
1223 #define IXGBE_RXPBSIZE_128KB    0x00020000 /* 128KB Packet Buffer */
1224 #define IXGBE_RXPBSIZE_MAX      0x00080000 /* 512KB Packet Buffer */
1225 #define IXGBE_TXPBSIZE_MAX      0x00028000 /* 160KB Packet Buffer */
1226
1227 #define IXGBE_TXPKT_SIZE_MAX    0xA /* Max Tx Packet size */
1228 #define IXGBE_MAX_PB            8
1229
1230 /* Packet buffer allocation strategies */
1231 enum {
1232         PBA_STRATEGY_EQUAL      = 0, /* Distribute PB space equally */
1233 #define PBA_STRATEGY_EQUAL      PBA_STRATEGY_EQUAL
1234         PBA_STRATEGY_WEIGHTED   = 1, /* Weight front half of TCs */
1235 #define PBA_STRATEGY_WEIGHTED   PBA_STRATEGY_WEIGHTED
1236 };
1237
1238 /* Transmit Flow Control status */
1239 #define IXGBE_TFCS_TXOFF        0x00000001
1240 #define IXGBE_TFCS_TXOFF0       0x00000100
1241 #define IXGBE_TFCS_TXOFF1       0x00000200
1242 #define IXGBE_TFCS_TXOFF2       0x00000400
1243 #define IXGBE_TFCS_TXOFF3       0x00000800
1244 #define IXGBE_TFCS_TXOFF4       0x00001000
1245 #define IXGBE_TFCS_TXOFF5       0x00002000
1246 #define IXGBE_TFCS_TXOFF6       0x00004000
1247 #define IXGBE_TFCS_TXOFF7       0x00008000
1248
1249 /* TCP Timer */
1250 #define IXGBE_TCPTIMER_KS               0x00000100
1251 #define IXGBE_TCPTIMER_COUNT_ENABLE     0x00000200
1252 #define IXGBE_TCPTIMER_COUNT_FINISH     0x00000400
1253 #define IXGBE_TCPTIMER_LOOP             0x00000800
1254 #define IXGBE_TCPTIMER_DURATION_MASK    0x000000FF
1255
1256 /* HLREG0 Bit Masks */
1257 #define IXGBE_HLREG0_TXCRCEN            0x00000001 /* bit  0 */
1258 #define IXGBE_HLREG0_RXCRCSTRP          0x00000002 /* bit  1 */
1259 #define IXGBE_HLREG0_JUMBOEN            0x00000004 /* bit  2 */
1260 #define IXGBE_HLREG0_TXPADEN            0x00000400 /* bit 10 */
1261 #define IXGBE_HLREG0_TXPAUSEEN          0x00001000 /* bit 12 */
1262 #define IXGBE_HLREG0_RXPAUSEEN          0x00004000 /* bit 14 */
1263 #define IXGBE_HLREG0_LPBK               0x00008000 /* bit 15 */
1264 #define IXGBE_HLREG0_MDCSPD             0x00010000 /* bit 16 */
1265 #define IXGBE_HLREG0_CONTMDC            0x00020000 /* bit 17 */
1266 #define IXGBE_HLREG0_CTRLFLTR           0x00040000 /* bit 18 */
1267 #define IXGBE_HLREG0_PREPEND            0x00F00000 /* bits 20-23 */
1268 #define IXGBE_HLREG0_PRIPAUSEEN         0x01000000 /* bit 24 */
1269 #define IXGBE_HLREG0_RXPAUSERECDA       0x06000000 /* bits 25-26 */
1270 #define IXGBE_HLREG0_RXLNGTHERREN       0x08000000 /* bit 27 */
1271 #define IXGBE_HLREG0_RXPADSTRIPEN       0x10000000 /* bit 28 */
1272
1273 /* VMD_CTL bitmasks */
1274 #define IXGBE_VMD_CTL_VMDQ_EN           0x00000001
1275 #define IXGBE_VMD_CTL_VMDQ_FILTER       0x00000002
1276
1277 /* VT_CTL bitmasks */
1278 #define IXGBE_VT_CTL_DIS_DEFPL          0x20000000 /* disable default pool */
1279 #define IXGBE_VT_CTL_REPLEN             0x40000000 /* replication enabled */
1280 #define IXGBE_VT_CTL_VT_ENABLE          0x00000001  /* Enable VT Mode */
1281 #define IXGBE_VT_CTL_POOL_SHIFT         7
1282 #define IXGBE_VT_CTL_POOL_MASK          (0x3F << IXGBE_VT_CTL_POOL_SHIFT)
1283
1284 /* VMOLR bitmasks */
1285 #define IXGBE_VMOLR_AUPE        0x01000000 /* accept untagged packets */
1286 #define IXGBE_VMOLR_ROMPE       0x02000000 /* accept packets in MTA tbl */
1287 #define IXGBE_VMOLR_ROPE        0x04000000 /* accept packets in UC tbl */
1288 #define IXGBE_VMOLR_BAM         0x08000000 /* accept broadcast packets */
1289 #define IXGBE_VMOLR_MPE         0x10000000 /* multicast promiscuous */
1290
1291 /* VFRE bitmask */
1292 #define IXGBE_VFRE_ENABLE_ALL   0xFFFFFFFF
1293
1294 #define IXGBE_VF_INIT_TIMEOUT   200 /* Number of retries to clear RSTI */
1295
1296 /* RDHMPN and TDHMPN bitmasks */
1297 #define IXGBE_RDHMPN_RDICADDR           0x007FF800
1298 #define IXGBE_RDHMPN_RDICRDREQ          0x00800000
1299 #define IXGBE_RDHMPN_RDICADDR_SHIFT     11
1300 #define IXGBE_TDHMPN_TDICADDR           0x003FF800
1301 #define IXGBE_TDHMPN_TDICRDREQ          0x00800000
1302 #define IXGBE_TDHMPN_TDICADDR_SHIFT     11
1303
1304 #define IXGBE_RDMAM_MEM_SEL_SHIFT               13
1305 #define IXGBE_RDMAM_DWORD_SHIFT                 9
1306 #define IXGBE_RDMAM_DESC_COMP_FIFO              1
1307 #define IXGBE_RDMAM_DFC_CMD_FIFO                2
1308 #define IXGBE_RDMAM_RSC_HEADER_ADDR             3
1309 #define IXGBE_RDMAM_TCN_STATUS_RAM              4
1310 #define IXGBE_RDMAM_WB_COLL_FIFO                5
1311 #define IXGBE_RDMAM_QSC_CNT_RAM                 6
1312 #define IXGBE_RDMAM_QSC_FCOE_RAM                7
1313 #define IXGBE_RDMAM_QSC_QUEUE_CNT               8
1314 #define IXGBE_RDMAM_QSC_QUEUE_RAM               0xA
1315 #define IXGBE_RDMAM_QSC_RSC_RAM                 0xB
1316 #define IXGBE_RDMAM_DESC_COM_FIFO_RANGE         135
1317 #define IXGBE_RDMAM_DESC_COM_FIFO_COUNT         4
1318 #define IXGBE_RDMAM_DFC_CMD_FIFO_RANGE          48
1319 #define IXGBE_RDMAM_DFC_CMD_FIFO_COUNT          7
1320 #define IXGBE_RDMAM_RSC_HEADER_ADDR_RANGE       32
1321 #define IXGBE_RDMAM_RSC_HEADER_ADDR_COUNT       4
1322 #define IXGBE_RDMAM_TCN_STATUS_RAM_RANGE        256
1323 #define IXGBE_RDMAM_TCN_STATUS_RAM_COUNT        9
1324 #define IXGBE_RDMAM_WB_COLL_FIFO_RANGE          8
1325 #define IXGBE_RDMAM_WB_COLL_FIFO_COUNT          4
1326 #define IXGBE_RDMAM_QSC_CNT_RAM_RANGE           64
1327 #define IXGBE_RDMAM_QSC_CNT_RAM_COUNT           4
1328 #define IXGBE_RDMAM_QSC_FCOE_RAM_RANGE          512
1329 #define IXGBE_RDMAM_QSC_FCOE_RAM_COUNT          5
1330 #define IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE         32
1331 #define IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT         4
1332 #define IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE         128
1333 #define IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT         8
1334 #define IXGBE_RDMAM_QSC_RSC_RAM_RANGE           32
1335 #define IXGBE_RDMAM_QSC_RSC_RAM_COUNT           8
1336
1337 #define IXGBE_TXDESCIC_READY    0x80000000
1338
1339 /* Receive Checksum Control */
1340 #define IXGBE_RXCSUM_IPPCSE     0x00001000 /* IP payload checksum enable */
1341 #define IXGBE_RXCSUM_PCSD       0x00002000 /* packet checksum disabled */
1342
1343 /* FCRTL Bit Masks */
1344 #define IXGBE_FCRTL_XONE        0x80000000 /* XON enable */
1345 #define IXGBE_FCRTH_FCEN        0x80000000 /* Packet buffer fc enable */
1346
1347 /* PAP bit masks*/
1348 #define IXGBE_PAP_TXPAUSECNT_MASK       0x0000FFFF /* Pause counter mask */
1349
1350 /* RMCS Bit Masks */
1351 #define IXGBE_RMCS_RRM                  0x00000002 /* Rx Recycle Mode enable */
1352 /* Receive Arbitration Control: 0 Round Robin, 1 DFP */
1353 #define IXGBE_RMCS_RAC                  0x00000004
1354 /* Deficit Fixed Prio ena */
1355 #define IXGBE_RMCS_DFP                  IXGBE_RMCS_RAC
1356 #define IXGBE_RMCS_TFCE_802_3X          0x00000008 /* Tx Priority FC ena */
1357 #define IXGBE_RMCS_TFCE_PRIORITY        0x00000010 /* Tx Priority FC ena */
1358 #define IXGBE_RMCS_ARBDIS               0x00000040 /* Arbitration disable bit */
1359
1360 /* FCCFG Bit Masks */
1361 #define IXGBE_FCCFG_TFCE_802_3X         0x00000008 /* Tx link FC enable */
1362 #define IXGBE_FCCFG_TFCE_PRIORITY       0x00000010 /* Tx priority FC enable */
1363
1364 /* Interrupt register bitmasks */
1365
1366 /* Extended Interrupt Cause Read */
1367 #define IXGBE_EICR_RTX_QUEUE    0x0000FFFF /* RTx Queue Interrupt */
1368 #define IXGBE_EICR_FLOW_DIR     0x00010000 /* FDir Exception */
1369 #define IXGBE_EICR_RX_MISS      0x00020000 /* Packet Buffer Overrun */
1370 #define IXGBE_EICR_PCI          0x00040000 /* PCI Exception */
1371 #define IXGBE_EICR_MAILBOX      0x00080000 /* VF to PF Mailbox Interrupt */
1372 #define IXGBE_EICR_LSC          0x00100000 /* Link Status Change */
1373 #define IXGBE_EICR_LINKSEC      0x00200000 /* PN Threshold */
1374 #define IXGBE_EICR_MNG          0x00400000 /* Manageability Event Interrupt */
1375 #define IXGBE_EICR_TS           0x00800000 /* Thermal Sensor Event */
1376 #define IXGBE_EICR_GPI_SDP0     0x01000000 /* Gen Purpose Interrupt on SDP0 */
1377 #define IXGBE_EICR_GPI_SDP1     0x02000000 /* Gen Purpose Interrupt on SDP1 */
1378 #define IXGBE_EICR_GPI_SDP2     0x04000000 /* Gen Purpose Interrupt on SDP2 */
1379 #define IXGBE_EICR_ECC          0x10000000 /* ECC Error */
1380 #define IXGBE_EICR_PBUR         0x10000000 /* Packet Buffer Handler Error */
1381 #define IXGBE_EICR_DHER         0x20000000 /* Descriptor Handler Error */
1382 #define IXGBE_EICR_TCP_TIMER    0x40000000 /* TCP Timer */
1383 #define IXGBE_EICR_OTHER        0x80000000 /* Interrupt Cause Active */
1384
1385 /* Extended Interrupt Cause Set */
1386 #define IXGBE_EICS_RTX_QUEUE    IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1387 #define IXGBE_EICS_FLOW_DIR     IXGBE_EICR_FLOW_DIR  /* FDir Exception */
1388 #define IXGBE_EICS_RX_MISS      IXGBE_EICR_RX_MISS   /* Pkt Buffer Overrun */
1389 #define IXGBE_EICS_PCI          IXGBE_EICR_PCI /* PCI Exception */
1390 #define IXGBE_EICS_MAILBOX      IXGBE_EICR_MAILBOX   /* VF to PF Mailbox Int */
1391 #define IXGBE_EICS_LSC          IXGBE_EICR_LSC /* Link Status Change */
1392 #define IXGBE_EICS_MNG          IXGBE_EICR_MNG /* MNG Event Interrupt */
1393 #define IXGBE_EICS_GPI_SDP0     IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1394 #define IXGBE_EICS_GPI_SDP1     IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
1395 #define IXGBE_EICS_GPI_SDP2     IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1396 #define IXGBE_EICS_ECC          IXGBE_EICR_ECC /* ECC Error */
1397 #define IXGBE_EICS_PBUR         IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1398 #define IXGBE_EICS_DHER         IXGBE_EICR_DHER /* Desc Handler Error */
1399 #define IXGBE_EICS_TCP_TIMER    IXGBE_EICR_TCP_TIMER /* TCP Timer */
1400 #define IXGBE_EICS_OTHER        IXGBE_EICR_OTHER /* INT Cause Active */
1401
1402 /* Extended Interrupt Mask Set */
1403 #define IXGBE_EIMS_RTX_QUEUE    IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1404 #define IXGBE_EIMS_FLOW_DIR     IXGBE_EICR_FLOW_DIR /* FDir Exception */
1405 #define IXGBE_EIMS_RX_MISS      IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */
1406 #define IXGBE_EIMS_PCI          IXGBE_EICR_PCI /* PCI Exception */
1407 #define IXGBE_EIMS_MAILBOX      IXGBE_EICR_MAILBOX   /* VF to PF Mailbox Int */
1408 #define IXGBE_EIMS_LSC          IXGBE_EICR_LSC /* Link Status Change */
1409 #define IXGBE_EIMS_MNG          IXGBE_EICR_MNG /* MNG Event Interrupt */
1410 #define IXGBE_EIMS_TS           IXGBE_EICR_TS /* Thermal Sensor Event */
1411 #define IXGBE_EIMS_GPI_SDP0     IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1412 #define IXGBE_EIMS_GPI_SDP1     IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
1413 #define IXGBE_EIMS_GPI_SDP2     IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1414 #define IXGBE_EIMS_ECC          IXGBE_EICR_ECC /* ECC Error */
1415 #define IXGBE_EIMS_PBUR         IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1416 #define IXGBE_EIMS_DHER         IXGBE_EICR_DHER /* Descr Handler Error */
1417 #define IXGBE_EIMS_TCP_TIMER    IXGBE_EICR_TCP_TIMER /* TCP Timer */
1418 #define IXGBE_EIMS_OTHER        IXGBE_EICR_OTHER /* INT Cause Active */
1419
1420 /* Extended Interrupt Mask Clear */
1421 #define IXGBE_EIMC_RTX_QUEUE    IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1422 #define IXGBE_EIMC_FLOW_DIR     IXGBE_EICR_FLOW_DIR /* FDir Exception */
1423 #define IXGBE_EIMC_RX_MISS      IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */
1424 #define IXGBE_EIMC_PCI          IXGBE_EICR_PCI /* PCI Exception */
1425 #define IXGBE_EIMC_MAILBOX      IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
1426 #define IXGBE_EIMC_LSC          IXGBE_EICR_LSC /* Link Status Change */
1427 #define IXGBE_EIMC_MNG          IXGBE_EICR_MNG /* MNG Event Interrupt */
1428 #define IXGBE_EIMC_GPI_SDP0     IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1429 #define IXGBE_EIMC_GPI_SDP1     IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
1430 #define IXGBE_EIMC_GPI_SDP2     IXGBE_EICR_GPI_SDP2  /* SDP2 Gen Purpose Int */
1431 #define IXGBE_EIMC_ECC          IXGBE_EICR_ECC /* ECC Error */
1432 #define IXGBE_EIMC_PBUR         IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1433 #define IXGBE_EIMC_DHER         IXGBE_EICR_DHER /* Desc Handler Err */
1434 #define IXGBE_EIMC_TCP_TIMER    IXGBE_EICR_TCP_TIMER /* TCP Timer */
1435 #define IXGBE_EIMC_OTHER        IXGBE_EICR_OTHER /* INT Cause Active */
1436
1437 #define IXGBE_EIMS_ENABLE_MASK ( \
1438                                 IXGBE_EIMS_RTX_QUEUE    | \
1439                                 IXGBE_EIMS_LSC          | \
1440                                 IXGBE_EIMS_TCP_TIMER    | \
1441                                 IXGBE_EIMS_OTHER)
1442
1443 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
1444 #define IXGBE_IMIR_PORT_IM_EN   0x00010000  /* TCP port enable */
1445 #define IXGBE_IMIR_PORT_BP      0x00020000  /* TCP port check bypass */
1446 #define IXGBE_IMIREXT_SIZE_BP   0x00001000  /* Packet size bypass */
1447 #define IXGBE_IMIREXT_CTRL_URG  0x00002000  /* Check URG bit in header */
1448 #define IXGBE_IMIREXT_CTRL_ACK  0x00004000  /* Check ACK bit in header */
1449 #define IXGBE_IMIREXT_CTRL_PSH  0x00008000  /* Check PSH bit in header */
1450 #define IXGBE_IMIREXT_CTRL_RST  0x00010000  /* Check RST bit in header */
1451 #define IXGBE_IMIREXT_CTRL_SYN  0x00020000  /* Check SYN bit in header */
1452 #define IXGBE_IMIREXT_CTRL_FIN  0x00040000  /* Check FIN bit in header */
1453 #define IXGBE_IMIREXT_CTRL_BP   0x00080000  /* Bypass check of control bits */
1454 #define IXGBE_IMIR_SIZE_BP_82599        0x00001000 /* Packet size bypass */
1455 #define IXGBE_IMIR_CTRL_URG_82599       0x00002000 /* Check URG bit in header */
1456 #define IXGBE_IMIR_CTRL_ACK_82599       0x00004000 /* Check ACK bit in header */
1457 #define IXGBE_IMIR_CTRL_PSH_82599       0x00008000 /* Check PSH bit in header */
1458 #define IXGBE_IMIR_CTRL_RST_82599       0x00010000 /* Check RST bit in header */
1459 #define IXGBE_IMIR_CTRL_SYN_82599       0x00020000 /* Check SYN bit in header */
1460 #define IXGBE_IMIR_CTRL_FIN_82599       0x00040000 /* Check FIN bit in header */
1461 #define IXGBE_IMIR_CTRL_BP_82599        0x00080000 /* Bypass chk of ctrl bits */
1462 #define IXGBE_IMIR_LLI_EN_82599         0x00100000 /* Enables low latency Int */
1463 #define IXGBE_IMIR_RX_QUEUE_MASK_82599  0x0000007F /* Rx Queue Mask */
1464 #define IXGBE_IMIR_RX_QUEUE_SHIFT_82599 21 /* Rx Queue Shift */
1465 #define IXGBE_IMIRVP_PRIORITY_MASK      0x00000007 /* VLAN priority mask */
1466 #define IXGBE_IMIRVP_PRIORITY_EN        0x00000008 /* VLAN priority enable */
1467
1468 #define IXGBE_MAX_FTQF_FILTERS          128
1469 #define IXGBE_FTQF_PROTOCOL_MASK        0x00000003
1470 #define IXGBE_FTQF_PROTOCOL_TCP         0x00000000
1471 #define IXGBE_FTQF_PROTOCOL_UDP         0x00000001
1472 #define IXGBE_FTQF_PROTOCOL_SCTP        2
1473 #define IXGBE_FTQF_PRIORITY_MASK        0x00000007
1474 #define IXGBE_FTQF_PRIORITY_SHIFT       2
1475 #define IXGBE_FTQF_POOL_MASK            0x0000003F
1476 #define IXGBE_FTQF_POOL_SHIFT           8
1477 #define IXGBE_FTQF_5TUPLE_MASK_MASK     0x0000001F
1478 #define IXGBE_FTQF_5TUPLE_MASK_SHIFT    25
1479 #define IXGBE_FTQF_SOURCE_ADDR_MASK     0x1E
1480 #define IXGBE_FTQF_DEST_ADDR_MASK       0x1D
1481 #define IXGBE_FTQF_SOURCE_PORT_MASK     0x1B
1482 #define IXGBE_FTQF_DEST_PORT_MASK       0x17
1483 #define IXGBE_FTQF_PROTOCOL_COMP_MASK   0x0F
1484 #define IXGBE_FTQF_POOL_MASK_EN         0x40000000
1485 #define IXGBE_FTQF_QUEUE_ENABLE         0x80000000
1486
1487 /* Interrupt clear mask */
1488 #define IXGBE_IRQ_CLEAR_MASK    0xFFFFFFFF
1489
1490 /* Interrupt Vector Allocation Registers */
1491 #define IXGBE_IVAR_REG_NUM              25
1492 #define IXGBE_IVAR_REG_NUM_82599        64
1493 #define IXGBE_IVAR_TXRX_ENTRY           96
1494 #define IXGBE_IVAR_RX_ENTRY             64
1495 #define IXGBE_IVAR_RX_QUEUE(_i)         (0 + (_i))
1496 #define IXGBE_IVAR_TX_QUEUE(_i)         (64 + (_i))
1497 #define IXGBE_IVAR_TX_ENTRY             32
1498
1499 #define IXGBE_IVAR_TCP_TIMER_INDEX      96 /* 0 based index */
1500 #define IXGBE_IVAR_OTHER_CAUSES_INDEX   97 /* 0 based index */
1501
1502 #define IXGBE_MSIX_VECTOR(_i)           (0 + (_i))
1503
1504 #define IXGBE_IVAR_ALLOC_VAL            0x80 /* Interrupt Allocation valid */
1505
1506 /* ETYPE Queue Filter/Select Bit Masks */
1507 #define IXGBE_MAX_ETQF_FILTERS          8
1508 #define IXGBE_ETQF_FCOE                 0x08000000 /* bit 27 */
1509 #define IXGBE_ETQF_BCN                  0x10000000 /* bit 28 */
1510 #define IXGBE_ETQF_1588                 0x40000000 /* bit 30 */
1511 #define IXGBE_ETQF_FILTER_EN            0x80000000 /* bit 31 */
1512 #define IXGBE_ETQF_POOL_ENABLE          (1 << 26) /* bit 26 */
1513
1514 #define IXGBE_ETQS_RX_QUEUE             0x007F0000 /* bits 22:16 */
1515 #define IXGBE_ETQS_RX_QUEUE_SHIFT       16
1516 #define IXGBE_ETQS_LLI                  0x20000000 /* bit 29 */
1517 #define IXGBE_ETQS_QUEUE_EN             0x80000000 /* bit 31 */
1518
1519 /*
1520  * ETQF filter list: one static filter per filter consumer. This is
1521  *                 to avoid filter collisions later. Add new filters
1522  *                 here!!
1523  *
1524  * Current filters:
1525  *      EAPOL 802.1x (0x888e): Filter 0
1526  *      FCoE (0x8906):   Filter 2
1527  *      1588 (0x88f7):   Filter 3
1528  *      FIP  (0x8914):   Filter 4
1529  */
1530 #define IXGBE_ETQF_FILTER_EAPOL         0
1531 #define IXGBE_ETQF_FILTER_FCOE          2
1532 #define IXGBE_ETQF_FILTER_1588          3
1533 #define IXGBE_ETQF_FILTER_FIP           4
1534 /* VLAN Control Bit Masks */
1535 #define IXGBE_VLNCTRL_VET               0x0000FFFF  /* bits 0-15 */
1536 #define IXGBE_VLNCTRL_CFI               0x10000000  /* bit 28 */
1537 #define IXGBE_VLNCTRL_CFIEN             0x20000000  /* bit 29 */
1538 #define IXGBE_VLNCTRL_VFE               0x40000000  /* bit 30 */
1539 #define IXGBE_VLNCTRL_VME               0x80000000  /* bit 31 */
1540
1541 /* VLAN pool filtering masks */
1542 #define IXGBE_VLVF_VIEN                 0x80000000  /* filter is valid */
1543 #define IXGBE_VLVF_ENTRIES              64
1544 #define IXGBE_VLVF_VLANID_MASK          0x00000FFF
1545 /* Per VF Port VLAN insertion rules */
1546 #define IXGBE_VMVIR_VLANA_DEFAULT       0x40000000 /* Always use default VLAN */
1547 #define IXGBE_VMVIR_VLANA_NEVER         0x80000000 /* Never insert VLAN tag */
1548
1549 #define IXGBE_ETHERNET_IEEE_VLAN_TYPE   0x8100  /* 802.1q protocol */
1550
1551 /* STATUS Bit Masks */
1552 #define IXGBE_STATUS_LAN_ID             0x0000000C /* LAN ID */
1553 #define IXGBE_STATUS_LAN_ID_SHIFT       2 /* LAN ID Shift*/
1554 #define IXGBE_STATUS_GIO                0x00080000 /* GIO Master Ena Status */
1555
1556 #define IXGBE_STATUS_LAN_ID_0   0x00000000 /* LAN ID 0 */
1557 #define IXGBE_STATUS_LAN_ID_1   0x00000004 /* LAN ID 1 */
1558
1559 /* ESDP Bit Masks */
1560 #define IXGBE_ESDP_SDP0         0x00000001 /* SDP0 Data Value */
1561 #define IXGBE_ESDP_SDP1         0x00000002 /* SDP1 Data Value */
1562 #define IXGBE_ESDP_SDP2         0x00000004 /* SDP2 Data Value */
1563 #define IXGBE_ESDP_SDP3         0x00000008 /* SDP3 Data Value */
1564 #define IXGBE_ESDP_SDP4         0x00000010 /* SDP4 Data Value */
1565 #define IXGBE_ESDP_SDP5         0x00000020 /* SDP5 Data Value */
1566 #define IXGBE_ESDP_SDP6         0x00000040 /* SDP6 Data Value */
1567 #define IXGBE_ESDP_SDP0_DIR     0x00000100 /* SDP0 IO direction */
1568 #define IXGBE_ESDP_SDP1_DIR     0x00000200 /* SDP1 IO direction */
1569 #define IXGBE_ESDP_SDP4_DIR     0x00001000 /* SDP4 IO direction */
1570 #define IXGBE_ESDP_SDP5_DIR     0x00002000 /* SDP5 IO direction */
1571 #define IXGBE_ESDP_SDP0_NATIVE  0x00010000 /* SDP0 IO mode */
1572 #define IXGBE_ESDP_SDP1_NATIVE  0x00020000 /* SDP1 IO mode */
1573
1574
1575 /* LEDCTL Bit Masks */
1576 #define IXGBE_LED_IVRT_BASE             0x00000040
1577 #define IXGBE_LED_BLINK_BASE            0x00000080
1578 #define IXGBE_LED_MODE_MASK_BASE        0x0000000F
1579 #define IXGBE_LED_OFFSET(_base, _i)     (_base << (8 * (_i)))
1580 #define IXGBE_LED_MODE_SHIFT(_i)        (8*(_i))
1581 #define IXGBE_LED_IVRT(_i)      IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i)
1582 #define IXGBE_LED_BLINK(_i)     IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i)
1583 #define IXGBE_LED_MODE_MASK(_i) IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i)
1584
1585 /* LED modes */
1586 #define IXGBE_LED_LINK_UP       0x0
1587 #define IXGBE_LED_LINK_10G      0x1
1588 #define IXGBE_LED_MAC           0x2
1589 #define IXGBE_LED_FILTER        0x3
1590 #define IXGBE_LED_LINK_ACTIVE   0x4
1591 #define IXGBE_LED_LINK_1G       0x5
1592 #define IXGBE_LED_ON            0xE
1593 #define IXGBE_LED_OFF           0xF
1594
1595 /* AUTOC Bit Masks */
1596 #define IXGBE_AUTOC_KX4_KX_SUPP_MASK 0xC0000000
1597 #define IXGBE_AUTOC_KX4_SUPP    0x80000000
1598 #define IXGBE_AUTOC_KX_SUPP     0x40000000
1599 #define IXGBE_AUTOC_PAUSE       0x30000000
1600 #define IXGBE_AUTOC_ASM_PAUSE   0x20000000
1601 #define IXGBE_AUTOC_SYM_PAUSE   0x10000000
1602 #define IXGBE_AUTOC_RF          0x08000000
1603 #define IXGBE_AUTOC_PD_TMR      0x06000000
1604 #define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000
1605 #define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000
1606 #define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000
1607 #define IXGBE_AUTOC_FECA        0x00040000
1608 #define IXGBE_AUTOC_FECR        0x00020000
1609 #define IXGBE_AUTOC_KR_SUPP     0x00010000
1610 #define IXGBE_AUTOC_AN_RESTART  0x00001000
1611 #define IXGBE_AUTOC_FLU         0x00000001
1612 #define IXGBE_AUTOC_LMS_SHIFT   13
1613 #define IXGBE_AUTOC_LMS_10G_SERIAL      (0x3 << IXGBE_AUTOC_LMS_SHIFT)
1614 #define IXGBE_AUTOC_LMS_KX4_KX_KR       (0x4 << IXGBE_AUTOC_LMS_SHIFT)
1615 #define IXGBE_AUTOC_LMS_SGMII_1G_100M   (0x5 << IXGBE_AUTOC_LMS_SHIFT)
1616 #define IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
1617 #define IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII (0x7 << IXGBE_AUTOC_LMS_SHIFT)
1618 #define IXGBE_AUTOC_LMS_MASK            (0x7 << IXGBE_AUTOC_LMS_SHIFT)
1619 #define IXGBE_AUTOC_LMS_1G_LINK_NO_AN   (0x0 << IXGBE_AUTOC_LMS_SHIFT)
1620 #define IXGBE_AUTOC_LMS_10G_LINK_NO_AN  (0x1 << IXGBE_AUTOC_LMS_SHIFT)
1621 #define IXGBE_AUTOC_LMS_1G_AN           (0x2 << IXGBE_AUTOC_LMS_SHIFT)
1622 #define IXGBE_AUTOC_LMS_KX4_AN          (0x4 << IXGBE_AUTOC_LMS_SHIFT)
1623 #define IXGBE_AUTOC_LMS_KX4_AN_1G_AN    (0x6 << IXGBE_AUTOC_LMS_SHIFT)
1624 #define IXGBE_AUTOC_LMS_ATTACH_TYPE     (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1625
1626 #define IXGBE_AUTOC_1G_PMA_PMD_MASK     0x00000200
1627 #define IXGBE_AUTOC_1G_PMA_PMD_SHIFT    9
1628 #define IXGBE_AUTOC_10G_PMA_PMD_MASK    0x00000180
1629 #define IXGBE_AUTOC_10G_PMA_PMD_SHIFT   7
1630 #define IXGBE_AUTOC_10G_XAUI    (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1631 #define IXGBE_AUTOC_10G_KX4     (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1632 #define IXGBE_AUTOC_10G_CX4     (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1633 #define IXGBE_AUTOC_1G_BX       (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1634 #define IXGBE_AUTOC_1G_KX       (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1635 #define IXGBE_AUTOC_1G_SFI      (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1636 #define IXGBE_AUTOC_1G_KX_BX    (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1637
1638 #define IXGBE_AUTOC2_UPPER_MASK 0xFFFF0000
1639 #define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK    0x00030000
1640 #define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT   16
1641 #define IXGBE_AUTOC2_10G_KR     (0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1642 #define IXGBE_AUTOC2_10G_XFI    (0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1643 #define IXGBE_AUTOC2_10G_SFI    (0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1644
1645 #define IXGBE_MACC_FLU          0x00000001
1646 #define IXGBE_MACC_FSV_10G      0x00030000
1647 #define IXGBE_MACC_FS           0x00040000
1648 #define IXGBE_MAC_RX2TX_LPBK    0x00000002
1649
1650 /* LINKS Bit Masks */
1651 #define IXGBE_LINKS_KX_AN_COMP  0x80000000
1652 #define IXGBE_LINKS_UP          0x40000000
1653 #define IXGBE_LINKS_SPEED       0x20000000
1654 #define IXGBE_LINKS_MODE        0x18000000
1655 #define IXGBE_LINKS_RX_MODE     0x06000000
1656 #define IXGBE_LINKS_TX_MODE     0x01800000
1657 #define IXGBE_LINKS_XGXS_EN     0x00400000
1658 #define IXGBE_LINKS_SGMII_EN    0x02000000
1659 #define IXGBE_LINKS_PCS_1G_EN   0x00200000
1660 #define IXGBE_LINKS_1G_AN_EN    0x00100000
1661 #define IXGBE_LINKS_KX_AN_IDLE  0x00080000
1662 #define IXGBE_LINKS_1G_SYNC     0x00040000
1663 #define IXGBE_LINKS_10G_ALIGN   0x00020000
1664 #define IXGBE_LINKS_10G_LANE_SYNC       0x00017000
1665 #define IXGBE_LINKS_TL_FAULT            0x00001000
1666 #define IXGBE_LINKS_SIGNAL              0x00000F00
1667
1668 #define IXGBE_LINKS_SPEED_82599         0x30000000
1669 #define IXGBE_LINKS_SPEED_10G_82599     0x30000000
1670 #define IXGBE_LINKS_SPEED_1G_82599      0x20000000
1671 #define IXGBE_LINKS_SPEED_100_82599     0x10000000
1672 #define IXGBE_LINK_UP_TIME              90 /* 9.0 Seconds */
1673 #define IXGBE_AUTO_NEG_TIME             45 /* 4.5 Seconds */
1674
1675 #define IXGBE_LINKS2_AN_SUPPORTED       0x00000040
1676
1677 /* PCS1GLSTA Bit Masks */
1678 #define IXGBE_PCS1GLSTA_LINK_OK         1
1679 #define IXGBE_PCS1GLSTA_SYNK_OK         0x10
1680 #define IXGBE_PCS1GLSTA_AN_COMPLETE     0x10000
1681 #define IXGBE_PCS1GLSTA_AN_PAGE_RX      0x20000
1682 #define IXGBE_PCS1GLSTA_AN_TIMED_OUT    0x40000
1683 #define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000
1684 #define IXGBE_PCS1GLSTA_AN_ERROR_RWS    0x100000
1685
1686 #define IXGBE_PCS1GANA_SYM_PAUSE        0x80
1687 #define IXGBE_PCS1GANA_ASM_PAUSE        0x100
1688
1689 /* PCS1GLCTL Bit Masks */
1690 #define IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN 0x00040000 /* PCS 1G autoneg to en */
1691 #define IXGBE_PCS1GLCTL_FLV_LINK_UP     1
1692 #define IXGBE_PCS1GLCTL_FORCE_LINK      0x20
1693 #define IXGBE_PCS1GLCTL_LOW_LINK_LATCH  0x40
1694 #define IXGBE_PCS1GLCTL_AN_ENABLE       0x10000
1695 #define IXGBE_PCS1GLCTL_AN_RESTART      0x20000
1696
1697 /* ANLP1 Bit Masks */
1698 #define IXGBE_ANLP1_PAUSE               0x0C00
1699 #define IXGBE_ANLP1_SYM_PAUSE           0x0400
1700 #define IXGBE_ANLP1_ASM_PAUSE           0x0800
1701 #define IXGBE_ANLP1_AN_STATE_MASK       0x000f0000
1702
1703 /* SW Semaphore Register bitmasks */
1704 #define IXGBE_SWSM_SMBI         0x00000001 /* Driver Semaphore bit */
1705 #define IXGBE_SWSM_SWESMBI      0x00000002 /* FW Semaphore bit */
1706 #define IXGBE_SWSM_WMNG         0x00000004 /* Wake MNG Clock */
1707 #define IXGBE_SWFW_REGSMP       0x80000000 /* Register Semaphore bit 31 */
1708
1709 /* SW_FW_SYNC/GSSR definitions */
1710 #define IXGBE_GSSR_EEP_SM       0x0001
1711 #define IXGBE_GSSR_PHY0_SM      0x0002
1712 #define IXGBE_GSSR_PHY1_SM      0x0004
1713 #define IXGBE_GSSR_MAC_CSR_SM   0x0008
1714 #define IXGBE_GSSR_FLASH_SM     0x0010
1715 #define IXGBE_GSSR_SW_MNG_SM    0x0400
1716
1717 /* FW Status register bitmask */
1718 #define IXGBE_FWSTS_FWRI        0x00000200 /* Firmware Reset Indication */
1719
1720 /* EEC Register */
1721 #define IXGBE_EEC_SK            0x00000001 /* EEPROM Clock */
1722 #define IXGBE_EEC_CS            0x00000002 /* EEPROM Chip Select */
1723 #define IXGBE_EEC_DI            0x00000004 /* EEPROM Data In */
1724 #define IXGBE_EEC_DO            0x00000008 /* EEPROM Data Out */
1725 #define IXGBE_EEC_FWE_MASK      0x00000030 /* FLASH Write Enable */
1726 #define IXGBE_EEC_FWE_DIS       0x00000010 /* Disable FLASH writes */
1727 #define IXGBE_EEC_FWE_EN        0x00000020 /* Enable FLASH writes */
1728 #define IXGBE_EEC_FWE_SHIFT     4
1729 #define IXGBE_EEC_REQ           0x00000040 /* EEPROM Access Request */
1730 #define IXGBE_EEC_GNT           0x00000080 /* EEPROM Access Grant */
1731 #define IXGBE_EEC_PRES          0x00000100 /* EEPROM Present */
1732 #define IXGBE_EEC_ARD           0x00000200 /* EEPROM Auto Read Done */
1733 #define IXGBE_EEC_FLUP          0x00800000 /* Flash update command */
1734 #define IXGBE_EEC_SEC1VAL       0x02000000 /* Sector 1 Valid */
1735 #define IXGBE_EEC_FLUDONE       0x04000000 /* Flash update done */
1736 /* EEPROM Addressing bits based on type (0-small, 1-large) */
1737 #define IXGBE_EEC_ADDR_SIZE     0x00000400
1738 #define IXGBE_EEC_SIZE          0x00007800 /* EEPROM Size */
1739 #define IXGBE_EERD_MAX_ADDR     0x00003FFF /* EERD alows 14 bits for addr. */
1740
1741 #define IXGBE_EEC_SIZE_SHIFT            11
1742 #define IXGBE_EEPROM_WORD_SIZE_SHIFT    6
1743 #define IXGBE_EEPROM_OPCODE_BITS        8
1744
1745 /* Part Number String Length */
1746 #define IXGBE_PBANUM_LENGTH     11
1747
1748 /* Checksum and EEPROM pointers */
1749 #define IXGBE_PBANUM_PTR_GUARD  0xFAFA
1750 #define IXGBE_EEPROM_CHECKSUM   0x3F
1751 #define IXGBE_EEPROM_SUM        0xBABA
1752 #define IXGBE_PCIE_ANALOG_PTR   0x03
1753 #define IXGBE_ATLAS0_CONFIG_PTR 0x04
1754 #define IXGBE_PHY_PTR           0x04
1755 #define IXGBE_ATLAS1_CONFIG_PTR 0x05
1756 #define IXGBE_OPTION_ROM_PTR    0x05
1757 #define IXGBE_PCIE_GENERAL_PTR  0x06
1758 #define IXGBE_PCIE_CONFIG0_PTR  0x07
1759 #define IXGBE_PCIE_CONFIG1_PTR  0x08
1760 #define IXGBE_CORE0_PTR         0x09
1761 #define IXGBE_CORE1_PTR         0x0A
1762 #define IXGBE_MAC0_PTR          0x0B
1763 #define IXGBE_MAC1_PTR          0x0C
1764 #define IXGBE_CSR0_CONFIG_PTR   0x0D
1765 #define IXGBE_CSR1_CONFIG_PTR   0x0E
1766 #define IXGBE_FW_PTR            0x0F
1767 #define IXGBE_PBANUM0_PTR       0x15
1768 #define IXGBE_PBANUM1_PTR       0x16
1769 #define IXGBE_ALT_MAC_ADDR_PTR  0x37
1770 #define IXGBE_FREE_SPACE_PTR    0X3E
1771
1772 /* External Thermal Sensor Config */
1773 #define IXGBE_ETS_CFG                   0x26
1774 #define IXGBE_ETS_LTHRES_DELTA_MASK     0x07C0
1775 #define IXGBE_ETS_LTHRES_DELTA_SHIFT    6
1776 #define IXGBE_ETS_TYPE_MASK             0x0038
1777 #define IXGBE_ETS_TYPE_SHIFT            3
1778 #define IXGBE_ETS_TYPE_EMC              0x000
1779 #define IXGBE_ETS_NUM_SENSORS_MASK      0x0007
1780 #define IXGBE_ETS_DATA_LOC_MASK         0x3C00
1781 #define IXGBE_ETS_DATA_LOC_SHIFT        10
1782 #define IXGBE_ETS_DATA_INDEX_MASK       0x0300
1783 #define IXGBE_ETS_DATA_INDEX_SHIFT      8
1784 #define IXGBE_ETS_DATA_HTHRESH_MASK     0x00FF
1785
1786 #define IXGBE_SAN_MAC_ADDR_PTR          0x28
1787 #define IXGBE_DEVICE_CAPS               0x2C
1788 #define IXGBE_SERIAL_NUMBER_MAC_ADDR    0x11
1789 #define IXGBE_PCIE_MSIX_82599_CAPS      0x72
1790 #define IXGBE_MAX_MSIX_VECTORS_82599    0x40
1791 #define IXGBE_PCIE_MSIX_82598_CAPS      0x62
1792 #define IXGBE_MAX_MSIX_VECTORS_82598    0x13
1793
1794 /* MSI-X capability fields masks */
1795 #define IXGBE_PCIE_MSIX_TBL_SZ_MASK     0x7FF
1796
1797 /* Legacy EEPROM word offsets */
1798 #define IXGBE_ISCSI_BOOT_CAPS           0x0033
1799 #define IXGBE_ISCSI_SETUP_PORT_0        0x0030
1800 #define IXGBE_ISCSI_SETUP_PORT_1        0x0034
1801
1802 /* EEPROM Commands - SPI */
1803 #define IXGBE_EEPROM_MAX_RETRY_SPI      5000 /* Max wait 5ms for RDY signal */
1804 #define IXGBE_EEPROM_STATUS_RDY_SPI     0x01
1805 #define IXGBE_EEPROM_READ_OPCODE_SPI    0x03  /* EEPROM read opcode */
1806 #define IXGBE_EEPROM_WRITE_OPCODE_SPI   0x02  /* EEPROM write opcode */
1807 #define IXGBE_EEPROM_A8_OPCODE_SPI      0x08  /* opcode bit-3 = addr bit-8 */
1808 #define IXGBE_EEPROM_WREN_OPCODE_SPI    0x06  /* EEPROM set Write Ena latch */
1809 /* EEPROM reset Write Enable latch */
1810 #define IXGBE_EEPROM_WRDI_OPCODE_SPI    0x04
1811 #define IXGBE_EEPROM_RDSR_OPCODE_SPI    0x05  /* EEPROM read Status reg */
1812 #define IXGBE_EEPROM_WRSR_OPCODE_SPI    0x01  /* EEPROM write Status reg */
1813 #define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20  /* EEPROM ERASE 4KB */
1814 #define IXGBE_EEPROM_ERASE64K_OPCODE_SPI        0xD8  /* EEPROM ERASE 64KB */
1815 #define IXGBE_EEPROM_ERASE256_OPCODE_SPI        0xDB  /* EEPROM ERASE 256B */
1816
1817 /* EEPROM Read Register */
1818 #define IXGBE_EEPROM_RW_REG_DATA        16 /* data offset in EEPROM read reg */
1819 #define IXGBE_EEPROM_RW_REG_DONE        2 /* Offset to READ done bit */
1820 #define IXGBE_EEPROM_RW_REG_START       1 /* First bit to start operation */
1821 #define IXGBE_EEPROM_RW_ADDR_SHIFT      2 /* Shift to the address bits */
1822 #define IXGBE_NVM_POLL_WRITE            1 /* Flag for polling for wr complete */
1823 #define IXGBE_NVM_POLL_READ             0 /* Flag for polling for rd complete */
1824
1825 #define IXGBE_ETH_LENGTH_OF_ADDRESS     6
1826
1827 #define IXGBE_EEPROM_PAGE_SIZE_MAX      128
1828 #define IXGBE_EEPROM_RD_BUFFER_MAX_COUNT        512 /* words rd in burst */
1829 #define IXGBE_EEPROM_WR_BUFFER_MAX_COUNT        256 /* words wr in burst */
1830
1831 #ifndef IXGBE_EEPROM_GRANT_ATTEMPTS
1832 #define IXGBE_EEPROM_GRANT_ATTEMPTS     1000 /* EEPROM attempts to gain grant */
1833 #endif
1834
1835 #ifndef IXGBE_EERD_EEWR_ATTEMPTS
1836 /* Number of 5 microseconds we wait for EERD read and
1837  * EERW write to complete */
1838 #define IXGBE_EERD_EEWR_ATTEMPTS        100000
1839 #endif
1840
1841 #ifndef IXGBE_FLUDONE_ATTEMPTS
1842 /* # attempts we wait for flush update to complete */
1843 #define IXGBE_FLUDONE_ATTEMPTS          20000
1844 #endif
1845
1846 #define IXGBE_PCIE_CTRL2                0x5   /* PCIe Control 2 Offset */
1847 #define IXGBE_PCIE_CTRL2_DUMMY_ENABLE   0x8   /* Dummy Function Enable */
1848 #define IXGBE_PCIE_CTRL2_LAN_DISABLE    0x2   /* LAN PCI Disable */
1849 #define IXGBE_PCIE_CTRL2_DISABLE_SELECT 0x1   /* LAN Disable Select */
1850
1851 #define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET         0x0
1852 #define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET         0x3
1853 #define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP         0x1
1854 #define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS         0x2
1855 #define IXGBE_FW_LESM_PARAMETERS_PTR            0x2
1856 #define IXGBE_FW_LESM_STATE_1                   0x1
1857 #define IXGBE_FW_LESM_STATE_ENABLED             0x8000 /* LESM Enable bit */
1858 #define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR   0x4
1859 #define IXGBE_FW_PATCH_VERSION_4                0x7
1860 #define IXGBE_FCOE_IBA_CAPS_BLK_PTR             0x33 /* iSCSI/FCOE block */
1861 #define IXGBE_FCOE_IBA_CAPS_FCOE                0x20 /* FCOE flags */
1862 #define IXGBE_ISCSI_FCOE_BLK_PTR                0x17 /* iSCSI/FCOE block */
1863 #define IXGBE_ISCSI_FCOE_FLAGS_OFFSET           0x0 /* FCOE flags */
1864 #define IXGBE_ISCSI_FCOE_FLAGS_ENABLE           0x1 /* FCOE flags enable bit */
1865 #define IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR          0x27 /* Alt. SAN MAC block */
1866 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET      0x0 /* Alt SAN MAC capability */
1867 #define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET     0x1 /* Alt SAN MAC 0 offset */
1868 #define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET     0x4 /* Alt SAN MAC 1 offset */
1869 #define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET      0x7 /* Alt WWNN prefix offset */
1870 #define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET      0x8 /* Alt WWPN prefix offset */
1871 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC      0x0 /* Alt SAN MAC exists */
1872 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN      0x1 /* Alt WWN base exists */
1873
1874 #define IXGBE_DEVICE_CAPS_WOL_PORT0_1   0x4 /* WoL supported on ports 0 & 1 */
1875 #define IXGBE_DEVICE_CAPS_WOL_PORT0     0x8 /* WoL supported on port 0 */
1876 #define IXGBE_DEVICE_CAPS_WOL_MASK      0xC /* Mask for WoL capabilities */
1877
1878 /* PCI Bus Info */
1879 #define IXGBE_PCI_DEVICE_STATUS         0xAA
1880 #define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING     0x0020
1881 #define IXGBE_PCI_LINK_STATUS           0xB2
1882 #define IXGBE_PCI_DEVICE_CONTROL2       0xC8
1883 #define IXGBE_PCI_LINK_WIDTH            0x3F0
1884 #define IXGBE_PCI_LINK_WIDTH_1          0x10
1885 #define IXGBE_PCI_LINK_WIDTH_2          0x20
1886 #define IXGBE_PCI_LINK_WIDTH_4          0x40
1887 #define IXGBE_PCI_LINK_WIDTH_8          0x80
1888 #define IXGBE_PCI_LINK_SPEED            0xF
1889 #define IXGBE_PCI_LINK_SPEED_2500       0x1
1890 #define IXGBE_PCI_LINK_SPEED_5000       0x2
1891 #define IXGBE_PCI_LINK_SPEED_8000       0x3
1892 #define IXGBE_PCI_HEADER_TYPE_REGISTER  0x0E
1893 #define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80
1894 #define IXGBE_PCI_DEVICE_CONTROL2_16ms  0x0005
1895
1896 /* Number of 100 microseconds we wait for PCI Express master disable */
1897 #define IXGBE_PCI_MASTER_DISABLE_TIMEOUT        800
1898
1899 /* Check whether address is multicast. This is little-endian specific check.*/
1900 #define IXGBE_IS_MULTICAST(Address) \
1901                 (bool)(((u8 *)(Address))[0] & ((u8)0x01))
1902
1903 /* Check whether an address is broadcast. */
1904 #define IXGBE_IS_BROADCAST(Address) \
1905                 ((((u8 *)(Address))[0] == ((u8)0xff)) && \
1906                 (((u8 *)(Address))[1] == ((u8)0xff)))
1907
1908 /* RAH */
1909 #define IXGBE_RAH_VIND_MASK     0x003C0000
1910 #define IXGBE_RAH_VIND_SHIFT    18
1911 #define IXGBE_RAH_AV            0x80000000
1912 #define IXGBE_CLEAR_VMDQ_ALL    0xFFFFFFFF
1913
1914 /* Header split receive */
1915 #define IXGBE_RFCTL_ISCSI_DIS           0x00000001
1916 #define IXGBE_RFCTL_ISCSI_DWC_MASK      0x0000003E
1917 #define IXGBE_RFCTL_ISCSI_DWC_SHIFT     1
1918 #define IXGBE_RFCTL_RSC_DIS             0x00000010
1919 #define IXGBE_RFCTL_NFSW_DIS            0x00000040
1920 #define IXGBE_RFCTL_NFSR_DIS            0x00000080
1921 #define IXGBE_RFCTL_NFS_VER_MASK        0x00000300
1922 #define IXGBE_RFCTL_NFS_VER_SHIFT       8
1923 #define IXGBE_RFCTL_NFS_VER_2           0
1924 #define IXGBE_RFCTL_NFS_VER_3           1
1925 #define IXGBE_RFCTL_NFS_VER_4           2
1926 #define IXGBE_RFCTL_IPV6_DIS            0x00000400
1927 #define IXGBE_RFCTL_IPV6_XSUM_DIS       0x00000800
1928 #define IXGBE_RFCTL_IPFRSP_DIS          0x00004000
1929 #define IXGBE_RFCTL_IPV6_EX_DIS         0x00010000
1930 #define IXGBE_RFCTL_NEW_IPV6_EXT_DIS    0x00020000
1931
1932 /* Transmit Config masks */
1933 #define IXGBE_TXDCTL_ENABLE             0x02000000 /* Ena specific Tx Queue */
1934 #define IXGBE_TXDCTL_SWFLSH             0x04000000 /* Tx Desc. wr-bk flushing */
1935 #define IXGBE_TXDCTL_WTHRESH_SHIFT      16 /* shift to WTHRESH bits */
1936 /* Enable short packet padding to 64 bytes */
1937 #define IXGBE_TX_PAD_ENABLE             0x00000400
1938 #define IXGBE_JUMBO_FRAME_ENABLE        0x00000004  /* Allow jumbo frames */
1939 /* This allows for 16K packets + 4k for vlan */
1940 #define IXGBE_MAX_FRAME_SZ              0x40040000
1941
1942 #define IXGBE_TDWBAL_HEAD_WB_ENABLE     0x1 /* Tx head write-back enable */
1943 #define IXGBE_TDWBAL_SEQNUM_WB_ENABLE   0x2 /* Tx seq# write-back enable */
1944
1945 /* Receive Config masks */
1946 #define IXGBE_RXCTRL_RXEN               0x00000001 /* Enable Receiver */
1947 #define IXGBE_RXCTRL_DMBYPS             0x00000002 /* Desc Monitor Bypass */
1948 #define IXGBE_RXDCTL_ENABLE             0x02000000 /* Ena specific Rx Queue */
1949 #define IXGBE_RXDCTL_SWFLSH             0x04000000 /* Rx Desc wr-bk flushing */
1950 #define IXGBE_RXDCTL_RLPMLMASK          0x00003FFF /* X540 supported only */
1951 #define IXGBE_RXDCTL_RLPML_EN           0x00008000
1952 #define IXGBE_RXDCTL_VME                0x40000000 /* VLAN mode enable */
1953
1954 #define IXGBE_TSYNCTXCTL_VALID          0x00000001 /* Tx timestamp valid */
1955 #define IXGBE_TSYNCTXCTL_ENABLED        0x00000010 /* Tx timestamping enabled */
1956
1957 #define IXGBE_TSYNCRXCTL_VALID          0x00000001 /* Rx timestamp valid */
1958 #define IXGBE_TSYNCRXCTL_TYPE_MASK      0x0000000E /* Rx type mask */
1959 #define IXGBE_TSYNCRXCTL_TYPE_L2_V2     0x00
1960 #define IXGBE_TSYNCRXCTL_TYPE_L4_V1     0x02
1961 #define IXGBE_TSYNCRXCTL_TYPE_L2_L4_V2  0x04
1962 #define IXGBE_TSYNCRXCTL_TYPE_EVENT_V2  0x0A
1963 #define IXGBE_TSYNCRXCTL_ENABLED        0x00000010 /* Rx Timestamping enabled */
1964
1965 #define IXGBE_RXMTRL_V1_CTRLT_MASK      0x000000FF
1966 #define IXGBE_RXMTRL_V1_SYNC_MSG        0x00
1967 #define IXGBE_RXMTRL_V1_DELAY_REQ_MSG   0x01
1968 #define IXGBE_RXMTRL_V1_FOLLOWUP_MSG    0x02
1969 #define IXGBE_RXMTRL_V1_DELAY_RESP_MSG  0x03
1970 #define IXGBE_RXMTRL_V1_MGMT_MSG        0x04
1971
1972 #define IXGBE_RXMTRL_V2_MSGID_MASK      0x0000FF00
1973 #define IXGBE_RXMTRL_V2_SYNC_MSG        0x0000
1974 #define IXGBE_RXMTRL_V2_DELAY_REQ_MSG   0x0100
1975 #define IXGBE_RXMTRL_V2_PDELAY_REQ_MSG  0x0200
1976 #define IXGBE_RXMTRL_V2_PDELAY_RESP_MSG 0x0300
1977 #define IXGBE_RXMTRL_V2_FOLLOWUP_MSG    0x0800
1978 #define IXGBE_RXMTRL_V2_DELAY_RESP_MSG  0x0900
1979 #define IXGBE_RXMTRL_V2_PDELAY_FOLLOWUP_MSG 0x0A00
1980 #define IXGBE_RXMTRL_V2_ANNOUNCE_MSG    0x0B00
1981 #define IXGBE_RXMTRL_V2_SIGNALLING_MSG  0x0C00
1982 #define IXGBE_RXMTRL_V2_MGMT_MSG        0x0D00
1983
1984 #define IXGBE_FCTRL_SBP         0x00000002 /* Store Bad Packet */
1985 #define IXGBE_FCTRL_MPE         0x00000100 /* Multicast Promiscuous Ena*/
1986 #define IXGBE_FCTRL_UPE         0x00000200 /* Unicast Promiscuous Ena */
1987 #define IXGBE_FCTRL_BAM         0x00000400 /* Broadcast Accept Mode */
1988 #define IXGBE_FCTRL_PMCF        0x00001000 /* Pass MAC Control Frames */
1989 #define IXGBE_FCTRL_DPF         0x00002000 /* Discard Pause Frame */
1990 /* Receive Priority Flow Control Enable */
1991 #define IXGBE_FCTRL_RPFCE       0x00004000
1992 #define IXGBE_FCTRL_RFCE        0x00008000 /* Receive Flow Control Ena */
1993 #define IXGBE_MFLCN_PMCF        0x00000001 /* Pass MAC Control Frames */
1994 #define IXGBE_MFLCN_DPF         0x00000002 /* Discard Pause Frame */
1995 #define IXGBE_MFLCN_RPFCE       0x00000004 /* Receive Priority FC Enable */
1996 #define IXGBE_MFLCN_RFCE        0x00000008 /* Receive FC Enable */
1997 #define IXGBE_MFLCN_RPFCE_MASK  0x00000FF4 /* Rx Priority FC bitmap mask */
1998 #define IXGBE_MFLCN_RPFCE_SHIFT 4 /* Rx Priority FC bitmap shift */
1999
2000 /* Multiple Receive Queue Control */
2001 #define IXGBE_MRQC_RSSEN        0x00000001  /* RSS Enable */
2002 #define IXGBE_MRQC_MRQE_MASK    0xF /* Bits 3:0 */
2003 #define IXGBE_MRQC_RT8TCEN      0x00000002 /* 8 TC no RSS */
2004 #define IXGBE_MRQC_RT4TCEN      0x00000003 /* 4 TC no RSS */
2005 #define IXGBE_MRQC_RTRSS8TCEN   0x00000004 /* 8 TC w/ RSS */
2006 #define IXGBE_MRQC_RTRSS4TCEN   0x00000005 /* 4 TC w/ RSS */
2007 #define IXGBE_MRQC_VMDQEN       0x00000008 /* VMDq2 64 pools no RSS */
2008 #define IXGBE_MRQC_VMDQRSS32EN  0x0000000A /* VMDq2 32 pools w/ RSS */
2009 #define IXGBE_MRQC_VMDQRSS64EN  0x0000000B /* VMDq2 64 pools w/ RSS */
2010 #define IXGBE_MRQC_VMDQRT8TCEN  0x0000000C /* VMDq2/RT 16 pool 8 TC */
2011 #define IXGBE_MRQC_VMDQRT4TCEN  0x0000000D /* VMDq2/RT 32 pool 4 TC */
2012 #define IXGBE_MRQC_RSS_FIELD_MASK       0xFFFF0000
2013 #define IXGBE_MRQC_RSS_FIELD_IPV4_TCP   0x00010000
2014 #define IXGBE_MRQC_RSS_FIELD_IPV4       0x00020000
2015 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000
2016 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX    0x00080000
2017 #define IXGBE_MRQC_RSS_FIELD_IPV6       0x00100000
2018 #define IXGBE_MRQC_RSS_FIELD_IPV6_TCP   0x00200000
2019 #define IXGBE_MRQC_RSS_FIELD_IPV4_UDP   0x00400000
2020 #define IXGBE_MRQC_RSS_FIELD_IPV6_UDP   0x00800000
2021 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000
2022 #define IXGBE_MRQC_L3L4TXSWEN           0x00008000
2023
2024 /* Queue Drop Enable */
2025 #define IXGBE_QDE_ENABLE        0x00000001
2026 #define IXGBE_QDE_IDX_MASK      0x00007F00
2027 #define IXGBE_QDE_IDX_SHIFT     8
2028 #define IXGBE_QDE_WRITE         0x00010000
2029 #define IXGBE_QDE_READ          0x00020000
2030
2031 #define IXGBE_TXD_POPTS_IXSM    0x01 /* Insert IP checksum */
2032 #define IXGBE_TXD_POPTS_TXSM    0x02 /* Insert TCP/UDP checksum */
2033 #define IXGBE_TXD_CMD_EOP       0x01000000 /* End of Packet */
2034 #define IXGBE_TXD_CMD_IFCS      0x02000000 /* Insert FCS (Ethernet CRC) */
2035 #define IXGBE_TXD_CMD_IC        0x04000000 /* Insert Checksum */
2036 #define IXGBE_TXD_CMD_RS        0x08000000 /* Report Status */
2037 #define IXGBE_TXD_CMD_DEXT      0x20000000 /* Desc extension (0 = legacy) */
2038 #define IXGBE_TXD_CMD_VLE       0x40000000 /* Add VLAN tag */
2039 #define IXGBE_TXD_STAT_DD       0x00000001 /* Descriptor Done */
2040
2041 #define IXGBE_RXDADV_IPSEC_STATUS_SECP          0x00020000
2042 #define IXGBE_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000
2043 #define IXGBE_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000
2044 #define IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED    0x18000000
2045 #define IXGBE_RXDADV_IPSEC_ERROR_BIT_MASK       0x18000000
2046 /* Multiple Transmit Queue Command Register */
2047 #define IXGBE_MTQC_RT_ENA       0x1 /* DCB Enable */
2048 #define IXGBE_MTQC_VT_ENA       0x2 /* VMDQ2 Enable */
2049 #define IXGBE_MTQC_64Q_1PB      0x0 /* 64 queues 1 pack buffer */
2050 #define IXGBE_MTQC_32VF         0x8 /* 4 TX Queues per pool w/32VF's */
2051 #define IXGBE_MTQC_64VF         0x4 /* 2 TX Queues per pool w/64VF's */
2052 #define IXGBE_MTQC_4TC_4TQ      0x8 /* 4 TC if RT_ENA and VT_ENA */
2053 #define IXGBE_MTQC_8TC_8TQ      0xC /* 8 TC if RT_ENA or 8 TQ if VT_ENA */
2054
2055 /* Receive Descriptor bit definitions */
2056 #define IXGBE_RXD_STAT_DD       0x01 /* Descriptor Done */
2057 #define IXGBE_RXD_STAT_EOP      0x02 /* End of Packet */
2058 #define IXGBE_RXD_STAT_FLM      0x04 /* FDir Match */
2059 #define IXGBE_RXD_STAT_VP       0x08 /* IEEE VLAN Packet */
2060 #define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0 /* Next Descriptor Index */
2061 #define IXGBE_RXDADV_NEXTP_SHIFT        0x00000004
2062 #define IXGBE_RXD_STAT_UDPCS    0x10 /* UDP xsum calculated */
2063 #define IXGBE_RXD_STAT_L4CS     0x20 /* L4 xsum calculated */
2064 #define IXGBE_RXD_STAT_IPCS     0x40 /* IP xsum calculated */
2065 #define IXGBE_RXD_STAT_PIF      0x80 /* passed in-exact filter */
2066 #define IXGBE_RXD_STAT_CRCV     0x100 /* Speculative CRC Valid */
2067 #define IXGBE_RXD_STAT_VEXT     0x200 /* 1st VLAN found */
2068 #define IXGBE_RXD_STAT_UDPV     0x400 /* Valid UDP checksum */
2069 #define IXGBE_RXD_STAT_DYNINT   0x800 /* Pkt caused INT via DYNINT */
2070 #define IXGBE_RXD_STAT_LLINT    0x800 /* Pkt caused Low Latency Interrupt */
2071 #define IXGBE_RXD_STAT_TS       0x10000 /* Time Stamp */
2072 #define IXGBE_RXD_STAT_SECP     0x20000 /* Security Processing */
2073 #define IXGBE_RXD_STAT_LB       0x40000 /* Loopback Status */
2074 #define IXGBE_RXD_STAT_ACK      0x8000 /* ACK Packet indication */
2075 #define IXGBE_RXD_ERR_CE        0x01 /* CRC Error */
2076 #define IXGBE_RXD_ERR_LE        0x02 /* Length Error */
2077 #define IXGBE_RXD_ERR_PE        0x08 /* Packet Error */
2078 #define IXGBE_RXD_ERR_OSE       0x10 /* Oversize Error */
2079 #define IXGBE_RXD_ERR_USE       0x20 /* Undersize Error */
2080 #define IXGBE_RXD_ERR_TCPE      0x40 /* TCP/UDP Checksum Error */
2081 #define IXGBE_RXD_ERR_IPE       0x80 /* IP Checksum Error */
2082 #define IXGBE_RXDADV_ERR_MASK           0xfff00000 /* RDESC.ERRORS mask */
2083 #define IXGBE_RXDADV_ERR_SHIFT          20 /* RDESC.ERRORS shift */
2084 #define IXGBE_RXDADV_ERR_RXE            0x20000000 /* Any MAC Error */
2085 #define IXGBE_RXDADV_ERR_FCEOFE         0x80000000 /* FCoEFe/IPE */
2086 #define IXGBE_RXDADV_ERR_FCERR          0x00700000 /* FCERR/FDIRERR */
2087 #define IXGBE_RXDADV_ERR_FDIR_LEN       0x00100000 /* FDIR Length error */
2088 #define IXGBE_RXDADV_ERR_FDIR_DROP      0x00200000 /* FDIR Drop error */
2089 #define IXGBE_RXDADV_ERR_FDIR_COLL      0x00400000 /* FDIR Collision error */
2090 #define IXGBE_RXDADV_ERR_HBO    0x00800000 /*Header Buffer Overflow */
2091 #define IXGBE_RXDADV_ERR_CE     0x01000000 /* CRC Error */
2092 #define IXGBE_RXDADV_ERR_LE     0x02000000 /* Length Error */
2093 #define IXGBE_RXDADV_ERR_PE     0x08000000 /* Packet Error */
2094 #define IXGBE_RXDADV_ERR_OSE    0x10000000 /* Oversize Error */
2095 #define IXGBE_RXDADV_ERR_USE    0x20000000 /* Undersize Error */
2096 #define IXGBE_RXDADV_ERR_TCPE   0x40000000 /* TCP/UDP Checksum Error */
2097 #define IXGBE_RXDADV_ERR_IPE    0x80000000 /* IP Checksum Error */
2098 #define IXGBE_RXD_VLAN_ID_MASK  0x0FFF  /* VLAN ID is in lower 12 bits */
2099 #define IXGBE_RXD_PRI_MASK      0xE000  /* Priority is in upper 3 bits */
2100 #define IXGBE_RXD_PRI_SHIFT     13
2101 #define IXGBE_RXD_CFI_MASK      0x1000  /* CFI is bit 12 */
2102 #define IXGBE_RXD_CFI_SHIFT     12
2103
2104 #define IXGBE_RXDADV_STAT_DD            IXGBE_RXD_STAT_DD  /* Done */
2105 #define IXGBE_RXDADV_STAT_EOP           IXGBE_RXD_STAT_EOP /* End of Packet */
2106 #define IXGBE_RXDADV_STAT_FLM           IXGBE_RXD_STAT_FLM /* FDir Match */
2107 #define IXGBE_RXDADV_STAT_VP            IXGBE_RXD_STAT_VP  /* IEEE VLAN Pkt */
2108 #define IXGBE_RXDADV_STAT_MASK          0x000fffff /* Stat/NEXTP: bit 0-19 */
2109 #define IXGBE_RXDADV_STAT_FCEOFS        0x00000040 /* FCoE EOF/SOF Stat */
2110 #define IXGBE_RXDADV_STAT_FCSTAT        0x00000030 /* FCoE Pkt Stat */
2111 #define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */
2112 #define IXGBE_RXDADV_STAT_FCSTAT_NODDP  0x00000010 /* 01: Ctxt w/o DDP */
2113 #define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */
2114 #define IXGBE_RXDADV_STAT_FCSTAT_DDP    0x00000030 /* 11: Ctxt w/ DDP */
2115 #define IXGBE_RXDADV_STAT_TS            0x00010000 /* IEEE1588 Time Stamp */
2116
2117 /* PSRTYPE bit definitions */
2118 #define IXGBE_PSRTYPE_TCPHDR    0x00000010
2119 #define IXGBE_PSRTYPE_UDPHDR    0x00000020
2120 #define IXGBE_PSRTYPE_IPV4HDR   0x00000100
2121 #define IXGBE_PSRTYPE_IPV6HDR   0x00000200
2122 #define IXGBE_PSRTYPE_L2HDR     0x00001000
2123
2124 /* SRRCTL bit definitions */
2125 #define IXGBE_SRRCTL_BSIZEPKT_SHIFT     10 /* so many KBs */
2126 #define IXGBE_SRRCTL_RDMTS_SHIFT        22
2127 #define IXGBE_SRRCTL_RDMTS_MASK         0x01C00000
2128 #define IXGBE_SRRCTL_DROP_EN            0x10000000
2129 #define IXGBE_SRRCTL_BSIZEPKT_MASK      0x0000007F
2130 #define IXGBE_SRRCTL_BSIZEHDR_MASK      0x00003F00
2131 #define IXGBE_SRRCTL_DESCTYPE_LEGACY    0x00000000
2132 #define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
2133 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
2134 #define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
2135 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
2136 #define IXGBE_SRRCTL_DESCTYPE_MASK      0x0E000000
2137
2138 #define IXGBE_RXDPS_HDRSTAT_HDRSP       0x00008000
2139 #define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
2140
2141 #define IXGBE_RXDADV_RSSTYPE_MASK       0x0000000F
2142 #define IXGBE_RXDADV_PKTTYPE_MASK       0x0000FFF0
2143 #define IXGBE_RXDADV_PKTTYPE_MASK_EX    0x0001FFF0
2144 #define IXGBE_RXDADV_HDRBUFLEN_MASK     0x00007FE0
2145 #define IXGBE_RXDADV_RSCCNT_MASK        0x001E0000
2146 #define IXGBE_RXDADV_RSCCNT_SHIFT       17
2147 #define IXGBE_RXDADV_HDRBUFLEN_SHIFT    5
2148 #define IXGBE_RXDADV_SPLITHEADER_EN     0x00001000
2149 #define IXGBE_RXDADV_SPH                0x8000
2150
2151 /* RSS Hash results */
2152 #define IXGBE_RXDADV_RSSTYPE_NONE       0x00000000
2153 #define IXGBE_RXDADV_RSSTYPE_IPV4_TCP   0x00000001
2154 #define IXGBE_RXDADV_RSSTYPE_IPV4       0x00000002
2155 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP   0x00000003
2156 #define IXGBE_RXDADV_RSSTYPE_IPV6_EX    0x00000004
2157 #define IXGBE_RXDADV_RSSTYPE_IPV6       0x00000005
2158 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
2159 #define IXGBE_RXDADV_RSSTYPE_IPV4_UDP   0x00000007
2160 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP   0x00000008
2161 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
2162
2163 /* RSS Packet Types as indicated in the receive descriptor. */
2164 #define IXGBE_RXDADV_PKTTYPE_NONE       0x00000000
2165 #define IXGBE_RXDADV_PKTTYPE_IPV4       0x00000010 /* IPv4 hdr present */
2166 #define IXGBE_RXDADV_PKTTYPE_IPV4_EX    0x00000020 /* IPv4 hdr + extensions */
2167 #define IXGBE_RXDADV_PKTTYPE_IPV6       0x00000040 /* IPv6 hdr present */
2168 #define IXGBE_RXDADV_PKTTYPE_IPV6_EX    0x00000080 /* IPv6 hdr + extensions */
2169 #define IXGBE_RXDADV_PKTTYPE_TCP        0x00000100 /* TCP hdr present */
2170 #define IXGBE_RXDADV_PKTTYPE_UDP        0x00000200 /* UDP hdr present */
2171 #define IXGBE_RXDADV_PKTTYPE_SCTP       0x00000400 /* SCTP hdr present */
2172 #define IXGBE_RXDADV_PKTTYPE_NFS        0x00000800 /* NFS hdr present */
2173 #define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP  0x00001000 /* IPSec ESP */
2174 #define IXGBE_RXDADV_PKTTYPE_IPSEC_AH   0x00002000 /* IPSec AH */
2175 #define IXGBE_RXDADV_PKTTYPE_LINKSEC    0x00004000 /* LinkSec Encap */
2176 #define IXGBE_RXDADV_PKTTYPE_ETQF       0x00008000 /* PKTTYPE is ETQF index */
2177 #define IXGBE_RXDADV_PKTTYPE_ETQF_MASK  0x00000070 /* ETQF has 8 indices */
2178 #define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */
2179
2180 /* Security Processing bit Indication */
2181 #define IXGBE_RXDADV_LNKSEC_STATUS_SECP         0x00020000
2182 #define IXGBE_RXDADV_LNKSEC_ERROR_NO_SA_MATCH   0x08000000
2183 #define IXGBE_RXDADV_LNKSEC_ERROR_REPLAY_ERROR  0x10000000
2184 #define IXGBE_RXDADV_LNKSEC_ERROR_BIT_MASK      0x18000000
2185 #define IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG       0x18000000
2186
2187 /* Masks to determine if packets should be dropped due to frame errors */
2188 #define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \
2189                                 IXGBE_RXD_ERR_CE | \
2190                                 IXGBE_RXD_ERR_LE | \
2191                                 IXGBE_RXD_ERR_PE | \
2192                                 IXGBE_RXD_ERR_OSE | \
2193                                 IXGBE_RXD_ERR_USE)
2194
2195 #define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \
2196                                 IXGBE_RXDADV_ERR_CE | \
2197                                 IXGBE_RXDADV_ERR_LE | \
2198                                 IXGBE_RXDADV_ERR_PE | \
2199                                 IXGBE_RXDADV_ERR_OSE | \
2200                                 IXGBE_RXDADV_ERR_USE)
2201
2202 #define IXGBE_RXDADV_ERR_FRAME_ERR_MASK_82599   IXGBE_RXDADV_ERR_RXE
2203
2204 /* Multicast bit mask */
2205 #define IXGBE_MCSTCTRL_MFE      0x4
2206
2207 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
2208 #define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE        8
2209 #define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE        8
2210 #define IXGBE_REQ_TX_BUFFER_GRANULARITY         1024
2211
2212 /* Vlan-specific macros */
2213 #define IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID in lower 12 bits */
2214 #define IXGBE_RX_DESC_SPECIAL_PRI_MASK  0xE000 /* Priority in upper 3 bits */
2215 #define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */
2216 #define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT
2217
2218 /* SR-IOV specific macros */
2219 #define IXGBE_MBVFICR_INDEX(vf_number)  (vf_number >> 4)
2220 #define IXGBE_MBVFICR(_i)               (0x00710 + ((_i) * 4))
2221 #define IXGBE_VFLRE(_i)                 (((_i & 1) ? 0x001C0 : 0x00600))
2222 #define IXGBE_VFLREC(_i)                 (0x00700 + ((_i) * 4))
2223 /* Translated register #defines */
2224 #define IXGBE_PVFCTRL(P)        (0x00300 + (4 * (P)))
2225 #define IXGBE_PVFSTATUS(P)      (0x00008 + (0 * (P)))
2226 #define IXGBE_PVFLINKS(P)       (0x042A4 + (0 * (P)))
2227 #define IXGBE_PVFRTIMER(P)      (0x00048 + (0 * (P)))
2228 #define IXGBE_PVFMAILBOX(P)     (0x04C00 + (4 * (P)))
2229 #define IXGBE_PVFRXMEMWRAP(P)   (0x03190 + (0 * (P)))
2230 #define IXGBE_PVTEICR(P)        (0x00B00 + (4 * (P)))
2231 #define IXGBE_PVTEICS(P)        (0x00C00 + (4 * (P)))
2232 #define IXGBE_PVTEIMS(P)        (0x00D00 + (4 * (P)))
2233 #define IXGBE_PVTEIMC(P)        (0x00E00 + (4 * (P)))
2234 #define IXGBE_PVTEIAC(P)        (0x00F00 + (4 * (P)))
2235 #define IXGBE_PVTEIAM(P)        (0x04D00 + (4 * (P)))
2236 #define IXGBE_PVTEITR(P)        (((P) < 24) ? (0x00820 + ((P) * 4)) : \
2237                                  (0x012300 + (((P) - 24) * 4)))
2238 #define IXGBE_PVTIVAR(P)        (0x12500 + (4 * (P)))
2239 #define IXGBE_PVTIVAR_MISC(P)   (0x04E00 + (4 * (P)))
2240 #define IXGBE_PVTRSCINT(P)      (0x12000 + (4 * (P)))
2241 #define IXGBE_VFPBACL(P)        (0x110C8 + (4 * (P)))
2242 #define IXGBE_PVFRDBAL(P)       ((P < 64) ? (0x01000 + (0x40 * (P))) \
2243                                  : (0x0D000 + (0x40 * ((P) - 64))))
2244 #define IXGBE_PVFRDBAH(P)       ((P < 64) ? (0x01004 + (0x40 * (P))) \
2245                                  : (0x0D004 + (0x40 * ((P) - 64))))
2246 #define IXGBE_PVFRDLEN(P)       ((P < 64) ? (0x01008 + (0x40 * (P))) \
2247                                  : (0x0D008 + (0x40 * ((P) - 64))))
2248 #define IXGBE_PVFRDH(P)         ((P < 64) ? (0x01010 + (0x40 * (P))) \
2249                                  : (0x0D010 + (0x40 * ((P) - 64))))
2250 #define IXGBE_PVFRDT(P)         ((P < 64) ? (0x01018 + (0x40 * (P))) \
2251                                  : (0x0D018 + (0x40 * ((P) - 64))))
2252 #define IXGBE_PVFRXDCTL(P)      ((P < 64) ? (0x01028 + (0x40 * (P))) \
2253                                  : (0x0D028 + (0x40 * ((P) - 64))))
2254 #define IXGBE_PVFSRRCTL(P)      ((P < 64) ? (0x01014 + (0x40 * (P))) \
2255                                  : (0x0D014 + (0x40 * ((P) - 64))))
2256 #define IXGBE_PVFPSRTYPE(P)     (0x0EA00 + (4 * (P)))
2257 #define IXGBE_PVFTDBAL(P)       (0x06000 + (0x40 * (P)))
2258 #define IXGBE_PVFTDBAH(P)       (0x06004 + (0x40 * (P)))
2259 #define IXGBE_PVFTTDLEN(P)      (0x06008 + (0x40 * (P)))
2260 #define IXGBE_PVFTDH(P)         (0x06010 + (0x40 * (P)))
2261 #define IXGBE_PVFTDT(P)         (0x06018 + (0x40 * (P)))
2262 #define IXGBE_PVFTXDCTL(P)      (0x06028 + (0x40 * (P)))
2263 #define IXGBE_PVFTDWBAL(P)      (0x06038 + (0x40 * (P)))
2264 #define IXGBE_PVFTDWBAH(P)      (0x0603C + (0x40 * (P)))
2265 #define IXGBE_PVFDCA_RXCTRL(P)  (((P) < 64) ? (0x0100C + (0x40 * (P))) \
2266                                  : (0x0D00C + (0x40 * ((P) - 64))))
2267 #define IXGBE_PVFDCA_TXCTRL(P)  (0x0600C + (0x40 * (P)))
2268 #define IXGBE_PVFGPRC(x)        (0x0101C + (0x40 * (x)))
2269 #define IXGBE_PVFGPTC(x)        (0x08300 + (0x04 * (x)))
2270 #define IXGBE_PVFGORC_LSB(x)    (0x01020 + (0x40 * (x)))
2271 #define IXGBE_PVFGORC_MSB(x)    (0x0D020 + (0x40 * (x)))
2272 #define IXGBE_PVFGOTC_LSB(x)    (0x08400 + (0x08 * (x)))
2273 #define IXGBE_PVFGOTC_MSB(x)    (0x08404 + (0x08 * (x)))
2274 #define IXGBE_PVFMPRC(x)        (0x0D01C + (0x40 * (x)))
2275
2276 #define IXGBE_PVFTDWBALn(q_per_pool, vf_number, vf_q_index) \
2277                 (IXGBE_PVFTDWBAL((q_per_pool)*(vf_number) + (vf_q_index)))
2278 #define IXGBE_PVFTDWBAHn(q_per_pool, vf_number, vf_q_index) \
2279                 (IXGBE_PVFTDWBAH((q_per_pool)*(vf_number) + (vf_q_index)))
2280
2281 /* Little Endian defines */
2282 #ifndef __le16
2283 #define __le16  u16
2284 #endif
2285 #ifndef __le32
2286 #define __le32  u32
2287 #endif
2288 #ifndef __le64
2289 #define __le64  u64
2290
2291 #endif
2292 #ifndef __be16
2293 /* Big Endian defines */
2294 #define __be16  u16
2295 #define __be32  u32
2296 #define __be64  u64
2297
2298 #endif
2299 enum ixgbe_fdir_pballoc_type {
2300         IXGBE_FDIR_PBALLOC_NONE = 0,
2301         IXGBE_FDIR_PBALLOC_64K  = 1,
2302         IXGBE_FDIR_PBALLOC_128K = 2,
2303         IXGBE_FDIR_PBALLOC_256K = 3,
2304 };
2305
2306 /* Flow Director register values */
2307 #define IXGBE_FDIRCTRL_PBALLOC_64K              0x00000001
2308 #define IXGBE_FDIRCTRL_PBALLOC_128K             0x00000002
2309 #define IXGBE_FDIRCTRL_PBALLOC_256K             0x00000003
2310 #define IXGBE_FDIRCTRL_INIT_DONE                0x00000008
2311 #define IXGBE_FDIRCTRL_PERFECT_MATCH            0x00000010
2312 #define IXGBE_FDIRCTRL_REPORT_STATUS            0x00000020
2313 #define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS     0x00000080
2314 #define IXGBE_FDIRCTRL_DROP_Q_SHIFT             8
2315 #define IXGBE_FDIRCTRL_FLEX_SHIFT               16
2316 #define IXGBE_FDIRCTRL_SEARCHLIM                0x00800000
2317 #define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT         24
2318 #define IXGBE_FDIRCTRL_FULL_THRESH_MASK         0xF0000000
2319 #define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT        28
2320
2321 #define IXGBE_FDIRTCPM_DPORTM_SHIFT             16
2322 #define IXGBE_FDIRUDPM_DPORTM_SHIFT             16
2323 #define IXGBE_FDIRIP6M_DIPM_SHIFT               16
2324 #define IXGBE_FDIRM_VLANID                      0x00000001
2325 #define IXGBE_FDIRM_VLANP                       0x00000002
2326 #define IXGBE_FDIRM_POOL                        0x00000004
2327 #define IXGBE_FDIRM_L4P                         0x00000008
2328 #define IXGBE_FDIRM_FLEX                        0x00000010
2329 #define IXGBE_FDIRM_DIPv6                       0x00000020
2330
2331 #define IXGBE_FDIRFREE_FREE_MASK                0xFFFF
2332 #define IXGBE_FDIRFREE_FREE_SHIFT               0
2333 #define IXGBE_FDIRFREE_COLL_MASK                0x7FFF0000
2334 #define IXGBE_FDIRFREE_COLL_SHIFT               16
2335 #define IXGBE_FDIRLEN_MAXLEN_MASK               0x3F
2336 #define IXGBE_FDIRLEN_MAXLEN_SHIFT              0
2337 #define IXGBE_FDIRLEN_MAXHASH_MASK              0x7FFF0000
2338 #define IXGBE_FDIRLEN_MAXHASH_SHIFT             16
2339 #define IXGBE_FDIRUSTAT_ADD_MASK                0xFFFF
2340 #define IXGBE_FDIRUSTAT_ADD_SHIFT               0
2341 #define IXGBE_FDIRUSTAT_REMOVE_MASK             0xFFFF0000
2342 #define IXGBE_FDIRUSTAT_REMOVE_SHIFT            16
2343 #define IXGBE_FDIRFSTAT_FADD_MASK               0x00FF
2344 #define IXGBE_FDIRFSTAT_FADD_SHIFT              0
2345 #define IXGBE_FDIRFSTAT_FREMOVE_MASK            0xFF00
2346 #define IXGBE_FDIRFSTAT_FREMOVE_SHIFT           8
2347 #define IXGBE_FDIRPORT_DESTINATION_SHIFT        16
2348 #define IXGBE_FDIRVLAN_FLEX_SHIFT               16
2349 #define IXGBE_FDIRHASH_BUCKET_VALID_SHIFT       15
2350 #define IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT       16
2351
2352 #define IXGBE_FDIRCMD_CMD_MASK                  0x00000003
2353 #define IXGBE_FDIRCMD_CMD_ADD_FLOW              0x00000001
2354 #define IXGBE_FDIRCMD_CMD_REMOVE_FLOW           0x00000002
2355 #define IXGBE_FDIRCMD_CMD_QUERY_REM_FILT        0x00000003
2356 #define IXGBE_FDIRCMD_FILTER_VALID              0x00000004
2357 #define IXGBE_FDIRCMD_FILTER_UPDATE             0x00000008
2358 #define IXGBE_FDIRCMD_IPv6DMATCH                0x00000010
2359 #define IXGBE_FDIRCMD_L4TYPE_UDP                0x00000020
2360 #define IXGBE_FDIRCMD_L4TYPE_TCP                0x00000040
2361 #define IXGBE_FDIRCMD_L4TYPE_SCTP               0x00000060
2362 #define IXGBE_FDIRCMD_IPV6                      0x00000080
2363 #define IXGBE_FDIRCMD_CLEARHT                   0x00000100
2364 #define IXGBE_FDIRCMD_DROP                      0x00000200
2365 #define IXGBE_FDIRCMD_INT                       0x00000400
2366 #define IXGBE_FDIRCMD_LAST                      0x00000800
2367 #define IXGBE_FDIRCMD_COLLISION                 0x00001000
2368 #define IXGBE_FDIRCMD_QUEUE_EN                  0x00008000
2369 #define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT           5
2370 #define IXGBE_FDIRCMD_RX_QUEUE_SHIFT            16
2371 #define IXGBE_FDIRCMD_VT_POOL_SHIFT             24
2372 #define IXGBE_FDIR_INIT_DONE_POLL               10
2373 #define IXGBE_FDIRCMD_CMD_POLL                  10
2374
2375 #define IXGBE_FDIR_DROP_QUEUE                   127
2376
2377 #define IXGBE_STATUS_OVERHEATING_BIT            20 /* STATUS overtemp bit num */
2378
2379 /* Manageablility Host Interface defines */
2380 #define IXGBE_HI_MAX_BLOCK_BYTE_LENGTH  1792 /* Num of bytes in range */
2381 #define IXGBE_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Num of dwords in range */
2382 #define IXGBE_HI_COMMAND_TIMEOUT        500 /* Process HI command limit */
2383
2384 /* CEM Support */
2385 #define FW_CEM_HDR_LEN                  0x4
2386 #define FW_CEM_CMD_DRIVER_INFO          0xDD
2387 #define FW_CEM_CMD_DRIVER_INFO_LEN      0x5
2388 #define FW_CEM_CMD_RESERVED             0X0
2389 #define FW_CEM_UNUSED_VER               0x0
2390 #define FW_CEM_MAX_RETRIES              3
2391 #define FW_CEM_RESP_STATUS_SUCCESS      0x1
2392
2393 /* Host Interface Command Structures */
2394
2395 struct ixgbe_hic_hdr {
2396         u8 cmd;
2397         u8 buf_len;
2398         union {
2399                 u8 cmd_resv;
2400                 u8 ret_status;
2401         } cmd_or_resp;
2402         u8 checksum;
2403 };
2404
2405 struct ixgbe_hic_drv_info {
2406         struct ixgbe_hic_hdr hdr;
2407         u8 port_num;
2408         u8 ver_sub;
2409         u8 ver_build;
2410         u8 ver_min;
2411         u8 ver_maj;
2412         u8 pad; /* end spacing to ensure length is mult. of dword */
2413         u16 pad2; /* end spacing to ensure length is mult. of dword2 */
2414 };
2415
2416 /* Transmit Descriptor - Legacy */
2417 struct ixgbe_legacy_tx_desc {
2418         u64 buffer_addr; /* Address of the descriptor's data buffer */
2419         union {
2420                 __le32 data;
2421                 struct {
2422                         __le16 length; /* Data buffer length */
2423                         u8 cso; /* Checksum offset */
2424                         u8 cmd; /* Descriptor control */
2425                 } flags;
2426         } lower;
2427         union {
2428                 __le32 data;
2429                 struct {
2430                         u8 status; /* Descriptor status */
2431                         u8 css; /* Checksum start */
2432                         __le16 vlan;
2433                 } fields;
2434         } upper;
2435 };
2436
2437 /* Transmit Descriptor - Advanced */
2438 union ixgbe_adv_tx_desc {
2439         struct {
2440                 __le64 buffer_addr; /* Address of descriptor's data buf */
2441                 __le32 cmd_type_len;
2442                 __le32 olinfo_status;
2443         } read;
2444         struct {
2445                 __le64 rsvd; /* Reserved */
2446                 __le32 nxtseq_seed;
2447                 __le32 status;
2448         } wb;
2449 };
2450
2451 /* Receive Descriptor - Legacy */
2452 struct ixgbe_legacy_rx_desc {
2453         __le64 buffer_addr; /* Address of the descriptor's data buffer */
2454         __le16 length; /* Length of data DMAed into data buffer */
2455         __le16 csum; /* Packet checksum */
2456         u8 status;   /* Descriptor status */
2457         u8 errors;   /* Descriptor Errors */
2458         __le16 vlan;
2459 };
2460
2461 /* Receive Descriptor - Advanced */
2462 union ixgbe_adv_rx_desc {
2463         struct {
2464                 __le64 pkt_addr; /* Packet buffer address */
2465                 __le64 hdr_addr; /* Header buffer address */
2466         } read;
2467         struct {
2468                 struct {
2469                         union {
2470                                 __le32 data;
2471                                 struct {
2472                                         __le16 pkt_info; /* RSS, Pkt type */
2473                                         __le16 hdr_info; /* Splithdr, hdrlen */
2474                                 } hs_rss;
2475                         } lo_dword;
2476                         union {
2477                                 __le32 rss; /* RSS Hash */
2478                                 struct {
2479                                         __le16 ip_id; /* IP id */
2480                                         __le16 csum; /* Packet Checksum */
2481                                 } csum_ip;
2482                         } hi_dword;
2483                 } lower;
2484                 struct {
2485                         __le32 status_error; /* ext status/error */
2486                         __le16 length; /* Packet length */
2487                         __le16 vlan; /* VLAN tag */
2488                 } upper;
2489         } wb;  /* writeback */
2490 };
2491
2492 /* Context descriptors */
2493 struct ixgbe_adv_tx_context_desc {
2494         __le32 vlan_macip_lens;
2495         __le32 seqnum_seed;
2496         __le32 type_tucmd_mlhl;
2497         __le32 mss_l4len_idx;
2498 };
2499
2500 /* Adv Transmit Descriptor Config Masks */
2501 #define IXGBE_ADVTXD_DTALEN_MASK        0x0000FFFF /* Data buf length(bytes) */
2502 #define IXGBE_ADVTXD_MAC_LINKSEC        0x00040000 /* Insert LinkSec */
2503 #define IXGBE_ADVTXD_MAC_TSTAMP         0x00080000 /* IEEE1588 time stamp */
2504 #define IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK 0x000003FF /* IPSec SA index */
2505 #define IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK 0x000001FF /* IPSec ESP length */
2506 #define IXGBE_ADVTXD_DTYP_MASK          0x00F00000 /* DTYP mask */
2507 #define IXGBE_ADVTXD_DTYP_CTXT          0x00200000 /* Adv Context Desc */
2508 #define IXGBE_ADVTXD_DTYP_DATA          0x00300000 /* Adv Data Descriptor */
2509 #define IXGBE_ADVTXD_DCMD_EOP           IXGBE_TXD_CMD_EOP  /* End of Packet */
2510 #define IXGBE_ADVTXD_DCMD_IFCS          IXGBE_TXD_CMD_IFCS /* Insert FCS */
2511 #define IXGBE_ADVTXD_DCMD_RS            IXGBE_TXD_CMD_RS /* Report Status */
2512 #define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI   0x10000000 /* DDP hdr type or iSCSI */
2513 #define IXGBE_ADVTXD_DCMD_DEXT          IXGBE_TXD_CMD_DEXT /* Desc ext 1=Adv */
2514 #define IXGBE_ADVTXD_DCMD_VLE           IXGBE_TXD_CMD_VLE  /* VLAN pkt enable */
2515 #define IXGBE_ADVTXD_DCMD_TSE           0x80000000 /* TCP Seg enable */
2516 #define IXGBE_ADVTXD_STAT_DD            IXGBE_TXD_STAT_DD  /* Descriptor Done */
2517 #define IXGBE_ADVTXD_STAT_SN_CRC        0x00000002 /* NXTSEQ/SEED pres in WB */
2518 #define IXGBE_ADVTXD_STAT_RSV           0x0000000C /* STA Reserved */
2519 #define IXGBE_ADVTXD_IDX_SHIFT          4 /* Adv desc Index shift */
2520 #define IXGBE_ADVTXD_CC                 0x00000080 /* Check Context */
2521 #define IXGBE_ADVTXD_POPTS_SHIFT        8  /* Adv desc POPTS shift */
2522 #define IXGBE_ADVTXD_POPTS_IXSM         (IXGBE_TXD_POPTS_IXSM << \
2523                                          IXGBE_ADVTXD_POPTS_SHIFT)
2524 #define IXGBE_ADVTXD_POPTS_TXSM         (IXGBE_TXD_POPTS_TXSM << \
2525                                          IXGBE_ADVTXD_POPTS_SHIFT)
2526 #define IXGBE_ADVTXD_POPTS_ISCO_1ST     0x00000000 /* 1st TSO of iSCSI PDU */
2527 #define IXGBE_ADVTXD_POPTS_ISCO_MDL     0x00000800 /* Middle TSO of iSCSI PDU */
2528 #define IXGBE_ADVTXD_POPTS_ISCO_LAST    0x00001000 /* Last TSO of iSCSI PDU */
2529 /* 1st&Last TSO-full iSCSI PDU */
2530 #define IXGBE_ADVTXD_POPTS_ISCO_FULL    0x00001800
2531 #define IXGBE_ADVTXD_POPTS_RSV          0x00002000 /* POPTS Reserved */
2532 #define IXGBE_ADVTXD_PAYLEN_SHIFT       14 /* Adv desc PAYLEN shift */
2533 #define IXGBE_ADVTXD_MACLEN_SHIFT       9  /* Adv ctxt desc mac len shift */
2534 #define IXGBE_ADVTXD_VLAN_SHIFT         16  /* Adv ctxt vlan tag shift */
2535 #define IXGBE_ADVTXD_TUCMD_IPV4         0x00000400 /* IP Packet Type: 1=IPv4 */
2536 #define IXGBE_ADVTXD_TUCMD_IPV6         0x00000000 /* IP Packet Type: 0=IPv6 */
2537 #define IXGBE_ADVTXD_TUCMD_L4T_UDP      0x00000000 /* L4 Packet TYPE of UDP */
2538 #define IXGBE_ADVTXD_TUCMD_L4T_TCP      0x00000800 /* L4 Packet TYPE of TCP */
2539 #define IXGBE_ADVTXD_TUCMD_L4T_SCTP     0x00001000 /* L4 Packet TYPE of SCTP */
2540 #define IXGBE_ADVTXD_TUCMD_MKRREQ       0x00002000 /* req Markers and CRC */
2541 #define IXGBE_ADVTXD_POPTS_IPSEC        0x00000400 /* IPSec offload request */
2542 #define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */
2543 #define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */
2544 #define IXGBE_ADVTXT_TUCMD_FCOE         0x00008000 /* FCoE Frame Type */
2545 #define IXGBE_ADVTXD_FCOEF_EOF_MASK     (0x3 << 10) /* FC EOF index */
2546 #define IXGBE_ADVTXD_FCOEF_SOF          ((1 << 2) << 10) /* FC SOF index */
2547 #define IXGBE_ADVTXD_FCOEF_PARINC       ((1 << 3) << 10) /* Rel_Off in F_CTL */
2548 #define IXGBE_ADVTXD_FCOEF_ORIE         ((1 << 4) << 10) /* Orientation End */
2549 #define IXGBE_ADVTXD_FCOEF_ORIS         ((1 << 5) << 10) /* Orientation Start */
2550 #define IXGBE_ADVTXD_FCOEF_EOF_N        (0x0 << 10) /* 00: EOFn */
2551 #define IXGBE_ADVTXD_FCOEF_EOF_T        (0x1 << 10) /* 01: EOFt */
2552 #define IXGBE_ADVTXD_FCOEF_EOF_NI       (0x2 << 10) /* 10: EOFni */
2553 #define IXGBE_ADVTXD_FCOEF_EOF_A        (0x3 << 10) /* 11: EOFa */
2554 #define IXGBE_ADVTXD_L4LEN_SHIFT        8  /* Adv ctxt L4LEN shift */
2555 #define IXGBE_ADVTXD_MSS_SHIFT          16  /* Adv ctxt MSS shift */
2556
2557 /* Autonegotiation advertised speeds */
2558 typedef u32 ixgbe_autoneg_advertised;
2559 /* Link speed */
2560 typedef u32 ixgbe_link_speed;
2561 #define IXGBE_LINK_SPEED_UNKNOWN        0
2562 #define IXGBE_LINK_SPEED_100_FULL       0x0008
2563 #define IXGBE_LINK_SPEED_1GB_FULL       0x0020
2564 #define IXGBE_LINK_SPEED_10GB_FULL      0x0080
2565 #define IXGBE_LINK_SPEED_82598_AUTONEG  (IXGBE_LINK_SPEED_1GB_FULL | \
2566                                          IXGBE_LINK_SPEED_10GB_FULL)
2567 #define IXGBE_LINK_SPEED_82599_AUTONEG  (IXGBE_LINK_SPEED_100_FULL | \
2568                                          IXGBE_LINK_SPEED_1GB_FULL | \
2569                                          IXGBE_LINK_SPEED_10GB_FULL)
2570
2571
2572 /* Physical layer type */
2573 typedef u32 ixgbe_physical_layer;
2574 #define IXGBE_PHYSICAL_LAYER_UNKNOWN            0
2575 #define IXGBE_PHYSICAL_LAYER_10GBASE_T          0x0001
2576 #define IXGBE_PHYSICAL_LAYER_1000BASE_T         0x0002
2577 #define IXGBE_PHYSICAL_LAYER_100BASE_TX         0x0004
2578 #define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU        0x0008
2579 #define IXGBE_PHYSICAL_LAYER_10GBASE_LR         0x0010
2580 #define IXGBE_PHYSICAL_LAYER_10GBASE_LRM        0x0020
2581 #define IXGBE_PHYSICAL_LAYER_10GBASE_SR         0x0040
2582 #define IXGBE_PHYSICAL_LAYER_10GBASE_KX4        0x0080
2583 #define IXGBE_PHYSICAL_LAYER_10GBASE_CX4        0x0100
2584 #define IXGBE_PHYSICAL_LAYER_1000BASE_KX        0x0200
2585 #define IXGBE_PHYSICAL_LAYER_1000BASE_BX        0x0400
2586 #define IXGBE_PHYSICAL_LAYER_10GBASE_KR         0x0800
2587 #define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI       0x1000
2588 #define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA      0x2000
2589 #define IXGBE_PHYSICAL_LAYER_1000BASE_SX        0x4000
2590
2591 /* Flow Control Data Sheet defined values
2592  * Calculation and defines taken from 802.1bb Annex O
2593  */
2594
2595 /* BitTimes (BT) conversion */
2596 #define IXGBE_BT2KB(BT)         ((BT + (8 * 1024 - 1)) / (8 * 1024))
2597 #define IXGBE_B2BT(BT)          (BT * 8)
2598
2599 /* Calculate Delay to respond to PFC */
2600 #define IXGBE_PFC_D     672
2601
2602 /* Calculate Cable Delay */
2603 #define IXGBE_CABLE_DC  5556 /* Delay Copper */
2604 #define IXGBE_CABLE_DO  5000 /* Delay Optical */
2605
2606 /* Calculate Interface Delay X540 */
2607 #define IXGBE_PHY_DC    25600 /* Delay 10G BASET */
2608 #define IXGBE_MAC_DC    8192  /* Delay Copper XAUI interface */
2609 #define IXGBE_XAUI_DC   (2 * 2048) /* Delay Copper Phy */
2610
2611 #define IXGBE_ID_X540   (IXGBE_MAC_DC + IXGBE_XAUI_DC + IXGBE_PHY_DC)
2612
2613 /* Calculate Interface Delay 82598, 82599 */
2614 #define IXGBE_PHY_D     12800
2615 #define IXGBE_MAC_D     4096
2616 #define IXGBE_XAUI_D    (2 * 1024)
2617
2618 #define IXGBE_ID        (IXGBE_MAC_D + IXGBE_XAUI_D + IXGBE_PHY_D)
2619
2620 /* Calculate Delay incurred from higher layer */
2621 #define IXGBE_HD        6144
2622
2623 /* Calculate PCI Bus delay for low thresholds */
2624 #define IXGBE_PCI_DELAY 10000
2625
2626 /* Calculate X540 delay value in bit times */
2627 #define IXGBE_DV_X540(_max_frame_link, _max_frame_tc) \
2628                         ((36 * \
2629                           (IXGBE_B2BT(_max_frame_link) + \
2630                            IXGBE_PFC_D + \
2631                            (2 * IXGBE_CABLE_DC) + \
2632                            (2 * IXGBE_ID_X540) + \
2633                            IXGBE_HD) / 25 + 1) + \
2634                          2 * IXGBE_B2BT(_max_frame_tc))
2635
2636 /* Calculate 82599, 82598 delay value in bit times */
2637 #define IXGBE_DV(_max_frame_link, _max_frame_tc) \
2638                         ((36 * \
2639                           (IXGBE_B2BT(_max_frame_link) + \
2640                            IXGBE_PFC_D + \
2641                            (2 * IXGBE_CABLE_DC) + \
2642                            (2 * IXGBE_ID) + \
2643                            IXGBE_HD) / 25 + 1) + \
2644                          2 * IXGBE_B2BT(_max_frame_tc))
2645
2646 /* Calculate low threshold delay values */
2647 #define IXGBE_LOW_DV_X540(_max_frame_tc) \
2648                         (2 * IXGBE_B2BT(_max_frame_tc) + \
2649                         (36 * IXGBE_PCI_DELAY / 25) + 1)
2650 #define IXGBE_LOW_DV(_max_frame_tc) \
2651                         (2 * IXGBE_LOW_DV_X540(_max_frame_tc))
2652
2653 /* Software ATR hash keys */
2654 #define IXGBE_ATR_BUCKET_HASH_KEY       0x3DAD14E2
2655 #define IXGBE_ATR_SIGNATURE_HASH_KEY    0x174D3614
2656
2657 /* Software ATR input stream values and masks */
2658 #define IXGBE_ATR_HASH_MASK             0x7fff
2659 #define IXGBE_ATR_L4TYPE_MASK           0x3
2660 #define IXGBE_ATR_L4TYPE_UDP            0x1
2661 #define IXGBE_ATR_L4TYPE_TCP            0x2
2662 #define IXGBE_ATR_L4TYPE_SCTP           0x3
2663 #define IXGBE_ATR_L4TYPE_IPV6_MASK      0x4
2664 enum ixgbe_atr_flow_type {
2665         IXGBE_ATR_FLOW_TYPE_IPV4        = 0x0,
2666         IXGBE_ATR_FLOW_TYPE_UDPV4       = 0x1,
2667         IXGBE_ATR_FLOW_TYPE_TCPV4       = 0x2,
2668         IXGBE_ATR_FLOW_TYPE_SCTPV4      = 0x3,
2669         IXGBE_ATR_FLOW_TYPE_IPV6        = 0x4,
2670         IXGBE_ATR_FLOW_TYPE_UDPV6       = 0x5,
2671         IXGBE_ATR_FLOW_TYPE_TCPV6       = 0x6,
2672         IXGBE_ATR_FLOW_TYPE_SCTPV6      = 0x7,
2673 };
2674
2675 /* Flow Director ATR input struct. */
2676 union ixgbe_atr_input {
2677         /*
2678          * Byte layout in order, all values with MSB first:
2679          *
2680          * vm_pool      - 1 byte
2681          * flow_type    - 1 byte
2682          * vlan_id      - 2 bytes
2683          * src_ip       - 16 bytes
2684          * dst_ip       - 16 bytes
2685          * src_port     - 2 bytes
2686          * dst_port     - 2 bytes
2687          * flex_bytes   - 2 bytes
2688          * bkt_hash     - 2 bytes
2689          */
2690         struct {
2691                 u8 vm_pool;
2692                 u8 flow_type;
2693                 __be16 vlan_id;
2694                 __be32 dst_ip[4];
2695                 __be32 src_ip[4];
2696                 __be16 src_port;
2697                 __be16 dst_port;
2698                 __be16 flex_bytes;
2699                 __be16 bkt_hash;
2700         } formatted;
2701         __be32 dword_stream[11];
2702 };
2703
2704 /* Flow Director compressed ATR hash input struct */
2705 union ixgbe_atr_hash_dword {
2706         struct {
2707                 u8 vm_pool;
2708                 u8 flow_type;
2709                 __be16 vlan_id;
2710         } formatted;
2711         __be32 ip;
2712         struct {
2713                 __be16 src;
2714                 __be16 dst;
2715         } port;
2716         __be16 flex_bytes;
2717         __be32 dword;
2718 };
2719
2720
2721 /*
2722  * Unavailable: The FCoE Boot Option ROM is not present in the flash.
2723  * Disabled: Present; boot order is not set for any targets on the port.
2724  * Enabled: Present; boot order is set for at least one target on the port.
2725  */
2726 enum ixgbe_fcoe_boot_status {
2727         ixgbe_fcoe_bootstatus_disabled = 0,
2728         ixgbe_fcoe_bootstatus_enabled = 1,
2729         ixgbe_fcoe_bootstatus_unavailable = 0xFFFF
2730 };
2731
2732 enum ixgbe_eeprom_type {
2733         ixgbe_eeprom_uninitialized = 0,
2734         ixgbe_eeprom_spi,
2735         ixgbe_flash,
2736         ixgbe_eeprom_none /* No NVM support */
2737 };
2738
2739 enum ixgbe_mac_type {
2740         ixgbe_mac_unknown = 0,
2741         ixgbe_mac_82598EB,
2742         ixgbe_mac_82599EB,
2743         ixgbe_mac_X540,
2744         ixgbe_num_macs
2745 };
2746
2747 enum ixgbe_phy_type {
2748         ixgbe_phy_unknown = 0,
2749         ixgbe_phy_none,
2750         ixgbe_phy_tn,
2751         ixgbe_phy_aq,
2752         ixgbe_phy_cu_unknown,
2753         ixgbe_phy_qt,
2754         ixgbe_phy_xaui,
2755         ixgbe_phy_nl,
2756         ixgbe_phy_sfp_passive_tyco,
2757         ixgbe_phy_sfp_passive_unknown,
2758         ixgbe_phy_sfp_active_unknown,
2759         ixgbe_phy_sfp_avago,
2760         ixgbe_phy_sfp_ftl,
2761         ixgbe_phy_sfp_ftl_active,
2762         ixgbe_phy_sfp_unknown,
2763         ixgbe_phy_sfp_intel,
2764         ixgbe_phy_sfp_unsupported, /*Enforce bit set with unsupported module*/
2765         ixgbe_phy_generic
2766 };
2767
2768 /*
2769  * SFP+ module type IDs:
2770  *
2771  * ID   Module Type
2772  * =============
2773  * 0    SFP_DA_CU
2774  * 1    SFP_SR
2775  * 2    SFP_LR
2776  * 3    SFP_DA_CU_CORE0 - 82599-specific
2777  * 4    SFP_DA_CU_CORE1 - 82599-specific
2778  * 5    SFP_SR/LR_CORE0 - 82599-specific
2779  * 6    SFP_SR/LR_CORE1 - 82599-specific
2780  */
2781 enum ixgbe_sfp_type {
2782         ixgbe_sfp_type_da_cu = 0,
2783         ixgbe_sfp_type_sr = 1,
2784         ixgbe_sfp_type_lr = 2,
2785         ixgbe_sfp_type_da_cu_core0 = 3,
2786         ixgbe_sfp_type_da_cu_core1 = 4,
2787         ixgbe_sfp_type_srlr_core0 = 5,
2788         ixgbe_sfp_type_srlr_core1 = 6,
2789         ixgbe_sfp_type_da_act_lmt_core0 = 7,
2790         ixgbe_sfp_type_da_act_lmt_core1 = 8,
2791         ixgbe_sfp_type_1g_cu_core0 = 9,
2792         ixgbe_sfp_type_1g_cu_core1 = 10,
2793         ixgbe_sfp_type_1g_sx_core0 = 11,
2794         ixgbe_sfp_type_1g_sx_core1 = 12,
2795         ixgbe_sfp_type_not_present = 0xFFFE,
2796         ixgbe_sfp_type_unknown = 0xFFFF
2797 };
2798
2799 enum ixgbe_media_type {
2800         ixgbe_media_type_unknown = 0,
2801         ixgbe_media_type_fiber,
2802         ixgbe_media_type_fiber_qsfp,
2803         ixgbe_media_type_fiber_lco,
2804         ixgbe_media_type_copper,
2805         ixgbe_media_type_backplane,
2806         ixgbe_media_type_cx4,
2807         ixgbe_media_type_virtual
2808 };
2809
2810 /* Flow Control Settings */
2811 enum ixgbe_fc_mode {
2812         ixgbe_fc_none = 0,
2813         ixgbe_fc_rx_pause,
2814         ixgbe_fc_tx_pause,
2815         ixgbe_fc_full,
2816         ixgbe_fc_default
2817 };
2818
2819 /* Smart Speed Settings */
2820 #define IXGBE_SMARTSPEED_MAX_RETRIES    3
2821 enum ixgbe_smart_speed {
2822         ixgbe_smart_speed_auto = 0,
2823         ixgbe_smart_speed_on,
2824         ixgbe_smart_speed_off
2825 };
2826
2827 /* PCI bus types */
2828 enum ixgbe_bus_type {
2829         ixgbe_bus_type_unknown = 0,
2830         ixgbe_bus_type_pci,
2831         ixgbe_bus_type_pcix,
2832         ixgbe_bus_type_pci_express,
2833         ixgbe_bus_type_reserved
2834 };
2835
2836 /* PCI bus speeds */
2837 enum ixgbe_bus_speed {
2838         ixgbe_bus_speed_unknown = 0,
2839         ixgbe_bus_speed_33      = 33,
2840         ixgbe_bus_speed_66      = 66,
2841         ixgbe_bus_speed_100     = 100,
2842         ixgbe_bus_speed_120     = 120,
2843         ixgbe_bus_speed_133     = 133,
2844         ixgbe_bus_speed_2500    = 2500,
2845         ixgbe_bus_speed_5000    = 5000,
2846         ixgbe_bus_speed_8000    = 8000,
2847         ixgbe_bus_speed_reserved
2848 };
2849
2850 /* PCI bus widths */
2851 enum ixgbe_bus_width {
2852         ixgbe_bus_width_unknown = 0,
2853         ixgbe_bus_width_pcie_x1 = 1,
2854         ixgbe_bus_width_pcie_x2 = 2,
2855         ixgbe_bus_width_pcie_x4 = 4,
2856         ixgbe_bus_width_pcie_x8 = 8,
2857         ixgbe_bus_width_32      = 32,
2858         ixgbe_bus_width_64      = 64,
2859         ixgbe_bus_width_reserved
2860 };
2861
2862 struct ixgbe_addr_filter_info {
2863         u32 num_mc_addrs;
2864         u32 rar_used_count;
2865         u32 mta_in_use;
2866         u32 overflow_promisc;
2867         bool user_set_promisc;
2868 };
2869
2870 /* Bus parameters */
2871 struct ixgbe_bus_info {
2872         enum ixgbe_bus_speed speed;
2873         enum ixgbe_bus_width width;
2874         enum ixgbe_bus_type type;
2875
2876         u16 func;
2877         u16 lan_id;
2878 };
2879
2880 /* Flow control parameters */
2881 struct ixgbe_fc_info {
2882         u32 high_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl High-water */
2883         u32 low_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl Low-water */
2884         u16 pause_time; /* Flow Control Pause timer */
2885         bool send_xon; /* Flow control send XON */
2886         bool strict_ieee; /* Strict IEEE mode */
2887         bool disable_fc_autoneg; /* Do not autonegotiate FC */
2888         bool fc_was_autonegged; /* Is current_mode the result of autonegging? */
2889         enum ixgbe_fc_mode current_mode; /* FC mode in effect */
2890         enum ixgbe_fc_mode requested_mode; /* FC mode requested by caller */
2891 };
2892
2893 /* Statistics counters collected by the MAC */
2894 struct ixgbe_hw_stats {
2895         u64 crcerrs;
2896         u64 illerrc;
2897         u64 errbc;
2898         u64 mspdc;
2899         u64 mpctotal;
2900         u64 mpc[8];
2901         u64 mlfc;
2902         u64 mrfc;
2903         u64 rlec;
2904         u64 lxontxc;
2905         u64 lxonrxc;
2906         u64 lxofftxc;
2907         u64 lxoffrxc;
2908         u64 pxontxc[8];
2909         u64 pxonrxc[8];
2910         u64 pxofftxc[8];
2911         u64 pxoffrxc[8];
2912         u64 prc64;
2913         u64 prc127;
2914         u64 prc255;
2915         u64 prc511;
2916         u64 prc1023;
2917         u64 prc1522;
2918         u64 gprc;
2919         u64 bprc;
2920         u64 mprc;
2921         u64 gptc;
2922         u64 gorc;
2923         u64 gotc;
2924         u64 rnbc[8];
2925         u64 ruc;
2926         u64 rfc;
2927         u64 roc;
2928         u64 rjc;
2929         u64 mngprc;
2930         u64 mngpdc;
2931         u64 mngptc;
2932         u64 tor;
2933         u64 tpr;
2934         u64 tpt;
2935         u64 ptc64;
2936         u64 ptc127;
2937         u64 ptc255;
2938         u64 ptc511;
2939         u64 ptc1023;
2940         u64 ptc1522;
2941         u64 mptc;
2942         u64 bptc;
2943         u64 xec;
2944         u64 qprc[16];
2945         u64 qptc[16];
2946         u64 qbrc[16];
2947         u64 qbtc[16];
2948         u64 qprdc[16];
2949         u64 pxon2offc[8];
2950         u64 fdirustat_add;
2951         u64 fdirustat_remove;
2952         u64 fdirfstat_fadd;
2953         u64 fdirfstat_fremove;
2954         u64 fdirmatch;
2955         u64 fdirmiss;
2956         u64 fccrc;
2957         u64 fclast;
2958         u64 fcoerpdc;
2959         u64 fcoeprc;
2960         u64 fcoeptc;
2961         u64 fcoedwrc;
2962         u64 fcoedwtc;
2963         u64 fcoe_noddp;
2964         u64 fcoe_noddp_ext_buff;
2965         u64 ldpcec;
2966         u64 pcrc8ec;
2967         u64 b2ospc;
2968         u64 b2ogprc;
2969         u64 o2bgptc;
2970         u64 o2bspc;
2971 };
2972
2973 /* forward declaration */
2974 struct ixgbe_hw;
2975
2976 /* iterator type for walking multicast address lists */
2977 typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr,
2978                                   u32 *vmdq);
2979
2980 /* Function pointer table */
2981 struct ixgbe_eeprom_operations {
2982         s32 (*init_params)(struct ixgbe_hw *);
2983         s32 (*read)(struct ixgbe_hw *, u16, u16 *);
2984         s32 (*read_buffer)(struct ixgbe_hw *, u16, u16, u16 *);
2985         s32 (*write)(struct ixgbe_hw *, u16, u16);
2986         s32 (*write_buffer)(struct ixgbe_hw *, u16, u16, u16 *);
2987         s32 (*validate_checksum)(struct ixgbe_hw *, u16 *);
2988         s32 (*update_checksum)(struct ixgbe_hw *);
2989         u16 (*calc_checksum)(struct ixgbe_hw *);
2990 };
2991
2992 struct ixgbe_mac_operations {
2993         s32 (*init_hw)(struct ixgbe_hw *);
2994         s32 (*reset_hw)(struct ixgbe_hw *);
2995         s32 (*start_hw)(struct ixgbe_hw *);
2996         s32 (*clear_hw_cntrs)(struct ixgbe_hw *);
2997         enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);
2998         u32 (*get_supported_physical_layer)(struct ixgbe_hw *);
2999         s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *);
3000         s32 (*get_san_mac_addr)(struct ixgbe_hw *, u8 *);
3001         s32 (*set_san_mac_addr)(struct ixgbe_hw *, u8 *);
3002         s32 (*get_device_caps)(struct ixgbe_hw *, u16 *);
3003         s32 (*get_wwn_prefix)(struct ixgbe_hw *, u16 *, u16 *);
3004         s32 (*get_fcoe_boot_status)(struct ixgbe_hw *, u16 *);
3005         s32 (*stop_adapter)(struct ixgbe_hw *);
3006         s32 (*get_bus_info)(struct ixgbe_hw *);
3007         void (*set_lan_id)(struct ixgbe_hw *);
3008         s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*);
3009         s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8);
3010         s32 (*setup_sfp)(struct ixgbe_hw *);
3011         s32 (*enable_rx_dma)(struct ixgbe_hw *, u32);
3012         s32 (*disable_sec_rx_path)(struct ixgbe_hw *);
3013         s32 (*enable_sec_rx_path)(struct ixgbe_hw *);
3014         s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u16);
3015         void (*release_swfw_sync)(struct ixgbe_hw *, u16);
3016
3017         /* Link */
3018         void (*disable_tx_laser)(struct ixgbe_hw *);
3019         void (*enable_tx_laser)(struct ixgbe_hw *);
3020         void (*flap_tx_laser)(struct ixgbe_hw *);
3021         s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool, bool);
3022         s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);
3023         s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *,
3024                                      bool *);
3025
3026         /* Packet Buffer manipulation */
3027         void (*setup_rxpba)(struct ixgbe_hw *, int, u32, int);
3028
3029         /* LED */
3030         s32 (*led_on)(struct ixgbe_hw *, u32);
3031         s32 (*led_off)(struct ixgbe_hw *, u32);
3032         s32 (*blink_led_start)(struct ixgbe_hw *, u32);
3033         s32 (*blink_led_stop)(struct ixgbe_hw *, u32);
3034
3035         /* RAR, Multicast, VLAN */
3036         s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32);
3037         s32 (*set_uc_addr)(struct ixgbe_hw *, u32, u8 *);
3038         s32 (*clear_rar)(struct ixgbe_hw *, u32);
3039         s32 (*insert_mac_addr)(struct ixgbe_hw *, u8 *, u32);
3040         s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32);
3041         s32 (*set_vmdq_san_mac)(struct ixgbe_hw *, u32);
3042         s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32);
3043         s32 (*init_rx_addrs)(struct ixgbe_hw *);
3044         s32 (*update_uc_addr_list)(struct ixgbe_hw *, u8 *, u32,
3045                                    ixgbe_mc_addr_itr);
3046         s32 (*update_mc_addr_list)(struct ixgbe_hw *, u8 *, u32,
3047                                    ixgbe_mc_addr_itr, bool clear);
3048         s32 (*enable_mc)(struct ixgbe_hw *);
3049         s32 (*disable_mc)(struct ixgbe_hw *);
3050         s32 (*clear_vfta)(struct ixgbe_hw *);
3051         s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool);
3052         s32 (*set_vlvf)(struct ixgbe_hw *, u32, u32, bool, bool *);
3053         s32 (*init_uta_tables)(struct ixgbe_hw *);
3054         void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int);
3055         void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int);
3056
3057         /* Flow Control */
3058         s32 (*fc_enable)(struct ixgbe_hw *);
3059
3060         /* Manageability interface */
3061         s32 (*set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8);
3062         s32 (*get_thermal_sensor_data)(struct ixgbe_hw *);
3063         s32 (*init_thermal_sensor_thresh)(struct ixgbe_hw *hw);
3064 };
3065
3066 struct ixgbe_phy_operations {
3067         s32 (*identify)(struct ixgbe_hw *);
3068         s32 (*identify_sfp)(struct ixgbe_hw *);
3069         s32 (*init)(struct ixgbe_hw *);
3070         s32 (*reset)(struct ixgbe_hw *);
3071         s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *);
3072         s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16);
3073         s32 (*setup_link)(struct ixgbe_hw *);
3074         s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool,
3075                                 bool);
3076         s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);
3077         s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *);
3078         s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *);
3079         s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8);
3080         s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *);
3081         s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8);
3082         void (*i2c_bus_clear)(struct ixgbe_hw *);
3083         s32 (*check_overtemp)(struct ixgbe_hw *);
3084 };
3085
3086 struct ixgbe_eeprom_info {
3087         struct ixgbe_eeprom_operations ops;
3088         enum ixgbe_eeprom_type type;
3089         u32 semaphore_delay;
3090         u16 word_size;
3091         u16 address_bits;
3092         u16 word_page_size;
3093 };
3094
3095 #define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED       0x01
3096 struct ixgbe_mac_info {
3097         struct ixgbe_mac_operations ops;
3098         enum ixgbe_mac_type type;
3099         u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
3100         u8 perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
3101         u8 san_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
3102         /* prefix for World Wide Node Name (WWNN) */
3103         u16 wwnn_prefix;
3104         /* prefix for World Wide Port Name (WWPN) */
3105         u16 wwpn_prefix;
3106 #define IXGBE_MAX_MTA                   128
3107         u32 mta_shadow[IXGBE_MAX_MTA];
3108         s32 mc_filter_type;
3109         u32 mcft_size;
3110         u32 vft_size;
3111         u32 num_rar_entries;
3112         u32 rar_highwater;
3113         u32 rx_pb_size;
3114         u32 max_tx_queues;
3115         u32 max_rx_queues;
3116         u32 orig_autoc;
3117         u8  san_mac_rar_index;
3118         u32 orig_autoc2;
3119         u16 max_msix_vectors;
3120         bool arc_subsystem_valid;
3121         bool orig_link_settings_stored;
3122         bool autotry_restart;
3123         u8 flags;
3124         struct ixgbe_thermal_sensor_data  thermal_sensor_data;
3125 };
3126
3127 struct ixgbe_phy_info {
3128         struct ixgbe_phy_operations ops;
3129         enum ixgbe_phy_type type;
3130         u32 addr;
3131         u32 id;
3132         enum ixgbe_sfp_type sfp_type;
3133         bool sfp_setup_needed;
3134         u32 revision;
3135         enum ixgbe_media_type media_type;
3136         bool reset_disable;
3137         ixgbe_autoneg_advertised autoneg_advertised;
3138         enum ixgbe_smart_speed smart_speed;
3139         bool smart_speed_active;
3140         bool multispeed_fiber;
3141         bool reset_if_overtemp;
3142         bool qsfp_shared_i2c_bus;
3143 };
3144
3145 #include "ixgbe_mbx.h"
3146
3147 struct ixgbe_mbx_operations {
3148         void (*init_params)(struct ixgbe_hw *hw);
3149         s32  (*read)(struct ixgbe_hw *, u32 *, u16,  u16);
3150         s32  (*write)(struct ixgbe_hw *, u32 *, u16, u16);
3151         s32  (*read_posted)(struct ixgbe_hw *, u32 *, u16,  u16);
3152         s32  (*write_posted)(struct ixgbe_hw *, u32 *, u16, u16);
3153         s32  (*check_for_msg)(struct ixgbe_hw *, u16);
3154         s32  (*check_for_ack)(struct ixgbe_hw *, u16);
3155         s32  (*check_for_rst)(struct ixgbe_hw *, u16);
3156 };
3157
3158 struct ixgbe_mbx_stats {
3159         u32 msgs_tx;
3160         u32 msgs_rx;
3161
3162         u32 acks;
3163         u32 reqs;
3164         u32 rsts;
3165 };
3166
3167 struct ixgbe_mbx_info {
3168         struct ixgbe_mbx_operations ops;
3169         struct ixgbe_mbx_stats stats;
3170         u32 timeout;
3171         u32 udelay;
3172         u32 v2p_mailbox;
3173         u16 size;
3174 };
3175
3176 struct ixgbe_hw {
3177         u8 __iomem *hw_addr;
3178         void *back;
3179         struct ixgbe_mac_info mac;
3180         struct ixgbe_addr_filter_info addr_ctrl;
3181         struct ixgbe_fc_info fc;
3182         struct ixgbe_phy_info phy;
3183         struct ixgbe_eeprom_info eeprom;
3184         struct ixgbe_bus_info bus;
3185         struct ixgbe_mbx_info mbx;
3186         u16 device_id;
3187         u16 vendor_id;
3188         u16 subsystem_device_id;
3189         u16 subsystem_vendor_id;
3190         u8 revision_id;
3191         bool adapter_stopped;
3192         bool force_full_reset;
3193         bool allow_unsupported_sfp;
3194 };
3195
3196 #define ixgbe_call_func(hw, func, params, error) \
3197                 (func != NULL) ? func params : error
3198
3199
3200 /* Error Codes */
3201 #define IXGBE_ERR_EEPROM                        -1
3202 #define IXGBE_ERR_EEPROM_CHECKSUM               -2
3203 #define IXGBE_ERR_PHY                           -3
3204 #define IXGBE_ERR_CONFIG                        -4
3205 #define IXGBE_ERR_PARAM                         -5
3206 #define IXGBE_ERR_MAC_TYPE                      -6
3207 #define IXGBE_ERR_UNKNOWN_PHY                   -7
3208 #define IXGBE_ERR_LINK_SETUP                    -8
3209 #define IXGBE_ERR_ADAPTER_STOPPED               -9
3210 #define IXGBE_ERR_INVALID_MAC_ADDR              -10
3211 #define IXGBE_ERR_DEVICE_NOT_SUPPORTED          -11
3212 #define IXGBE_ERR_MASTER_REQUESTS_PENDING       -12
3213 #define IXGBE_ERR_INVALID_LINK_SETTINGS         -13
3214 #define IXGBE_ERR_AUTONEG_NOT_COMPLETE          -14
3215 #define IXGBE_ERR_RESET_FAILED                  -15
3216 #define IXGBE_ERR_SWFW_SYNC                     -16
3217 #define IXGBE_ERR_PHY_ADDR_INVALID              -17
3218 #define IXGBE_ERR_I2C                           -18
3219 #define IXGBE_ERR_SFP_NOT_SUPPORTED             -19
3220 #define IXGBE_ERR_SFP_NOT_PRESENT               -20
3221 #define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT       -21
3222 #define IXGBE_ERR_NO_SAN_ADDR_PTR               -22
3223 #define IXGBE_ERR_FDIR_REINIT_FAILED            -23
3224 #define IXGBE_ERR_EEPROM_VERSION                -24
3225 #define IXGBE_ERR_NO_SPACE                      -25
3226 #define IXGBE_ERR_OVERTEMP                      -26
3227 #define IXGBE_ERR_FC_NOT_NEGOTIATED             -27
3228 #define IXGBE_ERR_FC_NOT_SUPPORTED              -28
3229 #define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE        -30
3230 #define IXGBE_ERR_PBA_SECTION                   -31
3231 #define IXGBE_ERR_INVALID_ARGUMENT              -32
3232 #define IXGBE_ERR_HOST_INTERFACE_COMMAND        -33
3233 #define IXGBE_ERR_OUT_OF_MEM                    -34
3234
3235 #define IXGBE_NOT_IMPLEMENTED                   0x7FFFFFFF
3236
3237 #define UNREFERENCED_XPARAMETER
3238
3239 #endif /* _IXGBE_TYPE_H_ */