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1#/** @file\r
2# ARM processor package.\r
3#\r
d6ebcab7 4# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>\r
c32aaba9 5# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r
8bbf0f09 6#\r
d6ebcab7 7# This program and the accompanying materials\r
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8# are licensed and made available under the terms and conditions of the BSD License\r
9# which accompanies this distribution. The full text of the license may be found at\r
10# http://opensource.org/licenses/bsd-license.php\r
11#\r
12# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
13# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
14#\r
15#**/\r
16\r
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17[Defines]\r
18 DEC_SPECIFICATION = 0x00010005\r
19 PACKAGE_NAME = ArmPkg\r
20 PACKAGE_GUID = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F\r
21 PACKAGE_VERSION = 0.1\r
22\r
23################################################################################\r
24#\r
25# Include Section - list of Include Paths that are provided by this package.\r
26# Comments are used for Keywords and Module Types.\r
27#\r
28# Supported Module Types:\r
29# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r
30#\r
31################################################################################\r
32[Includes.common]\r
33 Include # Root include for the package\r
34\r
35[LibraryClasses.common]\r
8bbf0f09 36 ArmLib|Include/Library/ArmLib.h\r
2ef2b01e 37 SemihostLib|Include/Library/Semihosting.h\r
8bbf0f09 38 UncachedMemoryAllocationLib|Include/Library/UncachedMemoryAllocationLib.h\r
11c20f4e 39 DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h\r
097bd461 40 ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h\r
c32aaba9 41\r
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42[Guids.common]\r
43 gArmTokenSpaceGuid = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }\r
44\r
44788bae 45 ## ARM MPCore table\r
46 # Include/Guid/ArmMpCoreInfo.h\r
47 gArmMpCoreInfoGuid = { 0xa4ee0728, 0xe5d7, 0x4ac5, {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }\r
48\r
49[Ppis]\r
50 ## Include/Ppi/ArmMpCoreInfo.h\r
51 gArmMpCoreInfoPpiGuid = { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }\r
52\r
2ef2b01e 53[Protocols.common]\r
8bbf0f09 54 gVirtualUncachedPagesProtocolGuid = { 0xAD651C7D, 0x3C22, 0x4DBF, { 0x92, 0xe8, 0x38, 0xa7, 0xcd, 0xae, 0x87, 0xb2 } }\r
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55\r
56[PcdsFeatureFlag.common]\r
57 gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE|BOOLEAN|0x00000001\r
58\r
1bfda055 59 # On ARM Architecture with the Security Extension, the address for the\r
60 # Vector Table can be mapped anywhere in the memory map. It means we can\r
61 # point the Exception Vector Table to its location in CpuDxe.\r
62 # By default we copy the Vector Table at PcdGet32(PcdCpuVectorBaseAddress)\r
63 gArmTokenSpaceGuid.PcdRelocateVectorTable|TRUE|BOOLEAN|0x00000022\r
eeec69c5 64 # Set this PCD to TRUE if the Exception Vector is changed to add debugger support before\r
65 # it has been configured by the CPU DXE\r
66 gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032\r
c32aaba9 67\r
bc87b507 68 # Define if the Power State Coordination Interface (PSCI) is supported by the Platform Trusted Firmware\r
69 gArmTokenSpaceGuid.PcdArmPsciSupport|FALSE|BOOLEAN|0x00000033\r
c32aaba9 70\r
2ef2b01e 71[PcdsFixedAtBuild.common]\r
12c5ae23 72 gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006\r
73\r
1bfda055 74 # This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file.\r
75 # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.\r
76 gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024\r
77\r
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78 gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000080000000|UINT64|0x00000002\r
79 gArmTokenSpaceGuid.PcdArmCacheOperationThreshold|1024|UINT32|0x00000003\r
5a4b8c6a 80 gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT32|0x00000004\r
2ef2b01e 81 gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005\r
c32aaba9 82\r
1bfda055 83 #\r
c32aaba9 84 # ARM Generic Interrupt Controller\r
1bfda055 85 #\r
86 gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT32|0x0000000C\r
87 gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT32|0x0000000D\r
be613c8b 88 gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025\r
1bfda055 89\r
90 #\r
262a9b04 91 # ARM Secure Firmware PCDs\r
1bfda055 92 #\r
93 gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT32|0x00000015\r
94 gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016\r
1ad14bc8 95 gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT32|0x0000002F\r
96 gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030\r
1bfda055 97\r
262a9b04 98 #\r
99 # ARM Normal (or Non Secure) Firmware PCDs\r
100 #\r
f92b93c9 101 gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT32|0x0000002B\r
102 gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C\r
103 gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT32|0x0000002D\r
104 gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E\r
c32aaba9 105\r
7245b435 106 #\r
107 # ARM Hypervisor Firmware PCDs\r
c32aaba9 108 #\r
7245b435 109 gArmTokenSpaceGuid.PcdHypFdBaseAddress|0|UINT32|0x0000003A\r
110 gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B\r
111 gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C\r
112 gArmTokenSpaceGuid.PcdHypFvSize|0|UINT32|0x0000003D\r
d6dc67ba 113\r
964680c1 114 # System Memory (DRAM): These PCDs define the region of in-built system memory\r
115 # Some platforms can get DRAM extensions, these additional regions will be declared\r
c32aaba9 116 # to UEFI by ArmPlatformLib\r
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117 gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029\r
118 gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A\r
964680c1 119\r
0787bc61 120 # Use ClusterId + CoreId to identify the PrimaryCore\r
121 gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031\r
c32aaba9 122 # The Primary Core is ClusterId[0] & CoreId[0]\r
0787bc61 123 gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037\r
124\r
1bfda055 125 #\r
126 # ARM L2x0 PCDs\r
127 #\r
128 gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B\r
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129\r
130 #\r
1bfda055 131 # BdsLib\r
132 #\r
133 gArmTokenSpaceGuid.PcdArmMachineType|0|UINT32|0x0000001E\r
a355a365 134 # The compressed Linux kernel is expected to be under 128MB from the beginning of the System Memory\r
135 gArmTokenSpaceGuid.PcdArmLinuxKernelMaxOffset|0x08000000|UINT32|0x0000001F\r
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136 # Maximum file size for TFTP servers that do not support 'tsize' extension\r
137 gArmTokenSpaceGuid.PcdMaxTftpFileSize|0x01000000|UINT32|0x00000000\r
1bfda055 138\r
da9675a2 139 #\r
140 # ARM Architectural Timer\r
141 #\r
142 gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034\r
143 # ARM Architectural Timer Interrupt(GIC PPI) number\r
c32aaba9 144 gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035\r
da9675a2 145 gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036\r
387653a4 146\r
147[PcdsFixedAtBuild.ARM]\r
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148 #\r
149 # ARM Security Extension\r
150 #\r
151\r
152 # Secure Configuration Register\r
153 # - BIT0 : NS - Non Secure bit\r
154 # - BIT1 : IRQ Handler\r
155 # - BIT2 : FIQ Handler\r
156 # - BIT3 : EA - External Abort\r
157 # - BIT4 : FW - F bit writable\r
158 # - BIT5 : AW - A bit writable\r
159 # - BIT6 : nET - Not Early Termination\r
160 # - BIT7 : SCD - Secure Monitor Call Disable\r
161 # - BIT8 : HCE - Hyp Call enable\r
162 # - BIT9 : SIF - Secure Instruction Fetch\r
163 # 0x31 = NS | EA | FW\r
164 gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038\r
165\r
387653a4 166 # By default we do not do a transition to non-secure mode\r
167 gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E\r
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168\r
169 # The Linux ATAGs are expected to be under 0x4000 (16KB) from the beginning of the System Memory\r
170 gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset|0x4000|UINT32|0x00000020\r
171\r
387653a4 172 # If the fixed FDT address is not available, then it should be loaded below the kernel.\r
173 # The recommendation from the Linux kernel is to have the FDT below 16KB.\r
174 # (see the kernel doc: Documentation/arm/Booting)\r
175 gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x4000|UINT32|0x00000023\r
176 # The FDT blob must be loaded at a 64bit aligned address.\r
177 gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x8|UINT32|0x00000026\r
25402f5d 178\r
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179 # Non Secure Access Control Register\r
180 # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality\r
181 # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31\r
182 # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable\r
183 # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable\r
184 # 0xC00 = cp10 | cp11\r
185 gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039\r
186\r
25402f5d 187[PcdsFixedAtBuild.AARCH64]\r
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188 #\r
189 # AArch64 Security Extension\r
190 #\r
191\r
192 # Secure Configuration Register\r
193 # - BIT0 : NS - Non Secure bit\r
194 # - BIT1 : IRQ Handler\r
195 # - BIT2 : FIQ Handler\r
196 # - BIT3 : EA - External Abort\r
197 # - BIT4 : FW - F bit writable\r
198 # - BIT5 : AW - A bit writable\r
199 # - BIT6 : nET - Not Early Termination\r
200 # - BIT7 : SCD - Secure Monitor Call Disable\r
201 # - BIT8 : HCE - Hyp Call enable\r
202 # - BIT9 : SIF - Secure Instruction Fetch\r
203 # - BIT10: RW - Register width control for lower exception levels\r
204 # - BIT11: SIF - Enables Secure EL1 access to EL1 Architectural Timer\r
205 # - BIT12: TWI - Trap WFI\r
206 # - BIT13: TWE - Trap WFE\r
207 # 0x501 = NS | HCE | RW\r
208 gArmTokenSpaceGuid.PcdArmScr|0x501|UINT32|0x00000038\r
209\r
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210 # By default we do transition to EL2 non-secure mode with Stack for EL2.\r
211 # Mode Description Bits\r
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212 # NS EL2 SP2 all interrupts disabled = 0x3c9\r
213 # NS EL1 SP1 all interrupts disabled = 0x3c5\r
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214 # Other modes include using SP0 or switching to Aarch32, but these are\r
215 # not currently supported.\r
216 gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E\r
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217 # If the fixed FDT address is not available, then it should be loaded above the kernel.\r
218 # The recommendation from the AArch64 Linux kernel is to have the FDT below 512MB.\r
219 # (see the kernel doc: Documentation/arm64/booting.txt)\r
220 gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x20000000|UINT32|0x00000023\r
221 # The FDT blob must be loaded at a 2MB aligned address.\r
222 gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x00200000|UINT32|0x00000026\r