[mirror_edk2.git] / ArmPkg / ArmPkg.dec

#/** @file\r
# ARM processor package.\r
#\r
# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>\r
# Copyright (c) 2011, ARM Limited. All rights reserved.\r
#\r
#    This program and the accompanying materials\r
#    are licensed and made available under the terms and conditions of the BSD License\r
#    which accompanies this distribution. The full text of the license may be found at\r
#    http://opensource.org/licenses/bsd-license.php\r
#\r
#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
#\r
#**/\r
\r
[Defines]\r
  DEC_SPECIFICATION              = 0x00010005\r
  PACKAGE_NAME                   = ArmPkg\r
  PACKAGE_GUID                   = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F\r
  PACKAGE_VERSION                = 0.1\r
\r
################################################################################\r
#\r
# Include Section - list of Include Paths that are provided by this package.\r
#                   Comments are used for Keywords and Module Types.\r
#\r
# Supported Module Types:\r
#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r
#\r
################################################################################\r
[Includes.common]\r
  Include                        # Root include for the package\r
\r
[LibraryClasses.common]\r
  ArmLib|Include/Library/ArmLib.h\r
  SemihostLib|Include/Library/Semihosting.h\r
  UncachedMemoryAllocationLib|Include/Library/UncachedMemoryAllocationLib.h\r
  DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h\r
  ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h\r
  \r
[Guids.common]\r
  gArmTokenSpaceGuid       = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }\r
\r
  ## ARM MPCore table\r
  # Include/Guid/ArmMpCoreInfo.h\r
  gArmMpCoreInfoGuid = { 0xa4ee0728, 0xe5d7, 0x4ac5,  {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }\r
\r
[Ppis]\r
  ## Include/Ppi/ArmMpCoreInfo.h\r
  gArmMpCoreInfoPpiGuid = { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }\r
\r
[Protocols.common]\r
  gVirtualUncachedPagesProtocolGuid = { 0xAD651C7D, 0x3C22, 0x4DBF, { 0x92, 0xe8, 0x38, 0xa7, 0xcd, 0xae, 0x87, 0xb2 } }\r
\r
[PcdsFeatureFlag.common]\r
  gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE|BOOLEAN|0x00000001\r
\r
  # On ARM Architecture with the Security Extension, the address for the\r
  # Vector Table can be mapped anywhere in the memory map. It means we can\r
  # point the Exception Vector Table to its location in CpuDxe.\r
  # By default we copy the Vector Table at  PcdGet32(PcdCpuVectorBaseAddress)\r
  gArmTokenSpaceGuid.PcdRelocateVectorTable|TRUE|BOOLEAN|0x00000022\r
  # Set this PCD to TRUE if the Exception Vector is changed to add debugger support before\r
  # it has been configured by the CPU DXE\r
  gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032\r
  \r
  gArmTokenSpaceGuid.PcdEfiUncachedMemoryToStronglyOrdered|FALSE|BOOLEAN|0x00000025\r
\r
[PcdsFixedAtBuild.common]\r
  # This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file.\r
  # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.\r
  gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024\r
\r
  gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000080000000|UINT64|0x00000002\r
  gArmTokenSpaceGuid.PcdArmCacheOperationThreshold|1024|UINT32|0x00000003\r
  gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT32|0x00000004\r
  gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005\r
  \r
  #\r
  # ARM PL390 General Interrupt Controller\r
  #\r
  gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT32|0x0000000C\r
  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT32|0x0000000D\r
  gArmTokenSpaceGuid.PcdGicNumInterrupts|96|UINT32|0x00000023\r
\r
  #\r
  # ARM Secure Firmware PCDs\r
  #\r
  gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT32|0x00000015\r
  gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016\r
  gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT32|0x0000002F\r
  gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030\r
\r
  #\r
  # ARM Normal (or Non Secure) Firmware PCDs\r
  #\r
  gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT32|0x0000002B\r
  gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C\r
  gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT32|0x0000002D\r
  gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E\r
\r
  # System Memory (DRAM): These PCDs define the region of in-built system memory\r
  # Some platforms can get DRAM extensions, these additional regions will be declared\r
  # to UEFI by ArmPLatformPlib   \r
  gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT32|0x00000029\r
  gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT32|0x0000002A\r
\r
  # Use ClusterId + CoreId to identify the PrimaryCore\r
  gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031\r
  # The Primary Core is ClusterId[0] & CoreId[0] \r
  gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037\r
\r
  #\r
  # ARM MPCore MailBox PCDs\r
  #\r
  # Address to Set/Get to Mailbox in Multicore system\r
  gArmTokenSpaceGuid.PcdMPCoreMailboxSetAddress|0|UINT32|0x00000017\r
  gArmTokenSpaceGuid.PcdMPCoreMailboxGetAddress|0|UINT32|0x00000018\r
  # Address/Value to clear Mailbox in Multicore system\r
  gArmTokenSpaceGuid.PcdMPCoreMailboxClearAddress|0|UINT32|0x00000019\r
  gArmTokenSpaceGuid.PcdMPCoreMailboxClearValue|0|UINT32|0x0000001A\r
\r
  #\r
  # ARM L2x0 PCDs\r
  #\r
  gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B\r
  \r
  #\r
  # ARM PL390 General Interrupt Controller\r
  #\r
  gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT32|0x0000001C\r
  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT32|0x0000001D\r
  \r
  # \r
  # BdsLib\r
  #\r
  gArmTokenSpaceGuid.PcdArmMachineType|0|UINT32|0x0000001E\r
  # The compressed Linux kernel is expected to be under 128MB from the beginning of the System Memory\r
  gArmTokenSpaceGuid.PcdArmLinuxKernelMaxOffset|0x08000000|UINT32|0x0000001F\r
  # The Linux ATAGs are expected to be under 0x4000 (16KB) from the beginning of the System Memory\r
  gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset|0x4000|UINT32|0x00000020\r
\r
Commit	Line	Data
8bbf0f09 A	1	#/** @file\r
	2	# ARM processor package.\r
	3	#\r
d6ebcab7	4	# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>\r
44788bae	5	# Copyright (c) 2011, ARM Limited. All rights reserved.\r
8bbf0f09	6	#\r
d6ebcab7	7	# This program and the accompanying materials\r
8bbf0f09 A	8	# are licensed and made available under the terms and conditions of the BSD License\r
	9	# which accompanies this distribution. The full text of the license may be found at\r
	10	# http://opensource.org/licenses/bsd-license.php\r
	11	#\r
	12	# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	13	# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	14	#\r
	15	#**/\r
	16	\r
2ef2b01e A	17	[Defines]\r
	18	DEC_SPECIFICATION = 0x00010005\r
	19	PACKAGE_NAME = ArmPkg\r
	20	PACKAGE_GUID = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F\r
	21	PACKAGE_VERSION = 0.1\r
	22	\r
	23	################################################################################\r
	24	#\r
	25	# Include Section - list of Include Paths that are provided by this package.\r
	26	# Comments are used for Keywords and Module Types.\r
	27	#\r
	28	# Supported Module Types:\r
	29	# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r
	30	#\r
	31	################################################################################\r
	32	[Includes.common]\r
	33	Include # Root include for the package\r
	34	\r
	35	[LibraryClasses.common]\r
8bbf0f09	36	ArmLib\|Include/Library/ArmLib.h\r
2ef2b01e	37	SemihostLib\|Include/Library/Semihosting.h\r
8bbf0f09	38	UncachedMemoryAllocationLib\|Include/Library/UncachedMemoryAllocationLib.h\r
11c20f4e	39	DefaultExceptionHandlerLib\|Include/Library/DefaultExceptionHandlerLib.h\r
097bd461	40	ArmDisassemblerLib\|Include/Library/ArmDisassemblerLib.h\r
097bd461	41	\r
2ef2b01e A	42	[Guids.common]\r
	43	gArmTokenSpaceGuid = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }\r
	44	\r
44788bae	45	## ARM MPCore table\r
	46	# Include/Guid/ArmMpCoreInfo.h\r
	47	gArmMpCoreInfoGuid = { 0xa4ee0728, 0xe5d7, 0x4ac5, {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }\r
	48	\r
	49	[Ppis]\r
	50	## Include/Ppi/ArmMpCoreInfo.h\r
	51	gArmMpCoreInfoPpiGuid = { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }\r
	52	\r
2ef2b01e	53	[Protocols.common]\r
8bbf0f09	54	gVirtualUncachedPagesProtocolGuid = { 0xAD651C7D, 0x3C22, 0x4DBF, { 0x92, 0xe8, 0x38, 0xa7, 0xcd, 0xae, 0x87, 0xb2 } }\r
2ef2b01e A	55	\r
	56	[PcdsFeatureFlag.common]\r
	57	gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport\|FALSE\|BOOLEAN\|0x00000001\r
	58	\r
1bfda055	59	# On ARM Architecture with the Security Extension, the address for the\r
	60	# Vector Table can be mapped anywhere in the memory map. It means we can\r
	61	# point the Exception Vector Table to its location in CpuDxe.\r
	62	# By default we copy the Vector Table at PcdGet32(PcdCpuVectorBaseAddress)\r
	63	gArmTokenSpaceGuid.PcdRelocateVectorTable\|TRUE\|BOOLEAN\|0x00000022\r
eeec69c5	64	# Set this PCD to TRUE if the Exception Vector is changed to add debugger support before\r
	65	# it has been configured by the CPU DXE\r
	66	gArmTokenSpaceGuid.PcdDebuggerExceptionSupport\|FALSE\|BOOLEAN\|0x00000032\r
1bfda055	67	\r
1bfda055	68	gArmTokenSpaceGuid.PcdEfiUncachedMemoryToStronglyOrdered\|FALSE\|BOOLEAN\|0x00000025\r
1bfda055	69	\r
2ef2b01e	70	[PcdsFixedAtBuild.common]\r
1bfda055	71	# This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file.\r
	72	# Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.\r
	73	gArmTokenSpaceGuid.PcdVFPEnabled\|0\|UINT32\|0x00000024\r
	74	\r
2ef2b01e A	75	gArmTokenSpaceGuid.PcdArmUncachedMemoryMask\|0x0000000080000000\|UINT64\|0x00000002\r
2ef2b01e A	76	gArmTokenSpaceGuid.PcdArmCacheOperationThreshold\|1024\|UINT32\|0x00000003\r
5a4b8c6a	77	gArmTokenSpaceGuid.PcdCpuVectorBaseAddress\|0xffff0000\|UINT32\|0x00000004\r
2ef2b01e	78	gArmTokenSpaceGuid.PcdCpuResetAddress\|0x00000000\|UINT32\|0x00000005\r
1bfda055	79	\r
1bfda055	80	#\r
	81	# ARM PL390 General Interrupt Controller\r
	82	#\r
	83	gArmTokenSpaceGuid.PcdGicDistributorBase\|0\|UINT32\|0x0000000C\r
	84	gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase\|0\|UINT32\|0x0000000D\r
	85	gArmTokenSpaceGuid.PcdGicNumInterrupts\|96\|UINT32\|0x00000023\r
	86	\r
	87	#\r
262a9b04	88	# ARM Secure Firmware PCDs\r
1bfda055	89	#\r
	90	gArmTokenSpaceGuid.PcdSecureFdBaseAddress\|0\|UINT32\|0x00000015\r
	91	gArmTokenSpaceGuid.PcdSecureFdSize\|0\|UINT32\|0x00000016\r
1ad14bc8	92	gArmTokenSpaceGuid.PcdSecureFvBaseAddress\|0x0\|UINT32\|0x0000002F\r
1ad14bc8	93	gArmTokenSpaceGuid.PcdSecureFvSize\|0x0\|UINT32\|0x00000030\r
1bfda055	94	\r
262a9b04	95	#\r
	96	# ARM Normal (or Non Secure) Firmware PCDs\r
	97	#\r
f92b93c9	98	gArmTokenSpaceGuid.PcdFdBaseAddress\|0\|UINT32\|0x0000002B\r
	99	gArmTokenSpaceGuid.PcdFdSize\|0\|UINT32\|0x0000002C\r
	100	gArmTokenSpaceGuid.PcdFvBaseAddress\|0\|UINT32\|0x0000002D\r
	101	gArmTokenSpaceGuid.PcdFvSize\|0\|UINT32\|0x0000002E\r
262a9b04	102	\r
964680c1	103	# System Memory (DRAM): These PCDs define the region of in-built system memory\r
	104	# Some platforms can get DRAM extensions, these additional regions will be declared\r
	105	# to UEFI by ArmPLatformPlib \r
	106	gArmTokenSpaceGuid.PcdSystemMemoryBase\|0\|UINT32\|0x00000029\r
	107	gArmTokenSpaceGuid.PcdSystemMemorySize\|0\|UINT32\|0x0000002A\r
	108	\r
0787bc61	109	# Use ClusterId + CoreId to identify the PrimaryCore\r
	110	gArmTokenSpaceGuid.PcdArmPrimaryCoreMask\|0xF03\|UINT32\|0x00000031\r
	111	# The Primary Core is ClusterId[0] & CoreId[0] \r
	112	gArmTokenSpaceGuid.PcdArmPrimaryCore\|0\|UINT32\|0x00000037\r
	113	\r
1bfda055	114	#\r
	115	# ARM MPCore MailBox PCDs\r
	116	#\r
	117	# Address to Set/Get to Mailbox in Multicore system\r
	118	gArmTokenSpaceGuid.PcdMPCoreMailboxSetAddress\|0\|UINT32\|0x00000017\r
	119	gArmTokenSpaceGuid.PcdMPCoreMailboxGetAddress\|0\|UINT32\|0x00000018\r
	120	# Address/Value to clear Mailbox in Multicore system\r
	121	gArmTokenSpaceGuid.PcdMPCoreMailboxClearAddress\|0\|UINT32\|0x00000019\r
	122	gArmTokenSpaceGuid.PcdMPCoreMailboxClearValue\|0\|UINT32\|0x0000001A\r
	123	\r
	124	#\r
	125	# ARM L2x0 PCDs\r
	126	#\r
	127	gArmTokenSpaceGuid.PcdL2x0ControllerBase\|0\|UINT32\|0x0000001B\r
	128	\r
	129	#\r
	130	# ARM PL390 General Interrupt Controller\r
	131	#\r
	132	gArmTokenSpaceGuid.PcdGicDistributorBase\|0\|UINT32\|0x0000001C\r
	133	gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase\|0\|UINT32\|0x0000001D\r
	134	\r
	135	# \r
	136	# BdsLib\r
	137	#\r
	138	gArmTokenSpaceGuid.PcdArmMachineType\|0\|UINT32\|0x0000001E\r
a355a365	139	# The compressed Linux kernel is expected to be under 128MB from the beginning of the System Memory\r
	140	gArmTokenSpaceGuid.PcdArmLinuxKernelMaxOffset\|0x08000000\|UINT32\|0x0000001F\r
	141	# The Linux ATAGs are expected to be under 0x4000 (16KB) from the beginning of the System Memory\r
	142	gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset\|0x4000\|UINT32\|0x00000020\r
1bfda055	143	\r