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1 | //\r |
| 2 | // Copyright (c) 2011, ARM Limited. All rights reserved.\r |
| 3 | //\r |
| 4 | // This program and the accompanying materials\r |
| 5 | // are licensed and made available under the terms and conditions of the BSD License\r |
| 6 | // which accompanies this distribution. The full text of the license may be found at\r |
| 7 | // http://opensource.org/licenses/bsd-license.php\r |
| 8 | //\r |
| 9 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| 10 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
| 11 | //\r |
| 12 | //\r |
| 13 | \r |
| 14 | #include <Library/ArmCpuLib.h>\r |
| 15 | \r |
| 16 | .text\r |
| 17 | .align 3\r |
| 18 | \r |
| 19 | GCC_ASM_EXPORT(ArmCpuSynchronizeWait)\r |
| 20 | GCC_ASM_IMPORT(CArmCpuSynchronizeWait)\r |
| 21 | \r |
| 22 | // VOID\r |
| 23 | // ArmCpuSynchronizeWait (\r |
| 24 | // IN ARM_CPU_SYNCHRONIZE_EVENT Event\r |
| 25 | // );\r |
| 26 | ASM_PFX(ArmCpuSynchronizeWait):\r |
| 27 | cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT\r |
| 28 | // The SCU enabled is the event to tell us the Init Boot Memory is initialized\r |
| 29 | bx lr\r |
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30 | b ASM_PFX(CArmCpuSynchronizeWait)\r |
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31 | \r |
| 32 | \r |
| 33 | #if 0\r |
| 34 | GCC_ASM_EXPORT(ArmCpuSynchronizeWait)\r |
| 35 | GCC_ASM_EXPORT(ArmGetScuBaseAddress)\r |
| 36 | GCC_ASM_IMPORT(CArmCpuSynchronizeWait)\r |
| 37 | \r |
| 38 | // VOID\r |
| 39 | // ArmCpuSynchronizeWait (\r |
| 40 | // IN ARM_CPU_SYNCHRONIZE_EVENT Event\r |
| 41 | // );\r |
| 42 | ASM_PFX(ArmCpuSynchronizeWait):\r |
| 43 | cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT\r |
| 44 | // The SCU enabled is the event to tell us the Init Boot Memory is initialized\r |
| 45 | beq ArmWaitScuEnabled\r |
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46 | b ASM_PFX(CArmCpuSynchronizeWait)\r |
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47 | \r |
| 48 | // IN None\r |
| 49 | // OUT r0 = SCU Base Address\r |
| 50 | ASM_PFX(ArmGetScuBaseAddress):\r |
| 51 | // Read Configuration Base Address Register. ArmCBar cannot be called to get\r |
| 52 | // the Configuration BAR as a stack is not necessary setup. The SCU is at the\r |
| 53 | // offset 0x0000 from the Private Memory Region.\r |
| 54 | mrc p15, 4, r0, c15, c0, 0\r |
| 55 | bx lr\r |
| 56 | \r |
| 57 | ASM_PFX(ArmWaitScuEnabled):\r |
| 58 | // Read Configuration Base Address Register. ArmCBar cannot be called to get\r |
| 59 | // the Configuration BAR as a stack is not necessary setup. The SCU is at the\r |
| 60 | // offset 0x0000 from the Private Memory Region.\r |
| 61 | mrc p15, 4, r0, c15, c0, 0\r |
| 62 | add r0, r0, #A9_SCU_CONTROL_OFFSET\r |
| 63 | ldr r0, [r0]\r |
| 64 | cmp r0, #1\r |
| 65 | bne ArmWaitScuEnabled\r |
| 66 | bx lr\r |
| 67 | #endif\r |
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