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ArmPlatformPkg: Introduced 'ArmPlatformSecLib'
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3127615b 1/** @file\r
2\r
b1d41be7 3 Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
3127615b 4\r
5 This program and the accompanying materials\r
6 are licensed and made available under the terms and conditions of the BSD License\r
7 which accompanies this distribution. The full text of the license may be found at\r
8 http://opensource.org/licenses/bsd-license.php\r
9\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13**/\r
14\r
15#include <Base.h>\r
16#include <Library/ArmLib.h>\r
17#include <Library/ArmCpuLib.h>\r
3127615b 18#include <Library/IoLib.h>\r
19#include <Library/PcdLib.h>\r
20\r
21#include <Chipset/ArmCortexA9.h>\r
22\r
3127615b 23VOID\r
24ArmEnableScu (\r
25 VOID\r
26 )\r
27{\r
28 INTN ScuBase;\r
29\r
30 ScuBase = ArmGetScuBaseAddress();\r
31\r
32 // Invalidate all: write -1 to SCU Invalidate All register\r
33 MmioWrite32(ScuBase + A9_SCU_INVALL_OFFSET, 0xffffffff);\r
34 // Enable SCU\r
35 MmioWrite32(ScuBase + A9_SCU_CONTROL_OFFSET, 0x1);\r
36}\r
37\r
38VOID\r
39ArmCpuSetup (\r
40 IN UINTN MpId\r
41 )\r
42{\r
43 // Enable SWP instructions\r
44 ArmEnableSWPInstruction ();\r
45\r
46 // Enable program flow prediction, if supported.\r
47 ArmEnableBranchPrediction ();\r
48\r
49 // If MPCore then Enable the SCU\r
50 if (ArmIsMpCore()) {\r
51 ArmEnableScu ();\r
52 }\r
53}\r
54\r
55\r
56VOID\r
57ArmCpuSetupSmpNonSecure (\r
58 IN UINTN MpId\r
59 )\r
60{\r
61 INTN ScuBase;\r
62\r
63 ArmSetAuxCrBit (A9_FEATURE_SMP);\r
64\r
65 // Make the SCU accessible in Non Secure world\r
66 if (IS_PRIMARY_CORE(MpId)) {\r
67 ScuBase = ArmGetScuBaseAddress();\r
68\r
69 // Allow NS access to SCU register\r
70 MmioOr32 (ScuBase + A9_SCU_SACR_OFFSET, 0xf);\r
71 // Allow NS access to Private Peripherals\r
72 MmioOr32 (ScuBase + A9_SCU_SSACR_OFFSET, 0xfff);\r
73 }\r
74}\r