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3127615b | 1 | /** @file\r |
2 | \r | |
3 | Copyright (c) 2011, ARM Limited. All rights reserved.\r | |
4 | \r | |
5 | This program and the accompanying materials\r | |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | #include <Base.h>\r | |
16 | #include <Library/ArmLib.h>\r | |
17 | #include <Library/ArmCpuLib.h>\r | |
18 | #include <Library/ArmGicLib.h>\r | |
19 | #include <Library/IoLib.h>\r | |
20 | #include <Library/PcdLib.h>\r | |
21 | \r | |
22 | #include <Chipset/ArmCortexA9.h>\r | |
23 | \r | |
24 | VOID\r | |
25 | ArmCpuSynchronizeSignal (\r | |
26 | IN ARM_CPU_SYNCHRONIZE_EVENT Event\r | |
27 | )\r | |
28 | {\r | |
29 | if (Event == ARM_CPU_EVENT_BOOT_MEM_INIT) {\r | |
30 | // Do nothing, Cortex A9 secondary cores are waiting for the SCU to be\r | |
31 | // enabled (done by ArmCpuSetup()) as a way to know when the Init Boot\r | |
32 | // Mem as been initialized\r | |
33 | } else {\r | |
34 | // Send SGI to all Secondary core to wake them up from WFI state.\r | |
35 | ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);\r | |
36 | }\r | |
37 | }\r | |
38 | \r | |
39 | VOID\r | |
40 | CArmCpuSynchronizeWait (\r | |
41 | IN ARM_CPU_SYNCHRONIZE_EVENT Event\r | |
42 | )\r | |
43 | {\r | |
44 | // Waiting for the SGI from the primary core\r | |
45 | ArmCallWFI ();\r | |
46 | \r | |
47 | // Acknowledge the interrupt and send End of Interrupt signal.\r | |
48 | ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);\r | |
49 | }\r | |
50 | \r | |
51 | VOID\r | |
52 | ArmEnableScu (\r | |
53 | VOID\r | |
54 | )\r | |
55 | {\r | |
56 | INTN ScuBase;\r | |
57 | \r | |
58 | ScuBase = ArmGetScuBaseAddress();\r | |
59 | \r | |
60 | // Invalidate all: write -1 to SCU Invalidate All register\r | |
61 | MmioWrite32(ScuBase + A9_SCU_INVALL_OFFSET, 0xffffffff);\r | |
62 | // Enable SCU\r | |
63 | MmioWrite32(ScuBase + A9_SCU_CONTROL_OFFSET, 0x1);\r | |
64 | }\r | |
65 | \r | |
66 | VOID\r | |
67 | ArmCpuSetup (\r | |
68 | IN UINTN MpId\r | |
69 | )\r | |
70 | {\r | |
71 | // Enable SWP instructions\r | |
72 | ArmEnableSWPInstruction ();\r | |
73 | \r | |
74 | // Enable program flow prediction, if supported.\r | |
75 | ArmEnableBranchPrediction ();\r | |
76 | \r | |
77 | // If MPCore then Enable the SCU\r | |
78 | if (ArmIsMpCore()) {\r | |
79 | ArmEnableScu ();\r | |
80 | }\r | |
81 | }\r | |
82 | \r | |
83 | \r | |
84 | VOID\r | |
85 | ArmCpuSetupSmpNonSecure (\r | |
86 | IN UINTN MpId\r | |
87 | )\r | |
88 | {\r | |
89 | INTN ScuBase;\r | |
90 | \r | |
91 | ArmSetAuxCrBit (A9_FEATURE_SMP);\r | |
92 | \r | |
93 | // Make the SCU accessible in Non Secure world\r | |
94 | if (IS_PRIMARY_CORE(MpId)) {\r | |
95 | ScuBase = ArmGetScuBaseAddress();\r | |
96 | \r | |
97 | // Allow NS access to SCU register\r | |
98 | MmioOr32 (ScuBase + A9_SCU_SACR_OFFSET, 0xf);\r | |
99 | // Allow NS access to Private Peripherals\r | |
100 | MmioOr32 (ScuBase + A9_SCU_SSACR_OFFSET, 0xfff);\r | |
101 | }\r | |
102 | }\r |